JPH01236636A - Mounting process of electronic component - Google Patents

Mounting process of electronic component

Info

Publication number
JPH01236636A
JPH01236636A JP6430288A JP6430288A JPH01236636A JP H01236636 A JPH01236636 A JP H01236636A JP 6430288 A JP6430288 A JP 6430288A JP 6430288 A JP6430288 A JP 6430288A JP H01236636 A JPH01236636 A JP H01236636A
Authority
JP
Japan
Prior art keywords
electronic component
solder bumps
wiring board
wiring substrate
thermoplastic resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6430288A
Other languages
Japanese (ja)
Inventor
Kenji Murata
邑田 健治
Hiroshi Inoue
浩 井上
Toshiya Tanaka
俊哉 田中
Shinichi Kamitsuma
上妻 信一
Yasuo Kishi
岸 靖雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP6430288A priority Critical patent/JPH01236636A/en
Publication of JPH01236636A publication Critical patent/JPH01236636A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To simplify the mounting process by a method wherein the substrate of an electronic component and a wiring substrate are fixed with a thermoplastic resin of a melting point lower than that of solder bumps and then the electronic component and the wiring substrate are heated at a temperature higher than the melting point of the solder bumps to connect the electronic component with the wiring substrate. CONSTITUTION:A substrate 2 of an electronic component 1 and a wiring substrate 8 are fixed by a thermoplastic resin 15 in lower melting point than that of solder bumps 11a, 11b in the state where the solder bumps 11a, 11b formed on the electronic component 1 are brought into contact with the input terminals 10a, 10b of the wiring substrate 8 and then the electronic component 1 and the wiring substrate 8 are heated at the temperature higher than the melting point of the solder bumps 11a, 11b to connect the electronic component 1 with the wiring substrate 8. The softened thermoplastic resin 15 enters into the gap between the electronic component 1 and the wiring substrate 8 not to decrease said gap exceeding the required amount while the thermoplastic resin 15 sets to become a reinforcement when the heating process is terminated thus eliminating any later reinforcing process. Through these procedures, the mounting process can be simplified.

Description

【発明の詳細な説明】 G(J  産業上の利用分野 本発明は光信号t−電気信号に変換し7tり、光エネル
ギを電気エネルギに変換する光電′R換表装置どの電子
部品を配線基板に袋層する電子部品の取付方法に関する
Detailed Description of the Invention G(J Industrial Field of Application) The present invention is a photoelectric conversion device that converts optical signals into electrical signals and converts optical energy into electrical energy. This invention relates to a method for attaching electronic components to a bag.

(l:+)従来の技術 透光性結縁基板の一主面上に、膜伏尤電変換体と当該光
!変換体の光電変換出力を導出する複数の出力端子を配
線した光[変換素子は1例えば特公昭5 B−2182
7号公報に太陽電池への適用例が開示され、特開昭58
−31585号公報に光センサへの適用例が記載さnて
いる如く既に種々の用途への展開が試みられている。
(l:+) Conventional technology A film-containing electrical converter and the light! A light wire with a plurality of output terminals for deriving the photoelectric conversion output of the converter [conversion element is 1, for example, Japanese Patent Publication No. 5 B-2182
No. 7 discloses an example of application to solar cells, and
Applications to various applications have already been attempted, as an example of application to an optical sensor is described in Japanese Patent No. 31585.

これら光電変換素子の実用に際しては、一般に周辺の[
gc回路と?!気的に接続すると共に機械的な固定も必
要である。
When putting these photoelectric conversion elements into practical use, the surrounding [
With gc circuit? ! In addition to electrical connection, mechanical fixing is also required.

IC等の電子部品の接続端子部分に半田?(ンプを形成
し、これにより配線基板とのt気的受続を行なう電子部
品の取付力@は、ワイヤポンディングで電気接続を行な
う方法に比べ実装密度を上げろことが可能であり、取付
けに要する時間も少ない九め、近年この取付方法を使用
する分野が増加している。
Solder on the connection terminals of electronic components such as ICs? (It is possible to increase the mounting density of electronic components, which form an electrical connection with the wiring board and thereby make an electrical connection with the wiring board, compared to the method of making electrical connections by wire bonding. In recent years, the number of fields using this mounting method has increased because it requires less time.

第7図ないし第」0図に従来の電子部品の取付方法の一
例を示す。第7図ないし第10因は取付工程順に示した
断面図である。
An example of a conventional mounting method for electronic components is shown in FIGS. 7 to 7. Figures 7 to 10 are cross-sectional views showing the mounting process in order.

これらの図において、 (8)はセラミックやガラスエ
ポキシからなり1表面に任意の配線t! (9B )(
9b)が施された配R基板、(1)は光センナ等の電子
部品、(Ilj)(llb)は電子部品Lυの接続端子
部分く形成した半田バンプ、■は袋層前の電子部品tl
】を配線基板(8)K固定するための固定治具、(21
1は電子部品(1)と配mai板(8)との間に介在さ
せるスペーク、@は装着後の電子部品(1)と配線基板
(8)との間に充填される補強材である。
In these figures, (8) is made of ceramic or glass epoxy and has arbitrary wiring t! on one surface. (9B) (
9b), (1) is an electronic component such as an optical sensor, (Ilj) (llb) is a solder bump formed on the connection terminal part of the electronic component Lυ, and ■ is the electronic component tl before the bag layer.
] Fixing jig for fixing wiring board (8)K, (21
1 is a space interposed between the electronic component (1) and the wiring board (8), and @ is a reinforcing material filled between the electronic component (1) and the wiring board (8) after mounting.

第7−に示すように、電子部品11)の半田パン1(1
11(llb)を基板ζ8)上の配線11Ac 91L
 )C9b)O所定部分(10a)(10b)に合わせ
、固定治具■により固定する。この時1wL子部品(1
)と基板(8]との間KH固定治具(至)Kよる一定の
圧力が印加される。続いて、MB図に示すように、半田
バンプ(In)(Ill))の融点以上に加熱する。こ
の加熱処理により半田バンプ(Ill)(llb)が溶
融し、電子部品(1)と基板(8)との間隔が固定治具
■からの応力により減少し、電子部品口1と基板(8)
の配線箇所(10a)(Job)は半田バンプC11a
)(llb) t−介L’t”!1Ejlc的に′IM
続されろ。
As shown in No. 7-, the solder pan 1 (1) of the electronic component 11)
11(llb) to the wiring 11Ac 91L on the board ζ8)
)C9b)O Align with the prescribed portions (10a) (10b) and fix with the fixing jig (■). At this time, 1wL child part (1
) and the board (8) by the KH fixing jig (to) K. Then, as shown in the MB diagram, the solder bumps (In) (Ill)) are heated to a temperature higher than their melting point. do. Through this heat treatment, the solder bumps (Ill) (llb) are melted, and the distance between the electronic component (1) and the board (8) is reduced due to the stress from the fixing jig (■), and the gap between the electronic component opening 1 and the board (8) is reduced.
The wiring location (10a) (Job) is solder bump C11a
) (llb) t-suke L't”!
Continue.

その後第9図に示すように、I&仮(8)を室温にもど
し、固定治具■とスペーfclJを除去する。
Thereafter, as shown in FIG. 9, I&temporary (8) is returned to room temperature, and fixing jig (3) and space fclJ are removed.

そして、この状態で電子部品(すと基板(8)の配線(
9JL)(9b)との!気的接続框終rしているが、物
理的強度は不足している。そのため、第10図に示すよ
うにエポキシ樹III等の熱硬化性樹脂やシリコン系の
補強材のを電子部品(1)と基板(8)との間に充填し
ている。
Then, in this state, the wiring (
9JL) (9b) and! Although the electrical connections are complete, the physical strength is insufficient. Therefore, as shown in FIG. 10, a thermosetting resin such as epoxy resin III or a silicon-based reinforcing material is filled between the electronic component (1) and the substrate (8).

し】 発明が解決しようとする課題 前述した半田バンプを使用する取漕力法においては、 中 電子部品(1)を配Rti、板(8)の所定の位置
に固定すること、 01)  71fl熱時KW1子部品(υと配線基板(
87との間隔が減少し、且つ一定の間隔以上Kに減少し
なhこと。
Problems to be Solved by the Invention In the above-mentioned handling method using solder bumps, there are the following steps: fixing the electronic component (1) at a predetermined position on the mounting Rti and the plate (8); When KW1 child parts (υ and wiring board (
87 decreases, and does not decrease to K by more than a certain distance.

Cl11)  取着後十分な強度を有すること。Cl11) Must have sufficient strength after installation.

が要求される。is required.

このため、従来は適切な固定治具及びスペーサを必要で
あると共に、取着後、補強材t−yr、填する必要があ
り、その工程が煩瑣であった。
For this reason, in the past, it was necessary to use appropriate fixing jigs and spacers, and it was also necessary to fill in the reinforcing material after attachment, making the process cumbersome.

に)課題を解決するための手段 本発明は、基板の一生面上に設けらrtた端子部に半田
バンプが形成さnた電子部品を、上記端子部と対応する
入力端子を備える配Jilifニア11した配線基板に
取着する電子部品の取付方法であ、て。
B.) Means for Solving the Problems The present invention provides an electronic component in which solder bumps are formed on terminal portions provided on one surface of a board, and an electronic component having input terminals corresponding to the terminal portions. 11. This is a method for attaching electronic components to a printed wiring board.

前11i3電子部品に形成されt半田バンプを配線基板
の入力端子に接触させた状態で、前記電子部品の基板と
配線基板とを前記半田バンプより融点の低い熱願塑性樹
脂で固定した後、前記電子部品と配m基板とを半田バン
プの融点以上に加熱して電子部品と配線基板とのW!続
を行なうことを特徴とする。
With the solder bumps formed on the front 11i3 electronic component in contact with the input terminals of the wiring board, the board of the electronic component and the wiring board are fixed with a hot plastic resin having a melting point lower than that of the solder bumps, and then the The electronic component and the wiring board are heated to a temperature higher than the melting point of the solder bump, and the electronic component and the wiring board are heated! It is characterized by continuing.

(ホ)作用 固定さf′L九電子電子部品線基板を加熱すると。(e) Effect When the fixed f'L9 electronic component wire board is heated.

熱可塑性樹脂が軟化する七共に半田バンプが溶融し、電
子部品と配線基板との間隔が減少する。そして、軟化、
した熱可塑性樹脂は電子部品と配線基板との閲に入シ込
み、電子部品と配線基板との間隔は必要以上忙減少しな
い、また加熱終了時には熱可塑性樹脂が硬化し、補強材
となるため、後工程で補#jJを行なう必要もない。
As the thermoplastic resin softens, the solder bumps melt, reducing the distance between the electronic component and the wiring board. And softening,
The heated thermoplastic resin will infiltrate between the electronic components and the wiring board, so the distance between the electronic components and the wiring board will not be reduced more than necessary, and the thermoplastic resin will harden and become a reinforcing material when heating is finished. There is no need to perform correction #jJ in the subsequent process.

(へ)実施例 以下Ml因ないし第6図を参照して本発明を光センナに
適用した実施例につき説明する。
(F) Embodiment Hereinafter, an embodiment in which the present invention is applied to an optical sensor will be described with reference to FIGS.

第1図は本発明による電子部品の取付途中の伏Nを示し
、(1)は光電変換素子であって、ガラス等の透光性絶
縁a!i[(23の一重部(211)上に、anO21
TO等に代表されろ透光性導電酸化物からなる第1t確
(3)、!a面に平行にpln接合。
FIG. 1 shows a state in which an electronic component according to the present invention is being installed, and (1) is a photoelectric conversion element, which is a translucent insulator such as glass. i[(23 on the single part (211), anO21
The first material (3), which is made of a translucent conductive oxide, such as TO, etc. pln junction parallel to the a-plane.

pn接合等の半導体接合t−有する例えば膜厚4゜00
λ〜xpms度のアモルファスシリコンヲ主体とする半
導体膜(4)及びアルミニワム等の金属からなるjt1
2電価膜(極膜の積ノ1体から構成される膜厚チプミク
ロン〜ミクロンオーダの膜状光WK変換体(6)が設け
られ、斯る光wt変換体(6)の光Wt変換出カは上記
tR1・第2を極膜(3]、+5)からの絶縁基板(2
]の一重部(2a)KW、在t、7F、延長部分(3;
、t5i 上ttc42七刑ボ劫目す旧6金、銀 IJ
に、等の金属粉末をエポキシ、フェノール等の樹脂に混
入した導電性ペーストを熱硬化した出力端子(7a)、
(7b)から導出さnる。(8)は任意の配線(9a)
、(9b〕が施さnた配線基板で、本発明でいう配線基
板とは通常のガラスエポキシからなるプリント配MA板
、ポリエステル、ポリイミド等の高分子材料からなるフ
レキシブル配線基板、更にhリードフレーム等を含む。
For example, a film thickness of 4°00 having a semiconductor junction such as a p-n junction
jt1 consisting of a semiconductor film (4) mainly composed of amorphous silicon of λ~xpms degree and a metal such as aluminum
A film-like optical WK converter (6) with a film thickness on the order of a chip micron to a micron, which is composed of a product of two-charged films (polar films), is provided, and the optical WK converter (6) is F is the above tR1/2nd insulating substrate (2) from the polar film (3],
] single part (2a) KW, t, 7F, extended part (3;
, t5i upper ttc42 seven punishments old 6 gold, silver IJ
Output terminal (7a) made of heat-cured conductive paste made by mixing metal powder such as epoxy or phenol into resin,
Derived from (7b). (8) is any wiring (9a)
, (9b), and the wiring board in the present invention includes a printed MA board made of ordinary glass epoxy, a flexible wiring board made of polymeric materials such as polyester and polyimide, and a lead frame, etc. including.

(10a)(10b)は上記配線基板(8)の特定の配
線(9a)(9b)に一体的に設けらnた入力端子で、
実装さnる光゛成変換素子ti+の出力端子(71(7
b)と対応している。
(10a) and (10b) are input terminals provided integrally with specific wirings (9a) and (9b) of the wiring board (8),
Output terminal (71 (7
It corresponds to b).

C1l&)(llb)は斯る光′vlt変換素子(11
の出力端子<7&)tab)上に予め配線されt半田ノ
(ングで、融点が光を変換素子(1)や配線基板(8)
の溝底要素に燕的損傷を与えることのないような低融点
なもので構成される。本実施例では融点約135℃前後
のビスマス系低融点ハンダを用いた。
C1l&)(llb) is such a light 'vlt conversion element (11
The melting point of the light converting element (1) or the wiring board (8) is pre-wired on the output terminal of the
It is made of a material with a low melting point that will not cause any damage to the groove bottom element. In this example, a bismuth-based low melting point solder having a melting point of about 135° C. was used.

また、上述の配M&板(8)の配M(9a)(9t))
は銅ハクにハンダメツキが施さnている。
In addition, the above-mentioned arrangement M & board (8) arrangement M (9a) (9t))
It is made of copper plated with solder plating.

さて、上述の光電変換素子(1)の出力端子(7a](
7b〕の半導バンプ(Ill)(llb) f、配線基
板(8)上の配線の所定部分すなわち、入力端子(10
a)(10b)に合わせて、熱可塑性樹脂u9により配
線基板(8)に光電変換素子(1)の基板(2)を固定
する。熱可塑性樹脂(151は軟化点約95℃前後のエ
チレンビニルアセテートポリアミド、ボリグロピレン、
ボリエtしン系の樹脂を用い、iπ協のノズルから液体
状で吐出せ、光電変換素子(IJの絶縁基板(2)と配
線基板(8)の所定の部分に塗布し、第4肉で示すよう
に両者を固定する。第2図はこのようにして熱可塑性樹
脂U31t−付層し次状態を示す平面図である。
Now, the output terminal (7a) of the above-mentioned photoelectric conversion element (1)
7b] semiconductor bumps (Ill) (llb) f, a predetermined portion of the wiring on the wiring board (8), that is, the input terminal (10
a) According to (10b), fix the substrate (2) of the photoelectric conversion element (1) to the wiring board (8) using thermoplastic resin u9. Thermoplastic resin (151 is ethylene vinyl acetate polyamide with a softening point of about 95°C, polyglopylene,
Using a polyethylene-based resin, it can be discharged in liquid form from the iπ-Kyo nozzle, and applied to predetermined parts of the photoelectric conversion element (IJ's insulating board (2) and wiring board (8)). Both are fixed as shown. Fig. 2 is a plan view showing the next state after the thermoplastic resin U31t is layered in this manner.

続いて、光vt変換素子11)を固定した基板(8)を
加熱する。前述した半田バンプ(111(llb)と熱
度ffi性樹脂a9の場合、約155℃程度のベイパー
フェイズ ソルダリング(以下、vpsという1、〕を
用いると良好な堆層が行なえる。すなわち、フッ素系不
活性有機溶剤を、檀の中で加熱し、液を沸謄させること
により得られる飽和蒸気相中に、光電変換素子(1)を
固定した配線基板(8)を挿入すると、蒸気は基板上に
凝縮し、そのりC化潜熱を放出する。この潜熱は基板の
温度全蒸気の温度域で急速に、かつ均一に上昇させ、半
H1おLび熱可塑性樹脂が溶融される。
Subsequently, the substrate (8) on which the optical Vt conversion element 11) is fixed is heated. In the case of the aforementioned solder bump (111 (llb)) and thermal ffi resin A9, good layer deposition can be achieved by using vapor phase soldering (hereinafter referred to as VPS 1) at about 155°C. When the wiring board (8) on which the photoelectric conversion element (1) is fixed is inserted into the saturated vapor phase obtained by heating the inert organic solvent in a wood and bringing the liquid to a boil, the vapor flows onto the board. This latent heat causes the temperature of the substrate to rise rapidly and uniformly in the total vapor temperature range, and the half H1 and thermoplastic resins are melted.

第5図は加熱により半田バンプ(lla)(11b〕と
熱可塑性樹脂ttSが溶融し次状態である。
FIG. 5 shows the next state in which the solder bump (lla) (11b) and the thermoplastic resin ttS are melted by heating.

そnぞれの融点、軟化点の差からまず、熱軟化性樹脂(
151の軟化が半田バンプ(lla)(lit))の溶
融に先行して発生する。軟化した熱可塑性樹脂(151
は光電変換素子(1)と配線基板(8)との間に進入し
て行き、光電変換素子(1)を基板(2)と共に配線基
板(8)側へ引きつけようとする応力が発生する。
Due to the difference in their melting points and softening points, we first choose thermoplastic resins (
151 softening occurs prior to melting of the solder bump (lla) (lit). Softened thermoplastic resin (151
enters between the photoelectric conversion element (1) and the wiring board (8), and a stress is generated that tends to pull the photoelectric conversion element (1) together with the substrate (2) toward the wiring board (8).

V P、 S Kよる加熱に前述のように、急速な温度
上昇をもたらすので、軟化した熱軟化性樹脂口四が半田
バンプ(111(1lb)へ到達する前に半田バンプ(
1111)(llb)は溶融し%前記応力により入力端
子(10a)(10b)と溶融した半田バンプ(Ill
(llfi)との司;気的接続が得らnる。
As mentioned above, heating by V P, S K causes a rapid temperature rise, so the solder bump (111 (1 lb)
1111) (llb) melted and the input terminals (10a) (10b) and the melted solder bumps (Ill
You will have an emotional connection with (llfi).

第5図およびm6図に示す工うに、軟化した熱可塑性樹
脂uSが溶融し九半田バンブ(Ill)(ilb)を囲
んでさらに内部まで進入する。光ti変換素子(1)と
基板(8)との間隔は、中間に熱可塑性樹脂σ9が介在
するために必要以上に減少することはなく、また半田バ
ンプ(Ill)(llb)全島可塑性樹脂tlSが囲つ
ているので、半田バンプ(Ill)(Ilb)が広がっ
て隣ff1Tる配Jlil(9a)(9t))や半田バ
ンプ(Ill)(llb)同志で短絡する心配もない。
As shown in FIGS. 5 and 6, the softened thermoplastic resin uS melts, surrounds the solder bumps (Ill) (ilb), and further penetrates into the interior. The distance between the optical Ti conversion element (1) and the substrate (8) is not reduced more than necessary because of the presence of the thermoplastic resin σ9 in between, and the distance between the solder bumps (Ill) (llb) and the entire island of the plastic resin tlS Since the solder bumps (Ill) (Ilb) are surrounded by the solder bumps (Ill) (Ilb), there is no need to worry about them spreading and causing a short circuit between the adjacent ff1T wiring (9a) (9t)) or the solder bumps (Ill) (llb).

この状態で呈温に戻すと、半田バンプ(Ill)(1l
b)に光電変換素子(11と配、11(8)とは電りC
的に接続さn%島可塑性樹脂ri9に硬化して光電変換
素子(IIと配線基板(8)との接続の物理的強度全土
げる補強材となる。
When the temperature is returned to normal in this state, solder bumps (Ill) (1l
b) Photoelectric conversion element (11 and arrangement, 11 (8) is electric C
The n% island is cured into a plastic resin RI9, and becomes a reinforcing material that increases the physical strength of the connection between the photoelectric conversion element (II) and the wiring board (8).

(ト〕発明の詳細 な説明したように、本発明によnば、特別な治具やスベ
ーチを必要とせず、更に、後工程として補強材を形成す
る必要もなく、取付工程の簡略化が図nると共に、確実
な成子部品の配線基板 ′ヘの取付が行なえる。
(G) As described in detail, according to the present invention, there is no need for special jigs or benches, and there is no need to form reinforcing materials as a post-process, which simplifies the installation process. At the same time, the parts can be reliably attached to the wiring board.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第6図は不発明の一実施例を示すもので、
第1図は取付途中の状態を示す斜視図。 第2図は電子部品と配線基板とを熱可塑性樹脂で固定し
た状態を示す平面図、第3図は本発明により電子部品を
配Jill基板に取付けた状態を示す平面図、第4図な
いし第6図は取付工程を順次説明するための第1図にお
けるX−X線断面に相当する断面図である。 第7図ないし第10面は従来の取付工程を順次説明する
ための断面図である。 l・・・光電変換素子(電子部品]、2・・・絶縁基板
、8・・・配、11基板%9a、9b−配線、10jL
、10b ’・・・入力端子、lla、llb・・・半
田バンプ。
Figures 1 to 6 show an embodiment of the invention,
FIG. 1 is a perspective view showing a state in the middle of installation. FIG. 2 is a plan view showing a state in which an electronic component and a wiring board are fixed with thermoplastic resin, FIG. 3 is a plan view showing a state in which an electronic component is attached to a wiring board according to the present invention, and FIGS. 6 is a sectional view corresponding to the section taken along the line X--X in FIG. 1 for sequentially explaining the mounting process. 7 to 10 are cross-sectional views for sequentially explaining the conventional mounting process. l... Photoelectric conversion element (electronic component), 2... Insulating substrate, 8... Distribution, 11 board%9a, 9b-wiring, 10jL
, 10b'...input terminal, lla, llb...solder bump.

Claims (1)

【特許請求の範囲】[Claims] (1)基板の一主面上に設けられた端子部に半田バンプ
が形成された電子部品を、上記端子部と対応する入力端
子を備える配線を施した配線基板に取着する電子部品の
取付方法であって、前記電子部品に形成された半田バン
プを配線基板の入力端子に接触させた状態で、前記電子
部品の基板と配線基板とを前記半田バンプより融点の低
い熱加塑性樹脂で固定した後、前記電子部品と配線基板
とを半田バンプの融点以上に加熱して、電子部品と配線
基板との接続を行なう電子部品の取付方法。
(1) Mounting of an electronic component, in which an electronic component having solder bumps formed on a terminal section provided on one main surface of the board is attached to a wiring board with wiring provided with an input terminal corresponding to the terminal section. The method includes fixing the electronic component substrate and the wiring board with a thermoplastic resin having a melting point lower than that of the solder bumps, with the solder bumps formed on the electronic component in contact with the input terminals of the wiring board. After that, the electronic component and the wiring board are heated to a temperature higher than the melting point of the solder bump to connect the electronic component and the wiring board.
JP6430288A 1988-03-17 1988-03-17 Mounting process of electronic component Pending JPH01236636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6430288A JPH01236636A (en) 1988-03-17 1988-03-17 Mounting process of electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6430288A JPH01236636A (en) 1988-03-17 1988-03-17 Mounting process of electronic component

Publications (1)

Publication Number Publication Date
JPH01236636A true JPH01236636A (en) 1989-09-21

Family

ID=13254319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6430288A Pending JPH01236636A (en) 1988-03-17 1988-03-17 Mounting process of electronic component

Country Status (1)

Country Link
JP (1) JPH01236636A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03145795A (en) * 1989-10-31 1991-06-20 Murata Mfg Co Ltd Mounting of electronic component
JP2010506733A (en) * 2006-10-17 2010-03-04 フライズ・メタルズ・インコーポレイテッド Materials and associated methods for use in wiring electrical equipment
JP2016530723A (en) * 2013-09-03 2016-09-29 チザラ リヒトシステーメ ゲーエムベーハーZizala Lichtsysteme GmbH Position-stable soldering method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873126A (en) * 1981-10-27 1983-05-02 Seiko Keiyo Kogyo Kk Mounting method of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873126A (en) * 1981-10-27 1983-05-02 Seiko Keiyo Kogyo Kk Mounting method of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03145795A (en) * 1989-10-31 1991-06-20 Murata Mfg Co Ltd Mounting of electronic component
JP2010506733A (en) * 2006-10-17 2010-03-04 フライズ・メタルズ・インコーポレイテッド Materials and associated methods for use in wiring electrical equipment
JP2016530723A (en) * 2013-09-03 2016-09-29 チザラ リヒトシステーメ ゲーエムベーハーZizala Lichtsysteme GmbH Position-stable soldering method
JP2019071427A (en) * 2013-09-03 2019-05-09 ツェットカーヴェー グループ ゲーエムベーハー Position stable soldering method

Similar Documents

Publication Publication Date Title
US4437235A (en) Integrated circuit package
EP0863548B1 (en) Mounting assembly of integrated circuit device and method for production thereof
US4381602A (en) Method of mounting an I.C. chip on a substrate
US4396936A (en) Integrated circuit chip package with improved cooling means
US4363076A (en) Integrated circuit package
US5133810A (en) Flexible photovoltaic device and manufacturing method thereof
US7105931B2 (en) Electronic package and method
EP0645805B1 (en) Method for mounting a semiconductor device on a circuit board, and a circuit board with a semiconductor device mounted thereon
KR930010072B1 (en) Ccd package and making method of the same
JPH08213519A (en) Electronic element package
US3597666A (en) Lead frame design
US9318453B2 (en) Flip-chip hybridisation of two microelectronic components using a UV anneal
US20010023994A1 (en) Semiconductor device and the method for manufacturing the same
JPS616833A (en) Manufacture of material to be loaded
JPH01236636A (en) Mounting process of electronic component
JPS5821350A (en) Mounting structure of semiconductor integrated circuit
JPH0530360Y2 (en)
US20020074628A1 (en) Flexible wiring film, and semiconductor apparatus and system using the same
CN114173027A (en) Photosensitive assembly with heat dissipation element and preparation method thereof
JPS62169433A (en) Manufacture of semiconductor device
JP2841822B2 (en) Manufacturing method of hybrid integrated circuit
JPH06204096A (en) Manufacture of solid-state electrolytic capacitor
JP3096510B2 (en) Hybrid integrated circuit device
JP3249263B2 (en) Semiconductor package and manufacturing method thereof
JP3172630B2 (en) Film carrier type optical coupling device and method of manufacturing the same