JPH01236346A - Processor handshaking device - Google Patents

Abstract

PURPOSE:To smoothly switch a processing mode by providing plural receipt/ delivery registers and previously preparing parameters in an unused register when the processing mode is switched. CONSTITUTION:A program control section processes video signals based on parameters stored in one receipt/delivery register 201. At the time of switching the processing mode, a host computer first stores the parameter of the process in which the processing mode is switched in the other receipt/delivery register 202 through a switching section 101. When the storage of the parameter is completed, a flag is erected at the most significant bit and a switching controlling section 300 detects the flag and switches a switching section 102. Simultaneously, an address control section 400 designates the address of the program whose process is switched and the program control section executes the program whose process is switched by using the parameter in the register 202.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a processor shakehand device that is effective for use inside a digital video signal processing LSI used for real-time processing of video signals, for example.

(Prior Art) Digital video signal processing systems that can programmably process video signals using a plurality of calculation units have been considered. In this system, a plurality of arithmetic units are combined according to processing purposes to obtain certain functions (eg, gain control, synchronization processing, address generation, etc.). Furthermore, such a system not only processes one video signal, but also processes
Combine, wipe, and reduce multiple video signals.

It is also desired to add visual effects such as rotation.

In this case, it is necessary to switch the video signal processing mode, and the program of the arithmetic unit and the parameters necessary for video processing themselves are replaced. However, in a system operating in real time at the same time as the mode is switched, the output image will be distorted.

(Problems to be Solved by the Invention) As described above, in a digital video signal processing system, when the video processing mode is switched, it takes a long time to change the parameters, etc., and the output image is distorted.

Therefore, the present invention provides at least two transfer registers and prepares program addresses and parameters necessary for the next processing mode in advance under host control, so that when the processing mode of the programmable control section is switched, smooth processing can be achieved. It is an object of the present invention to provide a processor shake hand device that obtains switching and prevents image disturbance.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a host control section, a programmable control section,
It has a program memory that stores a plurality of types of programs for this programmable control section, and an address control section that controls a read address of this program memory.

Further, a first switching unit selectively supplies data from the host control unit to one or the other transfer register, and a first switching unit selectively deriving output data from the one or the other register to the programmable control unit. Alternatively, it has a second switching section that can be applied to the address control section. The switching control unit connects the second switching unit and the first transfer register so that the one transfer register is connected to the programmable control unit and the other transfer register is connected to the host control unit in a normal state. A switching unit is controlled, and each time a bit is input to a predetermined position of a transfer register connected to the host control unit, a predetermined command of the transfer register that has been connected to the host control unit is controlled by the address control unit. The transfer register is provided as a program start address to the host controller and the programmable controller, and the connection relationship between the transfer registers to the host controller and the programmable controller is switched.

(Function) When switching the processing mode of the programmable control unit using the above means, the host control unit stores the parameters required by the programmable operation unit in one transfer register in advance, and finally notifies that the process has been completed. writes a completion flag to a predetermined bit. As a result, the switching control section automatically switches the transfer register that was previously connected to the host control section to the programmable control section, and also switches the other transfer register that was connected to the programmable control section to the host control section. Switch to

As a result, the address control section specifies the program address for the processing mode to be switched, and at this time, the parameters and the like are already available for use by the programmable control section.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which reference numerals 101 and 102 denote an input switching section and an output switching section. Input switching section 10
1 can be supplied with data from a host computer. The input switching unit 101 can selectively supply data from the host computer to the transfer register 201 or 202. The output data of the transfer registers 201 and 202 is supplied to the output switching section 102. The output switching section 102 can select data from either register and provide it to the programmable control section. Further, an instruction for a predetermined portion of the register can be given to the address control unit 400. Furthermore,
For example, the most significant bits of the transfer registers 201 and 202 are input to the switching control section 300. The switching control unit 300 has, for example, a set input terminal and a reset input terminal of a flip-flop, and the transfer register 2 is connected to the set input terminal and the reset input terminal of a flip-flop, respectively.
The most significant bits of 01 and 202 are given. This switching control section 300 includes input and output switching sections 101 and 102.
For example, when one transfer register 202 is connected to the host computer, the other transfer register 201 is connected to the programmable control unit.

Now, assuming that one transfer register 202 is connected to the host computer and the other transfer register 2 (11) is connected to the programmable control section, the programmable control section uses the parameters stored in the transfer register 201. performs arithmetic processing (image processing).

Here, when switching the processing mode, parameters and the like are rewritten by the host computer in the other transfer register 202. When the rewriting is completed, the host computer writes "1" to the most significant bit of the transfer register 202 as a completion flag. Then, the state of the flip-flop of the switching control unit 300 is switched, and if the programmable control unit has executed the instruction to permit switching, the transfer register 202 is changed by 1 to the programmable control unit side, and the transfer register 20
1 is switched to the host computer side. Furthermore, at this time, the address control unit 40
0 is also given an instruction to initialize a predetermined address. Since the processing mode has been switched, this command is for starting a processing program in a new mode.

The address control unit 400 specifies the address of the program memory based on the above command and starts the program from the beginning. Based on this program, the operating functions of the programmable control section are determined, and image processing using parameters and the like is started.

At this time, the transfer register 202 is connected to the programmable control unit, and the transfer register 201 is connected to the host computer, but when switching the processing mode again, the host computer will need to connect the transfer register 201 this time. Write the parameters and finally write the completion flag. As a result, the connection relationship of the registers is switched as before.

In this way, in this embodiment, even if the processing mode is switched, the parameters necessary for the new processing are stored in the register in advance, so the processing mode can be switched at high speed, and the program required for the new processing can be Since the image starts from the beginning, smooth switching is possible without causing image disturbance.

FIG. 2 is an overall block diagram of a system using an embodiment of the present invention.

The circuits shown in FIG. 1 are configured inside the arithmetic processing units 21 (01) to 21 (to) shown in FIG. 2, respectively. Although FIG. 3 shows the arithmetic processing section 21 (01), the multiplication section 32. Arithmetic unit 33. The calculation unit provided inside the synchronization signal processing unit 36 and the address generation unit 38, etc.
This corresponds to the above-mentioned programmable control unit, and by changing these sequences through a program, the functions can be changed.

In FIG. 2, the network section 20 receives two 17-bit external video signals A1. Bl can be input. In addition to this, 17-bit input sections are prepared, making 32 in total.

The network unit 20 includes a plurality of (for example, 48 systems) 17
For example, the 17th to 48th output sections are grouped into two sets and each set is connected to the programmable arithmetic processing sections 21 (01) to 21 (1B), respectively. Programmable arithmetic processing unit 21 (01) to 2
1 (1G) are respectively connected to, for example, the 17th to 32nd input sections of the network section 20. The network section 20 is provided with an output section for obtaining a final video output. There are multiple output sections (
For example, from the 1st to the 16th network section), and can be connected to a similar network section at the next stage.

A main control section 22 provides control signals to the network section 20 and the arithmetic processing sections 21 (01) to 21 (1B).

The input digital signal format handled by the above system has a total of 17 bits, as shown in Figure (b), of which 1 bit is used as synchronization signal information, and the remaining bits are video signal data or synchronization signal. It is data. When the synchronization signal information is "1", the remaining 16 bits are synchronization signal data, and when it is "O", the remaining 16 bits are video signal data.

Further, the network section 20 has nine LSIs connected to one
The 17-bit input section and output section each have 2 bits assigned to each LSI to facilitate wiring connection to one LSI. Further, the network section 20 has a built-in network control section, and the input/output connection system can be programmably switched by a command from the main control section 22 or the arithmetic processing section.

FIG. 3 shows one of the arithmetic processing units, for example 21 (01).

Depending on its control state, the network section 20 transmits the external video signals A1 and B to the arithmetic processing section 21 (01).
1 or the video signal tg fed back from another arithmetic processing section can be supplied to this arithmetic processing section 21 (01) in pairs, or only one of the video signals can be supplied.

The arithmetic processing unit 21 (01) receives the video signal A2. It has two input sections that accept B2, and each input section is connected to a synchronization separation section 31A.
, 31B. Synchronization separation section 31A, 31B
The synchronization signal separated by is input to the sequencer 37,
It is used as a reference for determining the operation timing of the arithmetic processing unit 21 (01), and the video signal A2. Used for time adjustment of B2.

The 16-bit video data separated by the synchronization separation sections 31A and 31B can be input to the multiplication section 32 and the calculation section 33. The multiplier 32 can multiply two video signals or can multiply one video signal ti by a constant or by a variable value of =1. The arithmetic unit 33 can add, subtract, or compare two video signals, add or subtract a certain value to one video signal, or perform a comparison process with a certain value.

The outputs obtained by the multiplier 32 and the arithmetic unit 33 can be further supplied to the human power of one of the two.
Also supplied.

The switching section 34 selects and outputs either one of the human powers, and the output thereof is derived via the synchronization adding section 35. The synchronization adding section 35 can add or stop a synchronization signal.

This arithmetic processing section 21 (01) is further provided with a synchronization signal processing section 36 and an address generation section 38.

Furthermore, a control memory 41 is also included in addition to the external program memory. The control memory 41 is provided for each data processing section so that when each data processing section inside the arithmetic processing section 21 (01) performs its own assigned processing, there is no need to read out all instructions from the program memory each time. A unique program can be stored in advance.

FIG. 4 shows an example of combining video signals using the above system. In this case, the network unit 20 operates from the arithmetic processing units 21 (01) to 21 (03
) as shown in the figure, the external video signal A1
and 81 can be added and combined to obtain an output. The video signal A1 is manually multiplied by 0 in the multiplier of the arithmetic processing unit 21 (01), and the video signal B1 is multiplied by 0 in the arithmetic processing unit 21 (02).
is input to the multiplier and multiplied by (l-α). The output of each multiplier is input to the arithmetic processing unit 21 (03), and is added and derived in the arithmetic unit. Network part 2
0 and the arithmetic processing units 21 (01) to 21 (1B) can be switched to various forms depending on the processing purpose.

FIG. 5 shows in block form the processing functions that can be realized by further combining the systems shown in FIG. In this example, a processing unit 401 separates one composite video signal into luminance and color, and the output color signal and luminance signal are matrixed in the next processing unit 403 to derive R, G, and B signals.

Then, the R2O, B signals are subjected to γ correction in the processing section 4Q3, and the resulting R, G, B signals are subjected to inverse matrix processing. Further, the luminance signal and color signal obtained in this manner are encoded by the processing unit 406 to obtain a composite video output.

[Effects of the Invention] As explained above, the present invention provides at least two transfer registers and prepares program addresses and parameters necessary for the next processing mode in advance under host control, thereby improving the processing of the programmable control unit. Smooth switching can be achieved when the mode is switched, and image distortion can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2(a) is a configuration explanatory diagram showing a system using this invention,
FIG. 3(b) is a diagram showing the signal format, FIG. 4(c) is a diagram shown to further explain the network section, FIG. 2 is an explanatory diagram showing an example of a signal processing form of the system of FIG. 2, and FIG. 5 is a functional block diagram showing an example of use of the system of FIG. 2. 101.102...Switching section, 201.202...
Delivery register, 200... switching control unit, 400
・1. Address control section, 2o...Network section 2
1 (Of) to 21 (17)... Arithmetic processing unit, 22
...Main control section, 31A, 31B... Synchronization separation section, 32.°° Multiplication section, 33.degree. Calculation section, 34.. Switching section, 35.. Synchronization addition section, 36.. Synchronous signal processing section, 37... Sequencer, 38... Address generation section. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] A host control section, a programmable control section, a program memory storing a plurality of types of programs for this programmable control section, an address control section that controls a read address of this program memory, and data from the host control section a first switching section that selectively supplies the other transfer register; and a second switching section that can selectively derive output data of the one or the other register and provide it to the programmable control section or the address control section. a switching unit, and the second switching unit and the first switching unit such that in a normal state, the one transfer register is connected to the programmable control unit and the other transfer register is connected to the host control unit. Each time a bit is input to a predetermined position of a transfer register connected to the host control section, the address control section sends a predetermined command to the transfer register that has been connected to the host control section. 1. A processor shake hand device comprising: a switching control section for giving a program start address to a program start address and for switching a connection relationship between transfer registers to the host control section and the programmable control section.