JP2513772B2 - Digital signal time adjustment device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention relates to time alignment of digital signals effective for use in a digital video signal processing system used in broadcast signal processing equipment such as a broadcasting station. Regarding the device.

(Prior Art) Generally, in a digital video signal processing system, a processing unit is individually created according to the processing purpose of a video signal. The video signal processing includes processing such as combining a plurality of video signals, reduction, enlargement, and rotation. Recently, digital processing technology has been developed in order to avoid deterioration of signal processing characteristics due to temperature changes, aging changes, and the like.

However, conventionally, a unit dedicated to each of the above-described signal processes is created and a specific unit is associated with one specific process. Therefore, as the number of types of specific processing increases, the number of units also increases, and the overall size of the device becomes large.
A great deal of effort is required for maintenance and construction of processing functions by combining units.

(Problems to be Solved by the Invention) As described above, the conventional apparatus requires a great deal of labor for design, maintenance, combination of units, and the like, and improvement of this point is desired. Therefore, a system is conceivable in which a plurality of arithmetic processing units are combined and integrated so that a signal processing function can be constructed, and if the combination is programmable, various functions can be exhibited. However, in the case where a plurality of video signals are respectively transmitted via the arithmetic processing unit and finally combined, there may be a time difference between the two even though they are digital, due to the difference in the transmission path.

Therefore, the present invention does not require physical connection work depending on the processing purpose of the video signal, can be freely programmable and is extremely flexible, and therefore, the time lag in the middle of the digital transmission path An object of the present invention is to provide a digital signal time adjustment device capable of correcting the deviation even if it occurs.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, the first synchronization signal in which one of the two systems of digital signals to which the synchronization signal is added is supplied via the delay line. A separation unit; a second synchronization separation unit to which the signal of the other system is directly supplied; a data processing unit to which the data separated by the first and second synchronization separation units is supplied; The first and second synchronization signals separated by the second synchronization separation unit are supplied to control the program operation of the data processing unit and detect the phase shift between the first and second synchronization signals. A sequencer for latching delay amount control data for eliminating the phase shift and giving it to the delay line to control the delay amount is provided.

(Operation) By setting the processing contents (for example, multiplication, addition, comparison, etc.) of the programmable arithmetic processing unit by the above means, various video signal processing functions can be provided, and a plurality of programmable arithmetic processing units can be provided. Since the connection order and form of can be set, the final output video signal that has passed a plurality of video signal processing functions can be comprehensively obtained.
Since a means for correcting the time lag caused by passing through the arithmetic processing unit is provided, accurate and stable image processing can be performed.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a main part of one embodiment of the present invention.
2 and B2 are digital video signals. The format of the digital video signal will be described with reference to FIG.

One digital video signal A2 is output from the delay line 100 and supplied to the sync separation section 31A formed inside the LSI, and the other digital video signal B2 is directly supplied to the sync separation section 31B. The sync signal separated by the sync separation units 31A and 31B is supplied to the sequencer 37, and the data is input to the data processing unit 42.

The data processing unit 42 performs data processing based on the program of the sequencer 37, finally derives one video signal, and supplies it to the synchronization adding unit 35. The synchronization adding unit 35 adds a synchronization signal to the video signal and outputs it to the outside of LSI.

The sequencer 37 controls the procedure of each circuit operation in the LSI. Depending on the type of this procedure, the video signal processing function (amplification, gain control, correction, synthesis, insertion, dissolve, etc.)
And so on. The sequencer 37 reads a program from an external program memory in advance and gives instruction data to each circuit unit. Further, the sequencer 37 may require a program jump depending on the decoded instruction and the operating state (condition) of the circuit. In such a case, the instruction of the control memory 41 inside the LSI can be used without having to read from the external program memory. Especially in the case of a video signal, the data processing routine is always constant, and for example, it may be sufficient to process the same program instruction in the synchronizing signal period and the burst period. In some cases, it may be necessary to perform certain processing with a certain program in the next scanning period based on the data calculated in the synchronization signal period. In such a case, a program that is frequently used and needs a quick response is stored in the control memory 41 in advance, so that smooth data processing can be obtained even if there is a program jump.

Next, in this system, the delay amount control data is latched in the latch circuit of the sequencer 37, and the delay line 100 and the delay line 10 provided inside the LSI are latched.
Can be given to one.

Especially when two video signals are processed to obtain one video signal, the synchronization of the two input video signals becomes a problem. When there is a phase difference between the synchronization signals of the two video signals, the latch circuit of the sequencer 37 can latch the data for controlling the delay amount and give it to the delay line 101, for example. However, the delay line 10 that can be configured inside LSI
Since the delay amount of 1 has a limit, control data can be given to the external delay line 100 when the delay amount is insufficient.

There are various methods to detect the phase shift between two video signals, but when the video signal address is generated by incrementing from the time when one video signal sync signal is input, and the other video signal sync signal is input. It is also possible to know the delay amount by calculating the address of.
Furthermore, the phase shift of the video signal input to this circuit block may be measured in advance and the delay amount control data may be stored in the latch circuit. The time to detect the phase shift between the two video signals includes the time when the system enters stable operation, the time when the circuit function is switched, and the periodical operation. It is preferable to carry out.

The above-mentioned phase matching function is as shown in FIG.
This is effective when a video processing system is constructed by using multiple LSI in series. When synthesizing each video signal, as a pre-processing, the phase between the two video signals is applied while the same LSI is used to perform processing such as reduction, enlargement, and partial sampling on each video signal. A gap may occur. In such a case, good image processing can be obtained by executing the time adjustment function.

FIG. 2 is a block diagram showing an example of a video processing system using the present invention, and two 17-bit external video signals A1 and B1 can be input to the network unit 20.
In addition to this, a 17-bit input section is prepared, and there are 32 in total.

The network unit 20 has a plurality (for example, 48 systems) of 17-bit output units. For example, the 17th to 48th output units are grouped into two sets, and each set is programmable operation processing unit 21.
(01) to 21 (16), respectively. The outputs of the programmable arithmetic processing units 21 (01) to 21 (16) are connected to, for example, the 17th to 32nd input units of the network unit 20, respectively. The network unit 20 is provided with an output unit for obtaining a final video output. A plurality of output units (for example, 1st to 16th output units) are provided and can be connected to the same network unit in the next stage.

Reference numeral 22 denotes a main control unit, which gives a control signal to each control unit of the network unit 20 and the arithmetic processing units 21 (01) to 21 (16).

The input digital signal format handled by the above system is
As shown in FIG. 7B, the total is 17 bits, 1 bit of which is used as the synchronization signal information, and the remaining bits are the video signal data or the synchronization signal data. When the synchronization signal information is “1”, the remaining 16 bits are synchronization signal data, and when the synchronization signal information is “0”, the remaining 16 bits are video signal data.

Further, the network unit 20 is configured, for example, by providing nine LSI on one board, and a 17-bit input unit and an output unit are allocated to each LSI by two bits, respectively.
It facilitates wiring connection to one LSI. Further, the network unit 20 has a built-in network control unit, and its input / output connection system can be programmably switched by a command from the main control unit 22 or the arithmetic processing unit.

FIG. 3 shows one of the arithmetic processing units, for example, 21 (01).

According to the control state, the network unit 20 pairs the arithmetic processing unit 21 (01) with the external video signals A1 and B1 or the video signal fed back from another arithmetic processing unit as a pair. 01), or only one video signal can be supplied.

The arithmetic processing unit 21 (01) receives the video signals A2 and B2 2
It has an input unit, and each input unit is connected to the sync separation units 31A and 31B. The synchronization signals separated by the synchronization separation units 31A and 31B are input to the sequencer 37 and used as a reference for determining the operation timing of the arithmetic processing unit 21 (01), or as a video signal.
It is used for time adjustment of A2 and B2.

The 16-bit video data separated by the sync separation units 31A and 31B can be input to the multiplication unit 32 and the calculation unit 33.
The multiplication unit 32 can multiply two video signals with each other or multiply one video signal with a constant or a variable value. The arithmetic unit 33 can add, subtract, or compare the two input video signals, add or subtract a certain value to one of the video signals, and further compare it with a certain value.

The outputs obtained by the multiplication unit 32 and the calculation unit 33 can be further supplied to one input of each other, and are also supplied to the switching unit 34.

The switching unit 34 selects and outputs one of the inputs, and the output is derived via the synchronization adding unit 35. The synchronization adding unit 35 can add or stop the synchronization signal.

The arithmetic processing unit 21 (01) further includes a synchronization signal processing unit 3
6. An address generator 38 is provided. Furthermore, the control memory 41 is attached to the external program memory.
Is also built in. When each data processing unit in the arithmetic processing unit 21 (01) performs its own shared processing, the control memory 41 controls each data processing unit so that all instructions do not have to be read from the program memory each time. A unique program can be stored in advance.

FIG. 4 shows an example of a case where video signals are combined using the above system. In this case, the network unit 20 can obtain an output obtained by adding and synthesizing the external video signals A1 and B1 by setting the connection form of the arithmetic processing units 21 (01) to 21 (03) as shown in the figure. The video signal A1 is input to the multiplier of the arithmetic processing unit 21 (01) and multiplied by α, and the video signal B1 is input to the multiplier of the arithmetic processing unit 21 (02) and multiplied by (1−α). The output of each multiplier is input to the arithmetic processing unit 21 (03), is subjected to addition processing in the arithmetic unit, and is derived.

Network unit 20 and arithmetic processing units 21 (01) to 21 (16)
Can be switched to various forms according to its processing purpose.

FIG. 5 is a block diagram showing processing functions that can be realized by further combining the system shown in FIG. In this example, one composite video signal is subjected to luminance color separation by the processing unit 401, and its output color signal and luminance signal are processed by the next processing unit.
Matrix is performed at 402, and R, G, B signals are derived. And
The R, G, and B signals are γ-corrected by the processing unit 403, and the resulting R, G, and B signals are
G and B signals are subjected to inverse matrix processing. Further, the luminance signal and the color signal thus obtained are encoded by the processing unit 406 to obtain a composite video signal output.

[Effects of the Invention] As described above, the present invention does not require physical connection work according to the processing purpose of a video signal, can be freely programmable, and is extremely flexible. Even if a time shift occurs in the middle of the transmission path, the shift can be corrected and good digital video signal processing can be obtained.

[Brief description of drawings]

1 is a circuit block diagram showing an embodiment of the present invention, FIG. 2 (a) is a configuration explanatory view showing an example of use of the present invention, FIG. 2 (b) is a diagram showing a signal format, and FIG. ) Is a diagram shown for further explaining the network unit, FIG. 3 is a block diagram showing the configuration of the arithmetic processing unit of FIG. 2, and FIG.
Explanatory drawing which shows an example of the signal processing form by this invention, 5th
The figure is a functional block diagram showing an example of use of the system of the present invention. 100,101 …… Delay line, 20 …… Network section, 2
1 (01) to 21 (17) ... arithmetic processing unit, 22 ... main control unit, 31A, 31B ... synchronous separation unit, 32 ... multiplication unit, 33 ... arithmetic unit, 34 ... switching unit, 35 ...... Synchronization adder, 36 …… Synchronization signal processor, 37 …… Sequencer, 38 …… Address generator.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Ryoichi Yajima 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Broadcasting Research Institute of Japan Broadcasting Corporation (72) Inventor Kiyomasa Kanai 2-2-1 Shinnan, Shibuya-ku, Tokyo Within the Japan Broadcasting Corporation Broadcasting Center (72) Inventor Shigemi Mikami 2-2-1 Jinnan, Shibuya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Center (72) Nobuyuki Sasaki 1 Komukai Toshiba-cho, Kawasaki-shi, Kanagawa Prefecture Toshiba Corporation Komukai Plant (72) Inventor Koji Hoshino 1 Komukai Toshiba Town, Saiwai Ward, Kawasaki City, Kanagawa Prefecture Komukai Factory (72) Inventor Kazuhiro Harukawa Komukai Toshiba Town, Saiwai Ward, Kawasaki City, Kanagawa Prefecture No. 1 in Toshiba Komukai Factory (56) References JP-A-61-84178 (JP, A) JP-A-62-250772 (JP, A) JP-A-63-234722 ( P, A) JitsuHiraku Akira 62-85053 (JP, U)

Claims (1)

(57) [Claims] 1. A first sync separation section to which a signal of one system is supplied through a delay line and a signal of the other system is directly supplied from two systems of digital signals to which a synchronization signal is added. A second synchronization separation unit, a data processing unit to which the data separated by the first and second synchronization separation units is supplied, and a first processing unit separated by the first and second synchronization separation units. The second synchronization signal is supplied to control the program operation of the data processing unit, detect the phase shift between the first and second synchronization signals, and latch the delay amount control data for eliminating the phase shift. A digital signal time adjusting device, comprising: a sequencer for applying the delay line to control the delay amount.