JPH01236336A - System state notifying system - Google Patents

Abstract

PURPOSE:To make an abnormal state noticeable with a less quantity of hardware by performing state notification that each CPU reaches a prescribed state and, at the same time, whether or not the state notification of each CPU is made to a system controlling area. CONSTITUTION:When a CPU 10 reaches a prescribed state, it is notified to each CPU by driving state notifying means 37-40 provided commonly to each CPU. Therefore, it is understood that any one of the CPUs reaches the prescribed state. On the other hand, display controlling means 36, 41, 24, 26, and 28 detect the CPU which drives the state notifying means 37-40 and causes the detected CPU to be displayed on a system controlling area provided at part of the displaying screen of a display device 21. Accordingly, it can be known that which CPU drives the state notifying means 37-40 and which CPU reaches the prescribed state.

Description

[Detailed Description of the Invention] [Summary] Regarding a system equipped with a display device and a keyboard that switch and display contents processed by at least two central processing units, one of the central processing units state (for example, a state caused by an abnormality in the central processing device itself or an abnormality in the system under its control). In order to prevent the inconvenience and increase in size of the system by providing each central processing unit separately, it is provided in common to each central processing unit, and is driven by the central processing unit that is in a predetermined state that should be notified to the outside. A state notification means for notifying the occurrence of the predetermined state and a central 98 instantaneous device that has driven the state notification means are detected, and a person is displayed in a system display area set in a part of the display screen of the display device. It is configured by providing a table and a control stage.

[Industrial application field]

For this 'fl version, there are at least 62 central processing S! The present invention relates to a system including a display device that switches and displays contents processed by these central processing units, and a board.

Conventionally, two or more central processing units (hereinafter simply referred to as CPUs) have been provided to configure one system. This is used for backup purposes in case some kind of abnormality occurs in one of the CPUs, or when two CPUs are operated in parallel to achieve B-concatenation of processing.

In such a system, an indicating means is provided for indicating whether each CPU is i'+1 in a predetermined undesirable state. Here, the unfavorable predetermined state is, for example, an abnormality in each part of the system under its own control, an abnormality in the CPU itself, or a state other than an abnormality (for example, the remaining amount of storage capacity in the system is less than a predetermined value). (if exceeded), etc.
This is a state in which it is necessary to notify the outside (operator or maintenance staff). When each CPU reaches this predetermined state, it drives its corresponding instruction means to inform the operator and Hoyoi Q of this fact.

[Conventional technology]

FIG. 4 is a block diagram of an example of a conventional system. In the figure - the system has two CPUs 10 and 11; Each CPU 10 and 11 has its own underlying system 12 and 13, respectively. Each Cr'LI 1
0 and 11 are connected together via a common bus 20. A line system Ill 60 section 14, a printer control Ill1 section 15, and a file control section 17 are connected to the common bus 20. These each include line 19. A printer 16 and a magnetic disk 18 are connected.

The common bus 20 also has an operation panel lll11M11 part 9o.
is connected. The operation panel control section 90 controls the operation f'l panel 8.
Controls the CRT 21 and parking board 22 provided at 0. Driver/Receiver (hereinafter referred to as 1, D/R) 2
3 transmits and receives data between the common bus 2o and the operation panel control section 23. Microprocessor (hereinafter simply referred to as MP)
(referred to as U) 24 indicates that each component constituting the operation panel system fi11 section 90 is integrated within the machine and integrally υ)'Jf)-4.

ROM25LiMPLJ24 (programs necessary for J work) are stored as 7-Mura Air. RAM26 is M
It has a work area and a table area necessary when the PU 24 operates. The screen memory 27 stores data to be displayed on the CRT 21 (display data).The screen control unit 28 reads out the display data from the screen memory 27 and performs predetermined signal processing (for example, a portion of the video signal). and output to CRT21 1°-1 = -hort vI tall rJs
2 '9 Lt, No. 11 from the keyboard 1522 and the screen changeover switch 30 is processed. The screen changeover switch 3o selects the data to be displayed on the display screen of the CRT 21.
It shall be under υ1@ of CPU10, or CPL
This is a selection switch to select between b and b which are under the control of lll. Further, the bus control unit 31 performs bus timing control of the common bus 20, such as +111111.

FIG. 5 is a diagram showing the program (firmware) stored in the ROM 25. In the same figure, the MPU vector {circle around (2)} processes interrupts to the MPLI 24. Screen control ■ is used to display electrocardiographic programs to display data. 4-Board Control (2) is a program necessary for processing data from the keyboard 22 and screen changeover switch 30.

The operation panel 11111 section 90 further includes a buzzer register 32a.
and 32b, and lamp registers 33a and 33b. Buzzer register 32a and lamp register 33
a is provided corresponding to the CPU 10. The buzzer register 32b and the lamp register 33b are cpuii
It is set up correspondingly. Buzzers 34a and 34b are connected to the buzzer registers 32a and 32b, respectively.

Additionally, lamps 35a and σ35b are connected to the lamp registers 33a and 33b, respectively.

When the CPUIO and CPU II are in a predetermined state during operation, they set flags in the corresponding buzzer registers 32a and 32b and lamp registers 33a and 33b.

Here, the predetermined condition 1 is a condition that needs to be notified to the outside, as described above. For example, CPU10
Or, there is an abnormality in the hv of the CPU 11, or an abnormality in various parts within the system under its own control. Here, when C)) UO enters a predetermined state and the flags are set in the buzzer registers 32a and 33a, the buzzer registers 32a and 33a are set.
-34a sounds and lamp 35a lights up. A-The operator and maintenance personnel knew that the CPU 10 was in a constant state, and did not take any necessary action on CPU i ot.

[Problem to be solved by the invention]

However, in the conventional configuration described above, it is necessary to turn off the buzzer and lamp for each CPU provided in the system, which requires hardware and increases costs. Further, since dedicated buzzer registers and lamp registers are required for each buzzer and lamp, the hardware becomes large and high. Furthermore, it is uneconomical because as many wires as the number of buzzers and lamps are required to connect the resistors and the buzzers or lamps. Furthermore, since buzzers and lamps are usually more prone to failure than other components in the system, they lack reliability in notifying outsiders of abnormalities.

Therefore, it is an object of the present invention to solve these problems and provide an economical system that can reliably notify external parties of which CPU is in a predetermined state such as an abnormality using a small amount of hardware. With the goal.

[Means to solve the problem]

The present invention provides at least two central processing units 10 and 11
And the display! 21 and 1 - board 22, a sub-section that switches the contents processed by each central processing unit 10 and 11 and displays it on the display device 21, and a υ control section (operation panel control section) that controls information from the keyboard 22; 100 is assumed to be an A1 elephant.

In the above system, the present invention provides a state notification means that is provided in common in each of the central processing units 10 and 11, is driven by the central processing unit that has reached a predetermined state that should be notified to the outside, and notifies the occurrence of the predetermined state. Display control means 36, 41 that detects the central processing unit that drives the status notification means 37 and 40 and displays the system display installed on a part of the display screen of the display device 21 at the rear.
．． 24, 26, and 28 are provided.

[Meizuki]

For example, when the central processing unit 10 reaches a predetermined state, the central processing unit 10 drives the status notification stage 37 and -40, which are installed in common in each central processing ill device, to notify this state. Notify. This indicates that one of the central processing units has reached a predetermined state. On the other hand, the display control means 36, 41, 24, 26, 28 detects the central processing unit that has driven the status indicating means 37 to 40, and displays the information in the system control area provided in a part of the display screen of the display device 21. . As a result, it is possible to know which central processing unit has activated the status notification means 37 to 40 (A11i), that is, which central processing unit has reached a predetermined state. It is possible to identify the central processing unit that has reached a predetermined state without providing a status notification means for each central processing unit.In this case, since the existing display 'VIl' position is used for display, less hardware is required. You can be notified reliably by using the software.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, references to j4- are omitted for components that are similar to those in Fig. 4. System 1 or 2 CPUs in this embodiment
10, CPU 11, and mail system control 211 section 12.13. Printer control section 15,)? File control unit 17. Printer 16.6nm desk 18. timesal
9. It is comprised of a CRT 21, a keyboard 229, a display changeover switch 30, and a display panel control section 100.

The display panel control alS100 is a driver/receiver (D/R
)23. Microbe 0 set (MPtJ)? I.

RAM26. It is equipped with a screen control section 276, a keyboard control section 29, and a bus control section 31. These components are the same as those shown in FIG.

The display panel f, 1H11 section 100 includes a ROM 36.

1<OM 36 is equipped with a six-piece program (tour unevenness T7) as shown in FIG. The ROM 36 stores MPU vectors i, ii! shown in FIG. i-screen system u■ and keyboard I
In addition to the ll I III programs, there is also a system-li tl I 11 rear control 1rV program. System control area restriction IVLIL displays information to be described later in a system control area provided in a part of the display screen of the CRT 21. The buzzer register 37 and the lamp register 38 are provided in common to the two CPLIIOs and 11. When the cpuio and 11 reach a predetermined state, such as when an abnormality occurs in itself or in each part under its control, the buzzer register 37 and lamp register 38 are activated.
A flag is set for driving the bridge 39 and the lamp 40, respectively.

At this time, the CPU that has set the flag updates its own identification bit. This identification bit is, for example, 1-bit information, and 0 is assigned to the CPU 10, and
is assigned 1.

A buzzer 39 is connected to the buzzer register 37, and a lamp 40 is connected to the lamp register 38. When the people flag is set in the buzzer register 37 and lamp register 38, the corresponding buzzer register 39 sounds and the lamp 40 lights up. It is. For this purpose, system display 1 in Figure 2
The rear control program ■ trains at predetermined intervals,
Start system display area control by MPU vector,
Upon receiving this, the MPU 24 performs a sensing operation at the predetermined time intervals.

Next, the operation will be explained.

During normal operation, for example, the CPU 10 gives instructions to the magnetic disk 18 via the file unit 17 shown in FIG. 1 and reads desired data from it.
0 sends the data onto the common bus 20 after performing a predetermined process. The sent data is stored in the RAM 26 in the display 511Iυ1111 section 100 via the D/R 23. The MPU 24 of the display panel control unit 100 is a ROM
According to the screen control block stored in 36 [1 gram ■,
Read out the necessary data from RAM26 and display the screen
Transfer to 27.

The MPU 24 displays screen 1. Drive the II control section 28,
Read the display data from the CRT 27 and output it to the CRT 21.
"do.

FIG. 3 shows the display screen of the CRT 21. The illustrated display screen is composed of 12 lines x 32 characters.

The display screen is divided into a user display area 42 of 10 lines x 32 characters and a system display area 43 of 2 lines x 32 characters. The display data described above is displayed in this user display area 42. The user display area 42 can be set to CPLJlo or CPUII by using the screen changeover switch 30.
Display the display data for either one. Therefore, if the screen changeover switch 30 specifies cpuio, display data under the control of CPU10 is read from the screen memory 27, and if CPUII is specified, the display data is read from the screen memory 27 under the control of cpuii. 1. Certain display data is read out 1. The system display area 43 always displays the information described below regardless of the state of the screen changeover switch 30. 4. During the above-mentioned movement, for example, the CPU 10 should indicate an abnormality etc. to the outside. When the state is reached, CPU10 sends a flag and its own identification bit to the common bus 23.

These data are sent to the buzzer register 3 via the D/R23.
7 and ramp register 38, respectively. When the flags are set in the buzzer register 37 and the lamp register 38, the buzzer 1-39 sounds and the lamp 401 lights up.

On the other hand, the MPU 24 activates the sense register 41 at a predetermined timing and reads the states of the Buna register 37 and the lamp register 38.3. In the above operation, C1) UIO
has set the flag, so the sense register 41 reads the flag and the pitted identification pins 1 to ((3III, for example)). When this is detected, M l) U 24
In accordance with the system display area control program 411V stored in the ROM 36, information shown in FIG. 3 of the CPU 10 is displayed on the system display [rear 43] on the display screen of the CRT 21.

In FIG. 3, CP U O= ” and “Cl) U 'l
= "indicates the CPU that is involved in the display data displayed on the Coza table 1 rear 42. In the case shown in the figure,"
``CPU O = DISP'' is displayed, indicating that the display data on the CPU 10 side is being displayed.
'BZ-"° and '1MP-"° in C
When the buzzer 39 and lamp 40 are driven due to a cause on the PU 10 side, 'BZ・ON' and 'L' are activated as shown in the figure.
"MP = ON" is displayed. In the case shown, CP
Since the UII is not in the specified state, "BZ=" and LMP=" are displayed. 3) This allows operators and maintenance personnel to determine which CP LJ causes the buzzer or lamp to turn on.) You can know for sure if it is.

As described above, the following effects can be obtained in this embodiment. First, since the buzzer and lamp are commonly provided in each CPLJ, it is sufficient to provide only one buzzer and one lamp each. Therefore, the hardware is reduced and it is economical. Furthermore, reliability is high because the number of buzzers and lamps that have a high failure rate is kept to a minimum. Furthermore, the number of wires connecting the buzzer resistor and lamp resistor to the buzzer and lamp can be minimized, which is economical. Note that the new hardware provided in this embodiment is the sense register 41 and the system display area control program (firmware) in the ROM 36;
The increase in A is extremely small compared to the decrease in hardware such as lights, lamps, and wiring. Furthermore, identifying the CPU in the event of an abnormality by using a buzzer and a lamp in common for each CPU is done using a part of the display screen of the existing CRT 21, so it is economical.

The present invention has been described in detail above. In addition, a buzzer register and a lamp register are provided for each CPU.
It is also possible to hint only the flag in the buzzer register and lamp register related to + (without using the Jυ1 bit). In this case, each output of the buzzer resistor is connected to one buzzer 39, and the output of the lamp resistor is connected to one lamp 40 as a dot OR or OR gate. The sense register 41 senses the output of each buzzer register and lamp register.

Furthermore, in the above embodiment, either the buzzer 39 or the lamp is driven when the CPU is in a predetermined state, but one of the buzzer 39 and the lamp is driven depending on the content of the predetermined state. Very good this year. In this case, on the system display 1 rear 43 of the display screen, "" is displayed on the part corresponding to the buzzer 39 or lamp 40 that is driven for each CPU.
N″′ is displayed.

Further, although the system display area 43 is composed of two lines, it may be composed of one line depending on the screen size, the size of characters to be displayed, etc.

(Effects of the Invention) As described above, the present invention provides an economical system that can reliably notify external parties of which CPU is in a predetermined abnormal state with a small amount of hardware. M42 can be used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a diagram showing the contents of the ROM shown in FIG. 1, and FIG. 3 is a diagram showing the display screen of the display device shown in FIG. 1. 4 is a block diagram of the conventional system team configuration, and FIG. 5 is a diagram showing the contents of the 711 missing OM shown in FIG. 4. In the figure, 10.11μ central processing unit 1lf (CPU), 21 a display device (CRr), 22 a -1-board, 23 a driver/receiver (D/R), and 24 a microb[l processor (Ml processor)]. ″)U), 25.36 is RO~
1. 26 is a RAM, 27 is a screen memory, 28 is a screen control unit, 37 is a block register, 38 is a lamp register, 39 is a buzzer, 40 is a lamp, and 41 is a sense register. Figure 3 Fuushi≠Hairiai's ROM 72:l history (@Figure 5

Claims (1)

[Claims] At least two central processing units (10, 11), a display device (21) and a keyboard (22), and the content processed by each central processing unit (10, 11) is switched and displayed. In a system equipped with a control unit (100) that controls information displayed on the device (21), a controller is provided in common to each central processing unit (10, 11) when a predetermined state that should be notified to the outside is reached. a state notification means (driven by the central processing unit) that notifies the occurrence of the predetermined state;
37, 38, 39, 40) and the central processing unit that drove the status notification means (37, 38, 39, 40), and a system display area provided in a part of the display screen of the display device (21). (43) Display control means (36, 41, 24, 26, 28) for displaying information on the system status notification system.