JPH012354A - Transistor image sensor array and method for detecting images using the same, method and apparatus for sensing voltage signals - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

FIELD OF APPLICATION ON BEAM This invention generally relates to image sensor arrays, history [
In terms of 11A, it incorporates blooming control and
6, no measurable smearing,
The present invention relates to a line-addressed voltage beam modulated image lens array capable of zooming and panning. PRIOR TECHNOLOGIES AND PROBLEMS There are several basic device architectures in the art for constructing image sensor arrays. 2 of these
One is the frame transfer type and line address type architecture. Typically, such architectures have a plurality of COD devices arranged in rows and columns. For each COD photosite well, there must be another well adjacent to this one and separated by a barrier to receive the stored charge. Additionally, by requiring channel stops and well barriers,
Pixel density decreases. To prevent blooming, a train is formed in the channel stop, which takes up additional area of the array. Another type of imaging device is constructed according to a line-to-line transfer architecture. This kind of device is an empty CCD
It has several photosites, which can be either one or two. The photosites are separated by rows of COD elements provided to read the signals. Because it requires a CCD column,
Pixel density decreases. Since COD devices are used in this structure, channel stops and barriers are required, which further reduces pixel density. Yet another type of device uses an X-Y architecture. Each cell or element is individually addressed in the X and Y directions to read it. X-Y architecture includes CID, MOS transistor devices, and more recently, charge modulating transistor devices. In the C1,D device, two gates are formed, one connected to the dead line and the other to the row line. The CID7 ray has a long readout lead and therefore a large parasitic capacitance1, which reduces the dynamic range of the device due to the k T Cm,a associated with the long readout lead with large capacitance +a. becomes smaller. Furthermore, since each cell needs to be read out separately, reading out the entire 1b cell takes a considerable amount of time. High-density television systems (11D TV > format 1; L) require that the associated image sensor array be addressed and read within 53.5 microseconds of F! Therefore, in 1 Nj of a CID array device operating in II D TV format, 100
If there were 0 elements, each element in this row would be 53.5
It must be addressed and read within 10 seconds. This is very difficult to achieve due to the RC time constant associated with charging the read line, which limits the size of the CID image sensor array. Furthermore, due to the relatively large amount of time required to read the array, it is difficult to
Is it addressed by a small element and sent to Ikogi Ryo? The risk of 4 leaking increases, thus causing smearing. MOS transistor arrays suffer from the same problem as CID arrays in terms of long sense lines with high electrostatic charge velocities. Additionally, the charge from each addressed collector is not amplified, but is instead read directly to the sense lines. The pixel density of arrays in such devices is reduced by the need to form one or two transistors at each photosite for addressing. Recently, the Japanese Society of Applied Physics Journal No. 24, No. 5. Published on pages L323-325 (May 1985 issue) -
In the paper by Nakamura, Matsumoto et al., ``A new MOS phototransistor operating in a non-breaking intra-ring read mode'',
Charge modulation devices have been proposed. The sensor array according to this proposal uses the same X-Y architecture as the CID and MOS architectures described previously.
17, and therefore suffers from the same dynomic range and Daruma problems as other X-Y addressed architectures. These excessive image sensor manufacturing variations result in undesirable "pattern noise." Pixel density constraints and the architectures conventionally described for such devices do not provide enough flexibility to perform operations such as electronic zooming, panning, and auto-flj exposure control. Given the requirements of small pixel size and relatively fast addressing and readout, separate addresses for each element in a row with 1 = 100 elements to improve resolution. The designation has not been achieved on three devices within the HD TV horizontal reading period. Furthermore, recently introduced electrically modulated transistor devices modulate the output current rather than the voltage. The signal current from such an element varies as a function of both the dimensions of the element and its inherent threshold voltage.In order to reduce the pattern noise γ1 due to these two sources, it is possible to reduce the pattern noise γ1 by varying these parameters m. It was necessary to limit the material to a tolerance of 0.5% or less. As pixel dimensions become smaller, such strict control becomes increasingly difficult. Therefore, the industry knows that manufacturing variations between sensor elements with respect to doping and direct voltage (direct voltage), pattern noise, etc.
There is a desire for image sensor arrays that do not cause Additionally, the industry is aware of the need for a transistor image array architecture capable of electronic zooming, panning, and exposure control, as well as operating in high-density television control applications.
exists. Finally, the industry has blooming control 21
There is a need for an image sensor array that has a value of 0.1 and no measurable smearing. One aspect of the present invention provides an apparatus for sensing a voltage signal that is proportional to the number of photons of light that enter a sensor element during a selected charge integration period. This device has a sensor element with a unique threshold voltage. The sensor element may be operative to accumulate charge in response to light incident thereon and to have a changed B-value voltage in response to the accumulation of charge. The output voltage of the device changes as a function of the change in threshold voltage. A sampling circuit samples the output signal at a first time before removing charge from the device and at a second time after removing charge. A sampling circuit derives a change in voltage from the sampled output signal. A signal buffer consisting of a register, such as an array of capacitors controlled by a COD register or horizontal scanner, is coupled to the sampling circuit and stores the charge related to the derived voltage changes. One advantage of the present invention is that by generating a voltage signal rather than a current signal, sources of pattern noise due to sensor cord size and impurity variations are minimized. Another advantage is realized by sensing differences in voltages that are not directly related to the intrinsic threshold voltages of the elements.The unique threshold voltages of each element are attenuated and eliminated when processing the signal, thereby reducing the amplitude of the pattern. This source of noise γ is minimized. Another aspect of the invention provides a transistor image sensor array, the array comprising at least one
It is collapsed into a plurality of transistor image sensors arranged in rows and columns, with each transistor accumulating a charge in response to light incident on its region. The column line for each column is connected to the source of the sensor element(s) in that column.The row j selector for each row of sensors is connected to the source of the sensor element(s) in that column. A selector selects one row and applies a pulse to the selected 1j. Each of the plurality of sampling circuits is coupled to the column line of the people, and the selector selects one row and applies a pulse to the selected row. The voltage difference 1 [difference 1.-] which changes as the output voltage of the selected sensor 115 is sampled. A buffer is coupled to each column to simultaneously receive and store the voltage difference signals across the column lines.All columns can be read out in parallel to the buffer. This provides another advantage in that it eliminates the time wasted serially reading out each element in a row of the array, so the spread due to good column lines is less of a problem. 1 outputs the voltage signal serially from the buffer, which is a much easier task since it does not involve good column lines. The buffer in one embodiment consists of a pair of COD registers, one for each column. On the other hand, the V signal charge is input into the second COD register to the voltage rE group corresponding to the normal source voltage plus the difference of the voltage J'EI threshold 1fi of the selected image sensor element in that column. and the third signal charge corresponding to a normal source voltage that does not exceed the threshold X e f'l!
It is placed in the COD regisc. By reading out the 33rd signal and the reference signal simultaneously, it is possible to read out 16 voltages that are proportional to the difference in voltage 1 ifl and thus proportional to the number of charges stored in the addressed sensor. Another example buffer is comprised of an array of storage elements or capacitors coupled to each column line. A switching transistor for each memory transistor is
It may serve to couple the output sense line to the output sense line. Each switching transistor is activated by a respective stage of horizontal scanning. Another advantageous aspect of the present invention is to provide a method for operating the above-described array in a manner that allows for electronic goo 601 creation and panning. In the case of a single electronic zoom, the rows are encoded in such a way that every other (j) is addressed, rather than addressing each adjacent row. In normal operation, A buffer consisting of a COD register, etc. is - subjected to a first high speed O-tsuku operation, so that only every other pixel in the selected row is sampled at the output corner of the register. In addition, the clock speed may be increased further and only one of many pixels sampled. If a zoom operation is required, the buffer value may be increased by 0 and the value reduced by -1 for each pixel in the selected area. pixels are sampled at the output.The F and lower limits of the zoomed part of the array are determined by which line is addressed, and the left and right limits are determined by the preshift of the clock in the COD register. The portion of the array that is subject to zooming is determined by the number of row lines, the amount of preshift of the clock in the buffer, and the number of offsets. By changing the end of the clock operation, the clock operation can be performed from one location to another. Another embodiment of the present invention provides a COD register, at least 51 of which is in each node Z column. Multiple notes such as those provided for t!11-Yabashita and this note ↑%=
Replace the p-passacitor with multiple switching transistors connected to one or more output sense lines. The switching transistors are υ controlled by stages of horizontal scanners. Each step of Suyana is made fh
Make it so that it receives the signal I11! ! 7ru. This additional reading stage adapts the zoom operation to 11". Under normal conditions, where no zoom operation is required, the row decoder allows one a3 x ?J element to be selected. The row decoder can be activated to skip over several adjacent rows. The sensed voltage difference signal is stored in an array of storage capacitors. Sequentially in every other stage By applying the fjJ signal, every other storage capacitor can be read out.
They can be separated from each other by several non-read capacitors. When a zoom operation is requested, a row decoder selects every row within the zoomed section and a horizontal scanner selects every column within the zoomed section. subject to zoom action.

The "" section allows you to pan from one location to another by changing the row and column addresses. Another aspect of the invention provides an electronic exposure control device. Familiarity is the intrusion sensed by addressing adjacent row lines,
Each stroke is addressed and sensed, allowing it to accumulate charge until the entire array is addressed and read. This is the case in non-interlaced operation or in so-called sequential scanning. In the case of interlaced scanning, one field has (
The situation is similar, except that in the second field we read the odd lines (for example) and the even lines in the second field. In an electronic exposure control system, a line can be addressed first and then reset after a predetermined period of time to shorten the charge storage interval. For this reason, a batting line reset address that is smaller than the number of lines in the array body and different from the row line sensing address is selected. The line to be reset is addressed within the same horizontal blanking interval as the line being sensed. However, reset 1~・
A reset pulse is applied to the addressed line,
No signals from it will be detected. Therefore, less charge integration time is available for each sensed line of the sensor. Since the voltage Mv4 time to the array can be varied by changing the difference between the sensed line address and the reset line address, it is possible to can achieve the ability to The invention and its advantages will become more apparent from the following detailed description of the drawings. 1. Referring first to FIG. 1, there is shown a simplified plan view of the on-chip arrangement of the present invention. The imaging device is indicated generally at 10. The zero imager 10 includes a sensor array 12 that occupies most of the chip area. row decoding i! :1
4 are placed on one side of the array 12. A row decoder 14 is connected to a decoding vine driver 16 . A sense line bias switch area 18 is located on an adjacent side of array 12. A capacitor and clamp transistor area 20 is shown adjacent column line bias area vi18 in the illustrated embodiment. Column line bias area 14184 may be located on the side of array 12 opposite capacitor and clamp transistor area 20. An output sofa, generally designated 22, is located adjacent to the capacitor and clamp transistor area 111120. In the embodiment shown in FIG. 1, buffer 22 is comprised of a pair of COD registers 24 and 26. A first transfer gate area 28 is a capacitor and a Krambe transistor area 20 and a first COD register area 2.
It is located between 40 and 40. Second transfer gate area 11!1
30 is disposed between the COD register 24 and the COD register 26. A third transfer gate area 32 is located between the COD register 26 and the drain 1 area 34. Reset gate area 11! 36 and 38 are CC1 respectively]
The number is set on the output side of registers 24 and 26. Reset gate areas 36 and 38 are connected to charge amplifiers 40, respectively.
．． 42. Their respective electricity? iii I? The differential voltage output Vo is sensed by the output 44.46 of the single-width amplifier. Imaging device 10 has multiple voltage sources and signal inputs. A drain voltage source V supplies power to the sensor 12. Similarly, voltage source VDD2 is T
i Supply the center force to the load spanner 4042. Voltage source V
supplies power to the FJ8K1FJ)^16. Supply bias to the voltage source 1 (source V is the buffer) 122. Row decoding′! A14 is provided with a high bias or pulse source VH and a low bias voltage source vt-. The decoder driver 16 may have a TTL input address bus 48, which in the preferred embodiment is comprised of nine address bit lines. Alternatively, bus 48 may be replaced with a shift register. At this time, nine address bits are shifted in serially and read out to driver 16 in parallel. The COD registers 24 and 26 are supplied with clocks φ, 1 and φ8□. Transfer gate area b12
8. A transfer gate pulse πmiφ1o is installed at 30.32. Charge amplifiers 40,42 are provided with a ground source 50. Capacitor and clamp transistor section 1
A clamp pulse source φ (clamp) 120 is provided. Finally, the column line bias area 18 includes a bias
A clock 52 is provided. FIG. 1 shows only one possible shape of the imaging Vli 10. In other embodiments, if it is desired to drive the address lines of array 12 (described later) from both sides, the range
The same row decoder 14 can also be placed on the left side of the array 12. In yet another embodiment, row decoder 14
can be replaced by a vertical scanner consisting of switches and shift registers. Further, and referring specifically to FIG. 3a, the COD registers 24.26 and transfer gates 30.32 can be replaced by arrays of storage capacitors and horizontal spaces having multiple stages. In FIG. 2, a small portion of the hinge array 12 is shown.
It is shown schematically together with the peripheral circuitry consisting of: Sensor array 12 is comprised of a plurality of transistor sensor elements 60. Array element 60 has a plurality of rows 62
and columns 64. Instead of this, the array 12, as in a line scanner,
It may be configured with only 111 elements. Each array element 60 has a drain 66, a source 68, a gate region 70, and, in the illustrated embodiment, a gate 72. Gate 72 can be replaced by an equivalent capacitor (not shown in the drawing) formed at each photosite i on a portion of gate region 70. each source 6
8 is connected to column line or sense line 74. 914127
4 are provided for each row 64 of sensor elements. Each drain 66 connects to ■oo1 via a voltage supply line 76.
connected to. Each gate 72 corresponds to a row line or address I
! ; connected to 178. One dot line 78 is provided for each row 62 of sensor elements. As previously mentioned, only a small portion of sensor array 12 is shown in the drawing. In one embodiment, array 12 is 980 pixels by 11
There are 20 paintings, and each pixel or element 60 is hexagonal and approximately 5 microns by 5.8 microns. Other shapes and dimensions of the elements are also possible. The sensor element 60 responds to the incident light in the gate region 7o.
Accumulates charge in m and responds to the threshold value of the element fri
This type changes the voltage. One type of filling voltage modulation sensor element can be made as follows. Implant (N-) buried channels into the (P-) semiconductor layer. Next, two NF type regions are formed to form a drain 66 and a source 68. N+ type regions forming the source 68 and drain 66 are separated by a P type gate region 70. The gate region 70 is differentially doped to create a potential well for accumulating holes in response to the Okawa light and a potential well for the O-bube current. The hole potential well can be formed by implanting a boron. The probe current can be formed by using phosphorus. The device is constructed in such a way that the excess holes accumulated at a single potential overflow into the substrate, allowing automatic blooming control. Each (j line or address line 78 is connected as the output of the contusion n unit 14.As will be explained later, the 11 address line 78 of the 1st tree in which the contusion number m14 is selected is connected to the source 1- 1
and connect the remaining unselected batting lines 78 to the low bias source 1. A 911 line bias transistor 80 is provided for each line 74. The drain of each transistor 80 is connected to the column tQ
74. The gate of each transistor 80 is connected to column line bias source 52. The source of each transistor 80 is connected to ground or a suitable return line such as 88. Each column sense line 74 is further connected to a respective coupling capacitor (FIG. 3), which is coupled to the elements in the COD register 24 via circuitry that will now be described. COD register 24 is coupled to a second COD register 26 by transfer gate 30 (FIG. 1), and registers 24 and 26 are operated together in a manner as will now be described. For this reason, array 12 is connected in parallel to COD register 2.
4 and 26, and then the output appears in series at the main cylinder amplifier outputs 44, 46. Referring now to FIG. 3, the sensing circuitry for one selected sensor element 60 will be described. A source 68 of each sensor element 60 is connected to a sense node 79 . A sense node 79 is connected to both the current path of the sensing column bias transistor 80 and the coupling capacitor co. capacitor co
is the capacitor and clamp transistor section 1420
(FIG. 1), is connected to node 82. The current path of clamp transistor 84 is i! The gate of the clamp transistor 84 is controlled by the clamp clock φ (clamp). Furthermore, the node 82 connects the current path of the transfer gate 1 to the transistor 86. Transfer gate transistor 86
The other end of the current path is connected to the input diode 1liI88 of the first COD register 24. The gate of the transfer gate transistor 86 is the transfer gate clock φ■6
controlled by The COD register 24 is composed of a plurality of gates. Although 161 pairs of gates 90.92 are shown corresponding to sense line 74, it should be appreciated that at least two COD gates are provided for each column 64 of array 12. A COD gate clock controls gate 92. Gates 90 with alternate gates φ, 2
υItll. The COD register 24 described here is a two-phase CCD register, but instead, a virtual phase CC
5 using other types of COD registers like D registers.
good. Additionally, buffer 22 (FIG. 1) may be constructed with other storage and serial readout structures, such as an array of storage capacitors and one or more horizontal gaps, as discussed below with respect to FIG. 3a. I can do it. FIG. 4 shows a circuit diagram of a portion of the row TU encoder 14. For clarity of the drawing, only two bits of the nine bit address used in the preferred embodiment are shown. That is, bit A and bit B. Complement numbers 8 and B are generated by decoder driver 16 from the code provided on address bus 48 (FIG. 1). The decoder 14 receives a first matrix 94 and a second matrix 96. Matrix 94 is formed by b 178 crossing each of the m bit lines 98 from row decoder 14 . To decode the address on bit line 98, a decoding transistor 100 is formed at a selected intersection of dot line 78 and bit line 98. a current path formed in the row line 78 of each decoding transistor 1oO;
and have gates connected to respective bit lines 98. Each batting line 78 is connected to the ■H supply bus 101. Thus, when a correct address is received, transistor 100 on any one row line 78 connects that row line to the high bias voltage source V1. The remaining lines are disconnected from VH. Matrix 96 has row 1!1i78 and bit line 102°1
It is formed by the crossover of 03. Bit line 102.10
3 may be electrically connected to the corresponding spring 98 or may be provided separately from the decoder driver 16 (FIG. 1). A plurality of decoding transistors 104 are formed at each intersection of bit line 102 or its complement 103 and a respective row line 78 . The drain of each decoding transistor 104 is
It is connected to the L supply bus 105. each transistor 1
Gate of 04 bit line 1 for true address bit
02 or its complement. The gate connection of transistor 104 is chosen such that matrix 96 connects all unselected row lines 78 to low bias array voltage bus 105. As will be explained later, by providing the row decoder 14 in place of the four vehicle nose skies, electronic zoom,
Pan action and self! Fl] The advantage is that exposure control can be more easily realized. A circuit diagram of charge amplifier 400 is shown in FIG. The illustrated circuit is similarly provided for main amplifier 42 (FIG. 1). The COD register 24 is comprised of a series of gates controlled by φ,1 gates 92 and φ,2 gates 1-93. COD register 24 ends with a standard floating diffusion detection node 106. The sensing node and transistor 108 are sized optimally for the best signal-to-noise ratio. Detection clause 106
is connected to the current path of reset gate transistor 36 and embedded channel transistor 1
Also connected to the gate of 0B. A current path of transistor 108 leads from voltage source 002 to node 109, which node is connected to the gate of surface channel transistor 112. A current path of surface channel transistor 112 leads from voltage source V 2 to output terminal 44 . Therefore, the signal proportional to the charge detected at node 106 is
The signal is buffered by a two-stage source follower device and output to the detection node 44. Transistors 114 and 116 are buried channels and thus act as a common source to provide bias for transistors 108 and 112. A current path for reset transistor 36 is at line 124 and is connected to a reference generator, generally designated 118. The reference generator 118 has a transistor 120 and a transistor 122, which use the same doping 11 traces used to construct the CD resistor 24, or
It is convenient to have, and its current paths are connected in series. A line 124 is connected to the midpoint between the current paths of transistors 120 and 122 and connects this midpoint to the current path of reset transistor 36. transistor 12
The drain of transistor 122 is connected to voltage source VDD2, and the source of transistor 122 is connected to ground. The gates of I-transistors 120, 122 can be grounded or connected to a reference source. The source of transistor 122 and the gate of transistor 120, 122 may alternatively be connected to a suitable VSS return line. Next, the operation of the image forming apparatus 10 will be described with reference to FIGS. 1, 3, and 6. FIG. 6 is a diagram showing the operation of the image forming device 10. Decode driver 1 from bus 48
6 is supplied with an address. The decoder driver 16 supplies this address to the row 1 encoder 14 via the bit line 98°102.103 (FIG. 4). Row decoder 14 selects a particular strike line 78 to connect to VH and connects the remaining row lines 78 to source v1-. (2) is connected to only selected rows and is pulsed to reduce signal interference caused by them. The address of batting line 78 is shown at 130 in FIG. The selected row line is assigned a number Qk. Addressing of the selected row 78 occurs within the horizontal blanking period 132, which is compared to standard NTSC
In both the television system and high density television (HDTV) applications, the time is about 10 microseconds. Horizontal blanking m interval 1
32 intersects q with the horizontal reading period shown at 134 in the graph of φ, 1, 2. At the beginning of the horizontal blanking period 132, the sense line bias transistors 8 for all columns 64
0 (FIG. 3) and turn on at 136 (FIG. 6). To conserve power, sense line bias transistor 80 was previously turned off. When this poem was young? ! 3314 becomes 138 (Figure 6)
ends connecting all the unselected lines to v to eliminate any interference of the 1!1 signal originating from the elements 60 of the unselected rows. At 11 o'clock, the blooming control is deactivated on the unselected rows, but the period is so short that no signal interference is expected. 1
At 40, the φ (clamp) pulse turns on the clamp [- transistor 84. By this, the right side of #Sebashita co (Figure 3) or node 8 of the electrode
Based on 2, t\゛ichi1■ is set. At this time, the voltage at node 79 on the H side of the resistor Oo approximately corresponds to V + h. vS is the voltage normally present at the source 68 of the sensor element biased by transistor 80 (FIG. 3); This is the differential A-value voltage component. The voltage at node 79 becomes equal to the voltage at source 68 after some RC time period of line 74 (FIG. 3). While φ (clamp) is applied, the voltage at the right node 82 of capacitor C is set to V and OREF. This is preferably chosen to be about 5 volts. In the embodiment shown in FIG. 3, VREF is the COD register 24 (third
(Figure) should be selected so that it is compatible with reading. In another embodiment, V should be made compatible with the storage capacitor EF capacitor circuit if used. At time 142 (FIG. 6), the J3 quasi-voltage ff,V is sent to the input node 88 of the COD register 24 by pulsing the transfer gate 86. 11[, F After transferring the reference signal to the COD register 24, the time 14
4, transfer gate 86 is turned off and node 82 is unclamped. Other time orders are also possible. for example,
A clamp pulse may occur long before the transfer pulse. This causes the capacitor C to become
Separated from Lr. At this time, the voltage at node 82 is allowed to float. Next, by pulsing the Vt1 array bias high at time 146, the gate ff1till! Empty the hole potential well at 70. At the same time, the clock φs2 of the COD register is pulse-driven at 148.
This is in preparation for the transfer of the charge corresponding to the voltage reference signal to the second COD register 26 (FIG. 1), which occurs at time 150. The COD register 26 has a similar configuration to the COD register 24, and is designed to store charges corresponding to the voltage reference signals of the elements in the selected row. The COD register 24 is provided to store charges corresponding to voltage differences and signals. By emptying holes from the potential well in gate region 70, a voltage signal approximately corresponding to VS appears at node 79. The vh acid component is removed in response to hole shielding. Since the voltage at node 79 has dropped by Vh, capacitor c
The floating right side of o is correspondingly driven to V - V. This R[r voltage difference signal is transferred via transfer gate 86 to the input of COD register 24 by transfer gate pulse 150. At the same time, the charge corresponding to the voltage reference signal is transferred to the second C
Transferred to OD register. Thus, within a preselected integration period, Goo! - It is possible to extract the difference signal (■,) that changes directly with the photons accumulated in the region 70. The outside voltage 1λ is unrelated to the specific power output V of the Sen 4J Yuko 60. Therefore, variations in VL or physical dimensions from sensor to sensor are the source of the pattern 211 & (
Avoid it. Similarly, since the charges corresponding to the voltage FA quasi-signal and the charges corresponding to the voltage difference signal are processed by the same circuit, sources of this noise noise, such as variations in the input well dimension d1, are also avoided. . stomach*'? ini pressure (VREF V 1.) 4i:
By transferring to L' register 4 (7) input,
The basic signal transfer sequence from array 12 to serial registers 24,26 is completed. 1 and 2, this sensing and transfer process is performed simultaneously for all columns 64 of sensor elements 60, thus CC1)
Each well is filled over the entire length of the register 24,26. When the horizontal reading stage Fj 134 (FIG. 6) is started, the charge corresponding to the input voltage and reference voltage stored in the COD register 24.26 is transferred to the main cylinder amplifier 40.42.
is read out via output 44.46. A differential voltage signal corresponding to one Vh for each house is output from output 44 and output 4.
It can be determined by comparing 6. The parallel read method of the present invention allows one hammer to be read in parallel into the buffer 22 (FIG. 1) within a very short period of time without noticeable signal interference from unaddressed rows.
An important advantage is that individual υ° elements can be read out. Conventionally, the X-Y image sensor array is read row by row, but row by row. The architecture of the invention is more suitable for HD TV (High Density Television) applications since more time can be taken for addressing and readout, and therefore parallel readout is independent of the number of elements in a row. ing. Another embodiment of the invention is shown in FIG. 3a, in which the COD resistor 24 (FIG. 3) is replaced by an array of storage capacitors and associated 16 stages of horizontal scanners. As before, the coupled Yayapashita co generates a voltage difference signal at node 82. A transfer gate may act to transfer this signal to storage capacitor 160. storage capacitor 16
0 is connected between node 162 and reference voltage 164. Node 162 is connected to first output line 168 via a switching transistor 1660 circuit. The gate of transistor 166 is connected to a horizontal scanner stage 170, indicated generally at 172. In the illustrated embodiment,
The sensor elements of the adjacent column are coupled to a node 174 which is connected to a storage capacitor 176 for the beam 11 . Node 174 is ffJ of switching transistor 178
It is connected to the second output line 180 via the f path. Second
The gate of the switching transistor 178 is connected to the second stage 182 of the horizontal scanner 172. In operation, row line 78 selects a row of elements 60. In operation, row line 78 selects a row of elements 60. The electric current r=difference signal from each selected element is
Due to the action of a plurality of transfer gates such as the transfer gate 86, 160.176 snowflakes are transferred to the turning section. The voltage stored in the storage capacitor 160°176 etc.) is then transferred to the switching transistor 166.178'5.
(1) The signal can be transferred serially to the output lines 168 and 180. These gates are horizontally spaced 17
2, preferably 16 adjacent stages 170, 182, etc., respectively. In one embodiment, an activation signal E (not shown) is propagated to successive stages 170, 182 to sequentially activate switching transistors 166, 178. In another embodiment, C nxian'r-3 (not shown in the drawing) can be randomly applied to any selected stage 170, 182, etc., and thus any storage capacitor 160, 176'
The order in which S is read can be selected. In the embodiment shown in FIG. 3a, electrical zoom and pan operations are relatively easily performed. Addresses of selective rows within the zoomed section can be selected by a row decoder, and addresses of columns to be read in the zoomed section can be selected from horizontal columns 170, 182, etc. It can be selected by addressing the current location. Panning can be accomplished by simply changing the addresses of the rows and columns being addressed. The COD registers in Figures 3 and 5 allow standard 1
Because one row of elements can be addressed and stored within one horizontal blanking period of a television set of 0 microseconds, the architecture of the present invention combines electronic zoom and pan operations with electronic aperture. ” or automatic exposure control. First, the features of the electronic automatic exposure control of this invention will be explained. In normal operation, each of the sensor elements 60 (FIG. 2)
2 are sequentially addressed and read. The remaining rows 62 are then addressed and read before the first row is selected again. Therefore, the charge integration time for any one row of elements is equal to the total number of rows in the array times the time to address and read each row. When the distance between charge accumulation in each gate region 70 becomes λo, it becomes practically the same! IJ3 nine outputs i+'l mt and 1 electron aperture" can be obtained. - early in the morning at gate 72
When reset pulse 151 (FIG. 6) is applied to (FIG. 3), less metal is deposited to accumulate charge in response to the input rA. One way to do so is to take address l as the number of the line away from address k, and use the same horizontal return line: I"1 person 11
and selecting the second addressed row line at 152 (address 1) within the interval. A reset pulse 153 is applied to all gate regions 70 in row 1, but in this row the resulting voltage X signal is not transferred to register 24 or 26. For example, if there are 525 tree lines and the normal address and readout period for one row is t, then the normal main storage time is 525t, and the mechanical aperture with a width of 1; I will respond. If another address 1 is chosen that is a number of row lines away from address k, then the new integration time is (525-(kl))t. The integration time is correspondingly shorter and thus corresponds to a partial closing of the mechanical diaphragm. The architecture of this invention is that the automatic exposure t111 l
suitable for This is +fl for each photo 1 night.
This is because the configuration can be reset at any time, and all operations on the readout signal are performed within the horizontal blanking period rather than during the readout period. Returning to FIG. 6, the column line is the dummy row address 1.
54. This address is also used to provide the appropriate bias for the Sen+J elements during the readout period. The invention can also be used in systems that allow electronic zoom and pan operations. The array element 60 (FIG. 3) of the present invention is relatively small compared to conventional pixels, and therefore
It can have a density at least twice that of conventional sensor elements. When the imaging device 10 is used in a device capable of operating an electronic zoom operation, every other line 7
8 (FIG. 2) can normally be addressed for reading, or several lines can be skipped. For any particular row 78, every other pixel or element 60, or alternatively every n pixels, is sampled at outputs 44 and 46. Image degradation does not occur because the density of the imager array 12 is at least twice that of normal. In normal operation of this scheme, decoder 14 (FIGS. 1 and 4) decodes each row 7 for addressing and reading.
If you want to use every other row 78 or sequential scanning instead of 8, select number 3 [11 in one corner. Only every other pixel in the selected row is output 44.4
It is sampled at 6. When a zoom operation is desired, the address selection and readout performed by the row decoder 14 changes φs1,2. For example, sensor array 1 instead of the entire array
Assume that we only want to read out the upper left quarter of 2. To avoid loss of resolution, each row I! in the selected partial area, rather than every other row line! Address j178. Similarly, in order to pick up every pixel in the addressed row line, the clock φ
, 1 and 2 are decelerated to half the frequency when not in zoom operation. Row line 78 where the top and bottom of the zoom area are within the desired enlargement area
selected by selecting only . The left side of the zoom area is selected and defined by a preshift of one CCD register at 156 in FIG. This pre-shift starts the operation of reading the COD register during the horizontal blanking period, and the actual horizontal read phase is during tJ(
1, the information for the predetermined number of doors in the selected row is emitted to the output node of the COD register. 31. The right side of the enlarged area stops the read clock φ.
2 Therefore, you can choose. In this way, the number of columns read can be limited. Unused charge stored in registers 24-26 is automatically transferred to drain region 34 (FIG. 1) during the next horizontal blanking period. Since the vertical decoder 14 has irregular access to the row lines 78, the portion to be zoomed can be panned vertically by changing the selected row line 78. The portion subjected to the zoom operation can be panned in the horizontal direction by changing the period of the pre-shift of the zoom function and the interval between the registers 24 and 26. In summary, an image sensor array has been provided that senses and stores signals that vary as modulated threshold voltages of addressed centers. A method and apparatus has been described that eliminates inherent threshold voltage or other manufacturing variations as a source of pattern noise. Furthermore, the array of this invention
It is considerably more flexible than conventional X-Y addressed image arrays, providing features such as automatic 171 exposure control, electronic zooming, and electronic panning. Because the voltage difference signals are read out from the array into registers in parallel, sources of smearing are minimized. Although preferred embodiments and advantages of this invention have been described, it goes without saying that this invention is not limited thereto, but rather by the scope of the claims. Technical advantages of the invention: The element changes the direct voltage rather than the current, +1! One advantage of the present invention is achieved by a sensor array that does. By sensing and storing signals related only to the voltage accumulated on each sensor element's potential, sources of pattern noise due to inherent II la lightning voltage fluctuations and Ixl structural variations of the pond are eliminated. Minimized. Another advantage of the invention is achieved by using a rework decoder or shift register. This allows address row lines to be accessed from J$21111, allowing the array to perform automatic exposure control, electronic zooming, and electronic panning. The architecture of the present invention is different in that the time required to address and read the elements of a row of elements is independent of the number of elements in the row because the readouts are done in parallel. 1 point. Therefore, the architecture of the present invention is better suited for high density hemp television ()-IDTV) applications. Further, the present invention suppresses violet ring to 111 microeyes by using 1) serial readout of voltage difference signals to registers. In connection with the above description, the following sections are further disclosed. (1) A plurality of transistor image sensors arranged in at least 1 hour and divided into a plurality of columns, each transistor sensor having a width of 04"!
13, having a gate region that accumulates charge in response to light;
The voltage +51a value of each gate region can be actuated to vary according to the accumulated charge ω, and each sensor has a source region in the history, and a pair of IIFJ in each column and the above-mentioned coupled to the source area and further acts to address said at least one row; 1! ? a selector,
a plurality of circuits each coupled to a respective column line for sampling and storing a voltage difference Δ1] proportional to a change in source voltage of a selected sensor V in said sensor 911 due to a changed dark value voltage of said sensor; Lt sampling circuits are coupled to the da
8 storage means for receiving and storing the voltage difference signals in series, and an output for serially outputting each voltage difference signal from the storage means. (2) In the transistor image sensor array described in paragraph (1), a reference voltage selectively coupled to each sampling circuit and used to collect the voltage difference signal; , a first register of said storage means for storing a charge proportional to said voltage difference signal; and a first register of said storage means for storing a charge proportional to said voltage difference signal;
A transistor image sensor array having a second register of said storage means for storing a charge proportional to a reference voltage for the circuit, and a second output for serially outputting the stored reference voltage. (3) In the transistor image sensor array described in item (1), each sensor has a drain connected to a voltage source. (4) In the transistor image sensor ◆ array listed in paragraph (1) above, the selector may be operative to apply a predetermined pulse only to the at least one row, and the pulse is can act to remove accumulated charge from the gate region of each of the rows, such that the normal source voltage of each transistor in (j)
The source voltage of each sensor in the row is supplied from a bias source coupled to each source region, and the source voltage of each sensor in the row is applied to the respective gate gate 1i1! The transistor image sensor array returns to the normal source voltage in response to the removal of the accumulated voltage from the transistor image sensor array. (5) In the transistor image sensor array described in item (11Q), a decoder in which the selector is operable to address the at least one row in response to a received row line address. (6) In the transistor image sensor array described in paragraph (5), the array has a plurality of rows Ill#5, and the decoder has a plurality of rows. A decoder driver is provided which generates a binary address having @ address bits, and each address bit is outputted from the decoder driver to a respective bit line and output to the decoder driver. A first matrix is formed therein from bit lines and row lines connected to each row, the matrix being operable to connect a pulse source to a selected row line; Transistors are formed at selected intersections of the bit lines and row lines, the gates of each transistor are υ1 aligned with the bit lines, and the current path of each transistor is formed in the respective dots, and each dot line A transistor image sensor array whose - end T is connected to the pulse source. (7) A transistor image sensor array as described in No. (6) Ir!
In an image sensor array, the decoder includes a second matrix formed in the decoder from the row lines and the bit lines, connecting a low array bias source to unselected strike lines. and a second transistor is formed at the selected intersection of the bit line and the row line, the gate of each second transistor is coupled to the bit line, and the gate of each second transistor is coupled to the bit line. A current path connects the dot to a low array bias source.
Image sensor array. (8) In the transistor image sensor array described in item (1), the transistor image sensor array includes a vertical shift register. (9) No. (1) lrtc: 1 mounted transistor
In the image sensor array, the storage means includes:
. each having a plurality of storage capacitors coupled to the column lines for storing respective voltage difference signals, and at least one output sense line for each column; a sense line switch operable to couple a memory r1/pacitor for said column to said at least one sense line, and having a plurality of stages, each stage responsive to receiving an activation signal. , a transistor image sensor 7-ray with a horizontal scanner that can act as a respective sense line switch 111. (10) In the device δ that senses a voltage difference signal proportional to the number of photons accumulated in the dark at a selected integration time, a sensor element that accumulates charge in response to incident light is The sensor element T is operable to have a threshold voltage that varies in response to the product charge, the output signal of the element varying as a change in the threshold voltage, and further at a first time and from the element. a sampling circuit coupled to the sampling circuit for sampling the output signal at a second time after the voltage A1 is removed and deriving a change in threshold voltage from the sampled output signal; A 5A device with a buffer that stores a voltage difference signal that changes as the threshold voltage changes. (11) In the device described in item (10)rll'i, the sensor element is a transistor having a gate, a source and a drain connected to each other, a supply voltage is connected to the train 11, and a reset source is connected to the gate. selectively coupled to periodically remove the accumulated charge, the output signal appearing at the source, a bias source coupled to the source,
A normal source voltage is generated at the source, and the output signal is the normal source voltage plus a change of @m voltage (directly equivalent device. (12) In the device described in paragraph (10) a reference voltage source selectively coupled to the sampling circuit for providing a base voltage, the sampling circuit having a first terminal receiving the output signal and a second terminal coupled to a buffer; , the reference voltage is supplied to the buffer at a first time, and the sampling circuit has a terminal of i
Base 11 t1! Apparatus for transmitting to said buffer a signal proportional to the difference between the change in voltage and a threshold voltage. (13) In the apparatus described in paragraph (12), the sampling circuit includes a capacitor, a first side of the capacitor receives the signal, and a second side of the capacitor receives the buffer signal. selectively coupled to the voltage, the voltage is applied to the second side at the first time, the reference voltage is transferred to the register at the first time, and the reference voltage is transferred to the register at the first time;
side was allowed to float after the first time, and the second side entered the first side. Apparatus responsive to a change in the sampled output signal to vary from the reference voltage to a voltage difference signal, the voltage difference signal being stored in the register at the second time. (14) In the device described in item (13), υ acts to transmit the quasi-voltage and the voltage difference signal from the capacitor to the buffer? equipment with a transfer gate. (15) In the device 1 described in paragraph (13), the reference voltage source connects a clamp transistor having a gate and a current path, and the current path of the clamp transistor connects the reference voltage source to the capacitor. The gate of the quack clamp transistor Ivi is connected to a clamp pulse source which actuates the clamp transistor at the first time. device to do. (16) In the device described in item (13), the output No. 18 at the first time is I! generated by the accumulated charge at the normal source voltage. The output signal at the second time is equal to the normal source voltage without adding the voltage difference between the two directions.
Place A. (11) A device in which the buffer described in item (10) (d) is configured by a COD register. (18) In the device N described in item (10), the buffer is a storage capacitor. (19) In a method of sensing a voltage signal proportional to the number of photons accumulated by a sensor element within a preselected integration period, the sensor element accumulates a charge in response to light entering the sensor element; varying the dark value voltage of the sensor element in response to the accumulated charge and delivering an output signal from the sensor element that varies as the dark value voltage changes; Output at 'i' time (sample g, remove the W rectifier charge from the sensor element after the first time, sample the output signal at the second 0,'i time after removing the charge) , from the sampled output signal to the threshold (1 "[
A method comprising one culm for deriving changes in voltage and storing voltage difference signals varying as 1:I l + main voltage changes. (20) In the method described in paragraph (19), further:
The sensor element outputs a first output signal equal to the normal source voltage applied to the element plus the difference in dark value voltage caused by the accumulated charge, t. applying a first output signal to a first electrode of the main shibashita;
At the first time, a base r is applied to the second electrode of the shock absorber.
Jl voltage, transfers a charge proportional to the base*voltage to the register at the first time (11), and at the second time a second time equal to the normal source voltage with no difference in dark value voltage. outputting an output signal 11 from the sensor element, applying the second output signal to the first electrode of the capacitor at the second time, and applying the second output signal 4ii to the first electrode. 4
changing the voltage of the second electrode from the reference voltage to the voltage difference signal at the second time in response to applying .
A method comprising transferring a charge proportional to the voltage difference signal to a resistor. (21) In the method described in paragraph (20), the voltage difference signal is obtained by subtracting the difference in dark value voltage from the reference voltage by A (equal to 1n). (22) The voltage difference signal is arranged in rows and columns. A method for detecting images using an array of transistor image sensors includes selecting a row of image sensors and accumulating a charge in each sensor in the selected row in response to incident light. , changes the dark value voltage of each sensor in the row in response to the change in the accumulated charge, and transmits a first voltage signal that varies as a function of the change in the threshold 1a voltage to each transistor in the (1) - Sensing with the source of the image sensor, storing the reference signal for each sensor in the row, transferring the quasi-signal of the 1□ to the buffer, removing the accumulated charge, and calculating the dark value voltage caused by the accumulated charge. A second voltage signal, which differs from the first voltage signal by a fraction of S11!, is sensed at the source of each transistor, and for each sensor, a respective r
Form a voltage X' signal that differs from the reference signal by the difference in i11a voltage, and transfer the voltage ff:link to the buffer I for each key in the row; for each sensor located in the buffer, reading a voltage difference signal and a respective J1 quasi-signal 2J from the buffer. (23) In the method described at the top of No. (22), further:
The voltage difference for each sensor υ is transferred to the first register of the buffer, the voltage difference for each sensor is transferred to the second register of the buffer, and the voltage difference from the first register is transferred to the second register of the buffer. , serially reading out a voltage difference signal for each sensor from said register, and reading out a reference voltage difference signal for each sensor from said second register in series. A method that combines the process of reading out signals directly. (24) In the method described in item (23), further:
After sensing the first voltage signal from each sensor, the gate of each sensor is pulse-driven to remove the accumulated charge, and the reference signal is transferred to the first register from which the first voltage signal was obtained. and transferring a reference signal for each sensor from the first register to the second register when the sensor is pulsed. (25) In the method described in paragraph (22), a first array bias source is connected to the transistor image sensor in the selected row, and in order to remove the im′i￥f load, The first array bias is used to pulse the gates of the sensors, and the image sensors in each unselected row are connected to a second array to prevent signal interference from unselected rows. A method comprising connecting to an array bias source. (26) In the method described in No. (22) Jr.
The method further includes sensing and storing a voltage difference signal and a reference signal during a horizontal blanking period 1y1, and serially reading out the voltage difference signal during a horizontal readout period following the horizontal blanking period. Method. (27) In the method described in paragraph (22), each row of the image sensor is selectable using an address, adjacent rows have numerically adjacent addresses, and the address C Each row of four sensing sensors is addressed during a respective horizontal blanking period, and further addresses the first row of sensors during the horizontal blanking period;
Reference signal and voltage for each sensor in the row) [fl
sensing and storing the signals, changing said address to a reset address for the second row of image hinges during the same horizontal blanking period, and buffering the signals from each sensor in said second row. Without transferring, the charge accumulated in the center was removed, and the difference between the dark addresses in the first and second rows was subtracted from the number of gold items 1 in the row in the array (
Based on if+, the voltage vI for the sensor of the array
A method comprising the step of determining an integration time. (28) In the method described in paragraph (22), the buffer is read out serially according to a clock, the buffer has a plurality of stages equal to the number of columns, and the rows are irregularly read out by a row decoder. and at least two of the number of rows and columns required for the desired level of TpR imaging.
Double the number of rows and columns of image sensors are provided, typically storing a voltage difference signal for each selected 11 during a respective horizontal blanking period; line f
During each subsequent horizontal readout period, the voltage difference signal of each selected row is read out, the image sensors 1 of every other row are selected in series, and the image sensor 1 of every other row is selected. The first one is such that all the pixels in
A normal image is obtained by clocking the buffer for serial readout at a speed of - Select each successive row of sensors and set the horizontal blanking period in order to avoid reading out pixels connected to columns of sensors that are not in the part subject to the zoom operation in the dark during the next horizontal readout II. Q. Start the register clock operation for serial readout, and after the pixels corresponding to the columns in the part to be enlarged are read out, stop the readout clock and connect to the columns in the part to be enlarged. buffer? slowing down the read clock of the read clock to a speed equal to half the first speed. (29) The method 1c described in item (28) includes the step of performing a panning operation, 1.4. The step of performing the panning operation is to displace the magnified portion by a number of horizontal lines tJ by changing the address code of selected (30) The method includes the step of varying which column of sensors is read by varying the time at which the clock begins to operate, and varying the time at which the readout clock stops. 6
2 and a plurality of sensor elements 6 arranged in rows 64.
Consists of 0. Each element 60 may act to modulate the output voltage signal in response to the charge stored in its gate region 14704 in response to incident light. Intrinsic threshold (J, J,
A circuit 74.84°84.78.72 is provided for determining and storing a signal related to the difference in threshold voltages caused by the threshold voltage. The array 12 is capable of automatic blooming control, electronic aperture, zooming and panning.

[Brief explanation of the drawing]

FIG. 1 is a simplified plan view of the imager array of the present invention, illustrating one possible architectural arrangement. Figure 2 is a small partial schematic diagram of the sensor array shown in Figure 1, Figure 3 is a circuit diagram of one extracted image sensor element and the associated circuitry that processes its signal, and Figure 3a is a schematic diagram of the sensor array shown in Figure 1. Figure 2 is a circuit diagram of another embodiment of the invention, particularly showing a readout circuit comprised of an array of storage capacitors and respective stages of a horizontal scanner; FIG. 4 is a circuit diagram of a portion of the perpendicular i decoder for the array shown in FIG. 1, and FIG.
Circuit diagram of charge amplifier for OD shift register, No. 6
The figure is a time diagram of the operation of the array shown in FIGS. 1, 2, and 3. Explanation of main symbols 14: Contusion 1 24. 26: CCI') Resistance 6o: Sensor element 62: Row 64: Column 68: Source region 70: Gate region 74: Column line 80: Column line bias transistor 84: clamp transistor

Claims (3)

[Claims] (1) It has a plurality of transistor image sensors arranged in at least one row and a plurality of columns, and each transistor sensor has a gate region that accumulates charge in response to light incident thereon. each sensor further has a source region, and a column line for each column is coupled to the source region in that column. , further coupled to a selector operable to address the at least one row, each coupled to a respective column line, the source voltage of a selected sensor within said side due to a changed threshold voltage of said sensor. a plurality of sampling circuits for sampling and storing voltage difference signals proportional to changes in the voltage difference signals; storage means coupled to the column for simultaneously receiving and storing the voltage difference signals from each sampling circuit; and an output for serially outputting each voltage difference signal from the storage means. (2) An apparatus for sensing a voltage difference signal proportional to the number of photons accumulated during a selected integration time, the sensor element having a sensor element that accumulates a charge in response to incident light; the device is operable to have a threshold voltage that changes in response to accumulated charge, the output signal of the device changing as the threshold voltage changes, and further at a first time and when charge is removed from the device. sampling the output signal at a later second time;
An apparatus having a sampling circuit for deriving a change in dark value voltage from a sampled output signal, and a buffer coupled to the sampling circuit for storing a voltage difference signal that varies as a change in the threshold voltage. (3) In a method of sensing a voltage signal proportional to the number of photons accumulated by a sensor element within a preselected integration period, the sensor element accumulates charge in response to light incident on the sensor element and responds to the accumulated charge. changing the threshold voltage of the sensor element, delivering an output signal from the sensor element that changes as the threshold voltage changes, sampling the output signal at a first time, and discharging the accumulated charge from the sensor element after the first time. a step of marking the output signal at a second time after removing the charge, deriving a change in threshold voltage from the marked output signal, and storing a voltage difference signal that changes as a change in the threshold voltage. method including.