JPH01234089A - Brushless motor driving equipment - Google Patents

Abstract

PURPOSE:To simplify the circuitry, by comparing the counter-electromotive force produced from a coil which is controlled of its power supply through a switching transistor with the output frequency of a voltage controlled oscillator with a neutral point voltage, thereafter feeding the counter-electromotive force to the voltage controlled oscillator. CONSTITUTION:Output from a voltage controlled oscillation circuit 40 is frequency divided and transmitted through a power conduction switching circuit 44 comprising a logic circuit 42 and a power amplifier 43 and drive transistors Tr10-15 to drive coils 1-3. Outputs D1-D3 from the frequency division circuit 41 and outputs U1-W2 from the logic circuit 42 are fed to a phase difference detection circuit 28, then pulse timing is selected and a pulse is fed to a comparator 27. Voltages UB-WB obtained by passing the voltages U0-W0 at one terminals of the coils 1-3 through buffers 21-23 are compared 27 with a common joint voltage NB. Output from the comparator 27 is amplified 30 and fed to the voltage controlled oscillator 40, then the oscillation frequency and phase are controlled such that the phase difference will be zero. Consequently, a filter circuit is not required and power conduction timing close to the optimum timing can be achieved with respect to the counter-electromotive force of the drive coil.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a brushless motor drive device without a position detector for detecting the position of a movable element of a motor.

BACKGROUND OF THE INVENTION In recent years, brushless motors have been increasingly used for various drive motors in order to have longer lifespans, higher reliability, and thinner shapes.

Brushless motors generally require a position detector to detect the position of the movable element, and in order to achieve further cost reduction and miniaturization, so-called commutation sensorless brushless motors that do not have a position detector are required. It has become. A conventional example of such a drive device for a brushless motor is disclosed in Japanese Patent Application Laid-open No. 52-80415, for example.

An example of the above-mentioned conventional brushless motor drive device will be described below with reference to the drawings.

FIG. 8 is a circuit diagram of a conventional brushless motor drive device. In FIG. 8, one end of the drive coils 1 to 3 is common, and the other end of the drive coil 1 is connected to the anode of the diode 4, the cathode of the diode 5, and the drive transistor 10.
The other end of the drive coil 2 is connected to the anode of the diode 6, the cathode of the diode 7, and the collectors of the drive transistors 11 and 14, and the other end of the drive coil 3 is connected to the anode of the diode 8. It is connected to the cathode of diode 9 and the collectors of drive transistors 12 and 15. the cathode of the diode 4.6.8 and the drive transistor 10;
．． The emitters of the transistors 11.12 and 11.12 are connected to the positive feed line, and the anodes of the diodes 5.7.9 and the emitters of the drive transistors 13.14.15 are grounded.

The other ends of the drive coils 1 to 3 are each connected to a filter circuit 1.
6, and the output of the filter circuit 16 is input to the energization switching circuit 17. The output of the energization switching circuit 17 is input to the bases of the drive transistors 10 to 15, respectively.

The operation of the conventional brushless motor drive device configured as described above will be described below.

FIG. 9 is an explanatory diagram of the operation in FIG.
, Wo are energization waveforms of the drive coils 1.2.3. The energization waveform U. , Vo, and Wo have harmonic components removed by the filter circuit 16 and their phases are delayed by 90°,
F+, F2. Each is converted to F3. The filter circuit 16 is a first-order filter, and is composed of, for example, an RC passive filter, a negative-order mirror integration circuit, etc., and its cutoff wave number is set to a sufficiently lower frequency than the frequency of the drive coil energization waveform. Outputs F+, F2 . of the filter circuit 16 . F3 is UH,
UL, V)l, VL, WH, WLI:: Logically processed to cause the driving transistors 10 to 15 to perform switching operations. At this time, the switching operation is performed so that motor drive torque is always generated in one direction, and the motor is driven.

Problems to be Solved by the Invention However, in the above configuration, a filter circuit having low cutoff wavenumber characteristics is required for each phase of the drive coil, and therefore a large number of large capacitance capacitors are required.

Furthermore, when the inductance of the drive coil is large, the current flowing through the drive coil is delayed in time after the drive transistor is turned on, and the permanent magnetic field is further demagnetized by the magnetic field generated by the drive coil itself. There is a so-called armature reaction.

In such a case, it is known that if the drive coil is energized at the timing shown in FIG. 9, the efficiency will decrease. The improvement measures are F+, F2. Japanese Patent Laid-Open No. 52-80 discloses a method in which the phase of the F3 signal is slightly advanced and the drive transistor is operated to compensate for the delay in energization due to armature reaction.
Although this is described in Japanese Patent No. 145, additional parts such as capacitors are required to realize this. In addition, the drive coil energization waveform U. , Vo, and Wo are affected by spike noise generated when the drive transistor is turned off, current fluctuations due to power supply voltage fluctuations, load fluctuations, etc., and Uo, v
It is often difficult to accurately obtain an energization switching signal from the energization waveforms of o and Wo using a filter circuit. As a countermeasure to this problem, a method as shown in Japanese Patent Publication No. 59-36519 has been proposed.

However, the method of obtaining the energization switching signal from the drive coil energization waveform using a filter circuit basically has the following problems. In other words, the voltage drop caused by the current flowing through the drive coil and the internal impedance of the drive coil, as well as the spike noise that occurs immediately after energization is stopped, are superimposed on the fundamental wave (back electromotive force) of the drive coil energization waveform, and these It constantly fluctuates along with fluctuations in power supply voltage and load. Therefore, when filtering the drive coil energization waveform to obtain the energization switching signal, errors occur due to the above components that are constantly fluctuating and superimposed on the fundamental wave (back electromotive force) of the energization waveform, resulting in accurate drive coil energization. becomes difficult.

To solve these problems, various methods have been proposed to accurately obtain the energization switching signal, but basically the phase difference between the back electromotive force generated in the drive coil and the energization switching signal is kept constant. Therefore, the adjustment is performed around the filter circuit, and the adjustment is extremely troublesome. In addition, a large number of capacitors are required in addition to those used to configure the filter circuit.
Therefore, when using IC, the number of external parts and the number of bottles increase, resulting in an expensive product. In addition, a method for obtaining the energization switching signal digitally using a microcomputer, etc. without using a filter circuit was published in Japanese Patent Application Laid-Open No. 61-29319.
Although it is described in Publication No. 1, it is still expensive.

As mentioned above, the conventional brushless motor drive device is
From the drive coil energization waveform, a filter circuit obtains an energization switching signal that has a certain phase relationship with the position of the mover, and this is used to sequentially energize the drive coils, so the drive coil energization waveform It is difficult to obtain an accurate energization switching signal due to spike noise contained in the energization, voltage drop in the drive coil due to the energized current, fluctuations in these superimposed components due to fluctuations in the power supply voltage and load, and influences such as armature reaction. Further, a large number of large capacitance capacitors are required when constructing a filter circuit, and especially when integrated into an IC, the number of external parts and the number of bins increases, which is disadvantageous in terms of cost.

Therefore, as shown in Japanese Patent Publication No. 61-3193, the waveform of the back electromotive force generated in the drive coil is shaped, and P
A method has been proposed in which a proper phase pulse is generated using an LL circuit, and the drive coils are sequentially energized to drive the motor. That is, with the configuration shown in Fig. 10, the back electromotive voltages A, B, and C generated in the drive coils are pulse-shaped and arithmetic processed to obtain a pulse signal G. Comparing the phases of the frequency generator output I and the pulse signal G, and feeding the comparison output to the voltage controlled oscillator to synchronize the phases of the signals I and G;
A method is shown in which the frequency of the signal I is divided to generate an energization signal for a drive coil to drive a motor. FIG. 11 shows the signals of each part of this system. However, in this type of system, the back electromotive force generated in the drive coil includes the voltage drop caused by the current flowing when the drive coil is energized and the internal impedance of the drive coil, and the spike that occurs immediately after the energization is stopped. Noise etc. are superimposed, and therefore it is extremely difficult to obtain a pulse signal by waveform shaping and arithmetic processing of the back electromotive voltage generated in the drive coil. actual,
In the configuration shown in FIG. 10, it is not possible to obtain the pulse signal G as shown in FIG. 11, and the influence of spike noise that occurs immediately after energization of the drive coil always occurs. Therefore, phase comparison with the frequency divider output I becomes impossible, and phase synchronization of both signals I and G becomes impossible. Therefore, the special public official 1986-
In the method disclosed in Japanese Patent No. 3193, the back electromotive force of the drive coil is simply pulse-shaped and arithmetic processed, which causes the above-mentioned problems and makes it impossible to implement.

As described above, conventional brushless motor drive devices have had various problems.

In view of the above-mentioned problems, the present invention eliminates a large number of large capacitance capacitors that were required in the conventional filter circuit configuration by obtaining a drive coil energization switching signal without using a filter circuit, and at the same time, the drive coil energization waveform is To provide a new brushless motor drive device that can sequentially energize and drive drive coils without being affected by spike noise contained in the motor, power supply voltage fluctuations, load fluctuations, or armature reactions. It is.

Means for Solving the Problems In order to solve the above problems, a brushless motor drive device of the present invention includes a multi-phase motor drive coil, a plurality of drive transistors provided in the drive coil, a voltage controlled oscillator, an energization switching circuit that forms an energization switching signal for the drive coil based on a frequency signal corresponding to an oscillation frequency of the voltage controlled oscillator; and a energization switching circuit that has a predetermined phase relationship with the energization switching signal during a non-energization period of the drive coil. A comparator that generates a phase difference detection pulse at a timing selected by a pulse timing selection means, and compares the back electromotive force generated in the drive coil during the phase difference detection pulse generation period with the neutral point voltage of the drive coil. has
a phase error detector that equivalently detects the phase difference between the back electromotive voltage and the energization switching signal at the output of the comparator; and an error amplifier that amplifies the output of the phase error detector; The output is input to the voltage controlled oscillator.

Operation The present invention uses the above-described configuration to detect the phase difference between the back electromotive force generated in the motor drive coil and the energization switching signal of the same coil, and to control the frequency and phase of the energization switching signal according to the detected phase difference. Since a feedback loop or phase control loop (PLL loop) is configured so that the energization switching signal maintains a constant phase relationship with respect to the position of the movable element, the filter circuit that was previously required is no longer required. All of the various problems that occurred due to this will be resolved.

In addition, since the phase difference between the back electromotive force generated in the motor drive coil and the energization switching signal of the same coil is detected during the energization-off period, accurate phase difference detection is possible and stable operation of the above-mentioned phase control loop is possible. Kinaru.

EXAMPLE Hereinafter, a brushless motor drive device according to an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a brushless motor drive device according to an embodiment of the present invention. In FIG. 1, parts having the same functions as those of the conventional brushless motor drive device shown in FIG. 8 are given the same symbols, and their explanations will be omitted. In FIG. 1, the bases of drive transistors 10 to 15 are respectively connected to the outputs of power amplifiers 43, and the inputs of power amplifiers 43 are connected to the outputs of logic circuits . Here, the logic circuit 42 and the power amplifier 43 constitute an energization switching circuit 44. The input of the logic circuit 42 is connected to the output Dr of the frequency dividing circuit 41.
The input of 1 is connected to the output of voltage controlled oscillator 40. Further, a minimum frequency setting circuit 50 is connected to the voltage controlled oscillator 40. Output D1 of the frequency dividing circuit 41
rD2+D3 and the output 'U+'+ of the logic circuit 42
U2. Vt.

V2. W, , W2 are input to the phase difference detection pulse generation circuit 28 and are connected to one end U of the drive coil 1.2.3. .

Vo and Wo are input to buffer circuits 21, 22, and 23. The outputs UB, VB, WB of the buffer circuits 21, 22, 23 are input to a comparator 27 and are commonly connected via resistors 24, 25, 26, and this common connection point NB is input to the comparator 27. has been done. The output PD of the comparator 27 is controlled by the output of the phase difference detection pulse generation circuit 28. The generation timing of the phase difference detection pulse from the phase difference detection pulse generation circuit 28 is set by a pulse timing selection means 29. Here, each of the components 21 to 29 constitutes a phase error detector 20,
The output PD is the output of the phase error detector 20. The output PD of the phase error detector 20 is connected to the inverting input terminal of an operational amplifier 31 via a resistor 32, and a series circuit of a resistor 33 and a capacitor 34 is connected between the inverting input terminal and the output terminal of the operational amplifier 31. and a capacitor 35 are inserted. A constant bias voltage is applied to the non-inverting input terminal of the operational amplifier 31 by resistors 36 and 37. Here, the components 31 to 37 constitute an error amplifier 30, and the output EAO of the error amplifier 30 is connected to the input of the voltage controlled oscillator 40.

The operation of the brushless motor drive device configured as described above will be described below.

FIG. 2 is a detailed explanatory diagram of the present invention, showing the phase relationship between the drive coil back electromotive force and the drive coil energization waveform. FIG. 2(a) shows a case where the phase relationship between the back electromotive force (broken line part) and the energization waveform (solid line part) is in an optimal state,
Figures (b) and (c) show the case where the phase angle ψ deviates from the optimum state. Here, in FIG. 1, the output of the voltage controlled oscillator 40 is output from the frequency dividing circuit 412 to the energization switching circuit
．． Drive coils 1 to 1 through drive transistors 10 to 15
3 has been transmitted. Therefore, a certain phase relationship exists between the output of the voltage controlled oscillator 40 and the energization waveforms of the drive coils 1 to 3. That is, by controlling the oscillation frequency and phase of the voltage controlled oscillator 40, it is possible to control the phase difference between the drive coil back electromotive voltage and the drive coil energization waveform. Therefore, as shown in Fig. 2 (b) and (C), if a phase angle ψ deviation occurs between the drive coil back electromotive force and the drive coil energization waveform, the phase error ψ can be detected by phase error detection. By providing a phase control loop that detects and amplifies the voltage controlled oscillator 4o using the oscillator 20 and the error amplifier 30 and controls the oscillation frequency and phase of the voltage controlled oscillator 4o so that ψ becomes zero, the optimum energization state as shown in FIG. 2(a) is achieved. It becomes possible to secure the following. Therefore, it is possible to always generate motor drive torque stably and efficiently, and the motor is driven.

Here, a specific example of the configuration of the phase error detector 20 will be described in detail.

First, a concrete configuration of the phase difference detection pulse generation circuit 28 and the pulse timing selection means in the phase error detector 20 may be as shown in FIG. 3, for example. In FIG. 3, parts having the same functions as those in FIG. 1 are given the same symbols. The outputs of the logic circuit 42 UIIU21Vl, V2. WI, W2 and the output D1 of the frequency divider circuit 41. D2. D3 is applied as an input signal to this phase difference detection pulse generation circuit. Here, 29 is a pulse timing generating means for selecting and setting the timing at which the phase difference detection pulse is generated. A High, Middle, or Low signal is input to the input terminal PT, and the terminal Y corresponds to each input signal. ,Yl
, Y2 is determined. Depending on the combination, one of the switches Zo, Z+, or Z2 of the switch blocks 291 to 296 is turned on, and the remaining two are turned off. Now, here, the switch blocks 291 to 296
At Switch Z! We will proceed with the description of the case where the switch is ON1 and the remaining switches Zo and Z2 are OFF. FIG. 4 shows the switch Z1 in FIG.
4 is an explanatory diagram of the operation of the phase difference detection pulse generation circuit when is ON, and each waveform in FIG. 4 corresponds to the signal at the point indicated by the symbol in FIG. 3. FIG. Output terminals So, S+, S2 . S3, S
A signal waveform with the same symbol in FIG. 4 is output from 4°Ss and Ss.

Next, as a concrete configuration of the phase error detector 2o including the phase difference detection pulse generation circuit 28 and the pulse timing selection means 29, for example, the one shown in FIG. 5 can be considered. In FIG. 5, parts having the same functions as those in FIG. 1 are given the same symbols. That is, drive coil 1,
2.3 one ends Uo, Vo, Wo are input to the buffer circuits 21, 22, and 23, respectively, and the buffer circuits 2
1°22.23 output U8. VB, Ws haso tvE
'in resistors 24, 25, 26, and the common connection point NB is the comparator circuit 1-00.120, 140.
and the non-inverting input terminals of the comparison circuits 110, 130, and 150. The buffer circuit 21
The output UB of the buffer circuit 22 is connected to the non-inverting input terminal of the comparison circuit 100 and the inverting input terminal of the comparison circuit 110, and the output VB of the buffer circuit 22 is connected to the non-inverting input terminal of the comparison circuit 120 and the inverting input terminal of the comparison circuit 130. The output We of the buffer circuit 23 is connected to the input terminal of the comparison circuit 1.
40 and an inverting input terminal of the comparison circuit 150. The comparison circuit 100°110.
120, 130, 140.150 are oven collector outputs from the respective output transistors 101, 111, 121, 131゜141.151, and the transistor 10
1,111.12i.

The collectors of transistors 131, 141, and 151 are commonly connected to the collector of transistor 161, forming a phase error detector output PD. The base of the transistor 161 is connected to the base and collector of a transistor 162, the collector of a transistor 164, and the collector of a transistor 169 that operates as a constant current source. The emitter of the transistor 162 is a resistor 163
A stabilized power supply voltage Vreg is applied through the transistors 161 and 164, and the stabilized power supply voltage Vreg is applied to the emitters of the transistors 161 and 164. the transistor 164
The base of the transistor 167 is connected to the emitter via a resistor 166, and is also connected via a resistor 165 to the collector of a transistor 167 whose emitter is grounded. The base of the transistor 167 is connected to the output S of the phase difference detection pulse generation circuit 28 via a diode 168. is connected.

Other output S1°S of the phase difference detection pulse generation circuit 28
2. S3. S4. S5 and S6 each have a resistor of 171.
Transistors 170°172.174.173, 175.177.179.181 have their emitters grounded.
176, 178, 180, and the transistors 170, 172, 174, 176, 178, .
180 collectors each have a pre-engineered transistor 10
It is connected to each base of 1,111°, 121, 131, 141, and 151. The phase difference detection pulse generation circuit 2
Each input terminal of 8 is each output Us of the energization switching circuit 44.

U2. V+, V2. Wt, W2 and the outputs DI of the U frequency division DO path 41, D2. D3 is connected.

The operation of the phase error detector configured as above will be described below.

FIG. 6 is an explanatory diagram of the operation, and shows how the phase error between the back electromotive voltage and the energization waveform is detected with respect to the drive coil 1. In FIG. 6, the drive coil 1 receives signals U+, U2 . (that is, U)l, UL) is energized as a energization command signal. Therefore, a period in which neither Ul nor U2 is output is a energization suspension period, during which the drive coil energization waveform Uo coincides with the back electromotive force U. From Figure 6, the energization suspension period begins when Ul goes low and then U2
This period corresponds to one clock of Dl or four clocks of D3. Similarly, there is a energization suspension period in the period from when U2 becomes Low until when Ul becomes High, but to simplify the explanation, only the former period will be considered.

During the power-off period, the neutral point voltage N of each drive coil.

Comparing the drive coil energization waveform Uo, when the phase difference ψ between Uo and the drive coil back electromotive force TJe is zero, No and Uo
The intersection point coincides with the center of the energization suspension period, that is, two clocks after D3 after Ul becomes Low. Uo or U again
No and U if delayed by phase difference ψ with respect to e. is Ul
It matches two clocks after D3 after D3 goes LOW, and U.

If Ue advances by a phase difference ψ, No and Uo coincide two clocks after D3 after Ul becomes Low. Therefore, U occurs two clocks after D3 after Ul goes low. and N. By comparing Uo
It is possible to know the phase relationship between and Ue. Therefore, the phase difference ψ
As a method of detecting D3 after Ul becomes Low.
The phase difference detection pulse signals S2 and S have an appropriate width based on two clocks later. , S2 and S.

No and U only when it occurs. By comparing , it is possible to obtain a comparator output PD having a duty according to the phase difference ψ. In Figure 6, Ul is Low for S2 and So.
This shows a case where Uo lags behind TJe by a phase angle ψ, which occurs for a period of two clocks of D3 after 2 clocks of D3.

As described above, with respect to the energization waveform Uo of the drive coil 1, Ul is L
We have explained the operating principle of detecting the phase difference ψ using the energization suspension period from when Uo becomes low until U2 becomes High. and the period from when Ul becomes High, and the energization waveforms Vo of the other drive coils 2 and 3.
,W.

can also be detected in the same way, and in this embodiment, the phase error detector output PD is obtained by combining all of them.

As described above, in FIG. 3, the switch Z1 of the pulse timing selection means 29 is ON; and Z2 is OF
Although the case of F has been described, the operation of the pulse timing selection means 29 will now be described.

High, MidIe, and L input to input terminal PT
The ow signals are represented by H, M, and L, respectively, and the signals of terminals p, q, and terminals Yo, Yl, and Y2 are expressed as Hjgh and Low.
are represented by H and L, the signals at each of the terminals and the switch Z correspond to the signal at the input terminal PT. , Zs, and Z2 are as shown in the table below, where the previous switch Z. ,Zl
, Z2 are the terminals Y, respectively. , Y+, and Y2 are operated in such a manner that they are ○N when they are High, and OFF when they are Low.

Now, the operation of the pulse timing selection means 29 will be explained.

In the circuit diagram of the brushless motor drive device according to the embodiment of the present invention shown in FIG. 1, it is assumed that the bias of the non-inverting input terminal of the error amplifier 30 is set to vreg/2. When the output of the error amplifier 30 is not saturated and the phase control loop is operating stably, the inverting input terminal of the error amplifier 30 is in an imaginary short with the non-inverting input terminal, so that Vreg/ It becomes 2. The output PD of the phase error detector shown in FIG.
31.141,151. If you ignore the emitter-collector saturation voltage of 161, the high level will be Vreg.
, a waveform that operates when the low level is zero, that is, a waveform like PD in FIG. Now, when the phase control loop is operating stably, the PD waveform in the figure has an average voltage of Vreg/2, that is, a high level of 50% and a low level of 50%.
The pulse waveform is controlled to have a duty ratio of level 50%. By the way, during the power outage period,
Neutral point voltage No. of each drive coil and drive coil energization waveform U
. Comparing, when the phase difference ψ between Uo and drive coil back electromotive force Ue is zero, No and U. The intersection of the two coincides with the center of the energization suspension period, that is, two clocks after D3 after Ul becomes Low, so the phase difference detection pulses S2 and So are
D based on 2 clocks after D3 after l becomes Low
3 car clock period, and during that period U
.

If the duty of the PD is determined based on the magnitude relationship by comparing and No, the duty will be High.
The h level becomes 50% and the low level becomes 50%, and the phase control loop becomes stable. That is, Ue and U. Stable operation of the phase control loop is possible when the phase difference ψ is zero.

By the way, the above explanation is based on N during the energization suspension period. and U. This is based on the assumption that the intersection of Assume that the intersection of N and Uo is shifted from the center of the same period as a result of distortion. At this time, similarly to the above case, the phase difference detection pulses S2 and So are generated for a period of -clocks of D3 with the reference timing being two clocks after D3 after U+fJ<Low, and U during that period. and N
. When comparing, the duty of the PD waveform deviates from the state of High level 50% and Low level 50%, so
Feedback is applied to the input of the voltage/til control oscillator 40 via the error amplifier 30 to compensate for the deviation.

As a result, the duty of the PD waveform is 50% at the high level and 50% at the low level with a phase difference between Ue and Uo corresponding to the above-mentioned deviation, and the phase control loop becomes stable. In other words, the timing of energization switching of the drive coil deviates from the optimum efficiency point with respect to the back electromotive force of the drive coil. In order to improve this phenomenon, the present invention uses a phase difference detection pulse S!
~S6 and S.

The generation timing of the pulse can be set by a pulse timing selection means. That is, in one embodiment of the present invention shown in FIG.
Depending on the signal state of the input terminal PT of 9, the switches Zo and Z
s, Z2 can be selected as shown above. When the switch Zl is ON, phase difference detection pulses S2 and S are generated in FIG. 4 as in the same figure. U, becomes Low.

The reference timing is two clocks after the D3±-clock period. In addition, the switch Zo is ON.
In the case of , the phase difference detection pulse S
2 and S. After Ul becomes Low, D3's 1+-
The second clock period of D3 is generated using the period after the clock as a reference timing. Furthermore, when the switch Z2 is ON, the phase difference detection pulse S2 is different from that shown in FIG.
and S. is generated for the ±- clock period of D3 with reference timing being 2+- clocks after D3 after Ul becomes Low. 82. to simplify the explanation. So
We have talked about S+, S3, S4, Ss
, SS also generate phase difference detection pulses at the same timing as S2 and So, respectively.

Therefore, as mentioned above, if the energization timing of the drive coil deviates from the optimum efficiency point with respect to the back electromotive force of the drive coil, the timing of pulse generation can be selected and set by the pulse timing selection means. Thus, it is possible to relatively compensate for the deviation and improve the energization timing of the drive coil with respect to the back electromotive force of the drive coil so as to approach the optimum efficiency point.

Now, FIG. 7 shows the operating waveforms of each part when the configuration shown in FIG. 5 is used as the phase error detector 20 in FIG. This figure shows how the oscillation frequency f of the voltage controlled oscillator is controlled so that f becomes zero. Note that the lowest frequency setting circuit 50 in FIG. 1 sets the oscillation frequency of the voltage controlled oscillator 40 to the lowest frequency when starting the motor, and generates a rotating magnetic field at a speed that the movable element (rotor) can sufficiently follow. This is to ensure that the motor starts.

As described above, according to this embodiment, the motor drive coil is always energized based on the output of the voltage controlled oscillator, and the phase difference between the energization waveform and the back electromotive force of the drive coil is detected by the phase error detector. By providing a so-called phase control loop (PLL loop) in which the excavation frequency and phase of the voltage controlled oscillator are controlled by the amplified signal so that the phase error becomes zero, the motor is efficiently driven without the influence of armature reaction. Furthermore, the conventional filter circuit is not required, and the number of large-capacity capacitors can be significantly reduced. In addition, the phase error detector generates a phase difference detection pulse during the period when the drive coil is not energized, and compares the back electromotive force generated in the drive coil with the neutral point voltage during the detection pulse generation period, thereby isometrically detecting the Since the phase error output of the back electromotive voltage and the energization switching signal is obtained, by setting the detection pulse generation timing to avoid the spike noise generation period that occurs immediately after the drive coil energization is stopped, it is possible to avoid the influence of the spike noise. In addition, since phase error detection is performed during the energization stop period, there is no effect from voltage drops or fluctuations in the energization current and drive coil impedance that occur during the energization period. Furthermore, the width of the phase error detection pulse generated during the power-off period is constant with respect to the electrical angle or mechanical angle of the motor, and the width of the comparison output between the back electromotive force and the neutral point voltage during the phase difference detection pulse generation period is Since it depends only on the duty, the phase error detection gain does not change due to the influence of the motor rotation speed, and the phase control loop can always operate stably.

Effects of the Invention As described above, the present invention includes a multi-phase motor drive coil,
a plurality of drive transistors connected to the drive coil; a voltage-controlled oscillator; an energization switching circuit that forms an energization switching signal for the drive coil based on a frequency signal corresponding to an oscillation frequency of the voltage-controlled oscillator; During the energization suspension period of the coil, a phase difference detection pulse having a predetermined phase relationship with the energization switching signal is generated at a timing selected by the pulse timing selection means, and is generated in the drive coil during the phase difference detection pulse generation period. a phase error detector that includes a comparator that compares the back electromotive voltage and the neutral point voltage of the drive coil, and that isometrically detects the phase difference between the back electromotive voltage and the energization switching signal using the comparison output; and,
The configuration includes an error amplifier that amplifies the output of the phase error detector, and inputs the output of the error amplifier to the voltage controlled oscillator, thereby eliminating the need for a conventionally required filter circuit, and thus eliminating the need for a large-capacity capacitor. It also eliminates problems such as spike noise included in the drive coil energization waveform, voltage drop due to the energization current and drive coil impedance, fluctuations in these due to fluctuations in power supply voltage and load, and reduced efficiency due to armature reaction. It is possible to realize an extremely superior brushless motor drive device without any problems.

Furthermore, since the generation timing of the phase difference detection pulse can be set by the pulse timing selection means, an excellent effect is achieved in that the energization timing of the drive coil can be brought closer to the optimum efficiency point with respect to the back electromotive force of the drive coil. have

Although the embodiments of the present invention have been described using a three-phase full-wave drive system, other drive systems such as a two-phase full-wave drive system, a two-phase half-wave drive system, a three-phase half-wave drive system, etc. It is also possible to realize a brushless motor drive device using the same method as the present invention.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a brushless motor drive device according to an embodiment of the present invention, FIG. 2 is a diagram explaining the operating principle of FIG. 1, and FIG. 3 is a concrete diagram of a phase difference detection pulse generation circuit and pulse timing selection means. 4 is a diagram explaining the operation of FIG. 3, FIG. 5 is a detailed circuit diagram of the phase error detector, FIG. 6 is a diagram explaining the operation of FIG. 5, and FIG. 7 is a diagram explaining the operation of the present invention. FIG. 8 is a circuit configuration diagram of a conventional brushless motor drive device, FIG. 9 is an operation explanatory diagram of FIG. 8, and FIG. 10 is another conventional brushless motor drive device. FIG. 11 is an explanatory diagram of the operation of FIG. 10. 1-3... Drive coil, 10-15...
- Drive transistor, 20...1... Phase error detector, 28... Phase difference detection pulse generation circuit, 29...
...Pulse timing selection means, 30...
・Error amplifier, 40... Voltage controlled oscillator, 44
...... Energization switching circuit. Name of agent: Patent attorney Toshio Nakao and one other person Figure 6
. Figure 7 Ma Sa call L Figure 11 G; : ○

Claims (1)

[Claims] a multi-phase motor drive coil, a plurality of drive transistors connected to the drive coil, a voltage controlled oscillator,
an energization switching circuit that forms an energization switching signal for the drive coil based on a frequency signal corresponding to an oscillation frequency of the voltage controlled oscillator; and a energization switching circuit that has a predetermined phase relationship with the energization switching signal during a non-energization period of the drive coil. A comparator that generates a phase difference detection pulse at a timing selected by a pulse timing selection means, and compares the back electromotive force generated in the drive coil during the phase difference detection pulse generation period with the neutral point voltage of the drive coil. and a phase error detector that equivalently detects the phase difference between the back electromotive force and the energization switching signal at the output of the comparator, and an error amplifier that amplifies the output of the phase error detector, A brushless motor drive device comprising inputting the output of the error amplifier to the voltage controlled oscillator.