JP2643252B2 - Drive device for brushless motor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a brushless motor driving device without a position detector for detecting the position of a motor mover.

2. Description of the Related Art In recent years, brushless motors have often been used for various driving motors in order to extend their life, increase reliability, or reduce the shape of the motor. In general, a brushless motor requires a position detector that detects the position of the mover, and a so-called commutation sensorless brushless motor without a position detector is required in order to further reduce costs and reduce size. It has become. As a conventional example of such a brushless motor driving device, for example,
There is one as disclosed in Japanese Patent Application Laid-Open No. 52-80415.

Hereinafter, an example of the above-described conventional brushless motor driving device will be described with reference to the drawings.

FIG. 8 is a circuit diagram of a conventional brushless motor driving device. In FIG. 8, one end of the drive coils 1 to 3 is common, and the other end of the drive coil 1 is connected to the anode of the diode 4, the cathode of the diode 5, and the drive transistor 10.
The other end of the driving coil 2 is connected to the anode of the diode 6, the cathode of the diode 7, and the collectors of the driving transistors 11 and 14,
The other end of the driving coil 3 is connected to the anode of the diode 8, the cathode of the diode 9, and the collectors of the driving transistors 12 and 15. The cathodes of the diodes 4, 6, 8 and the emitters of the driving transistors 10, 11, 12 are connected to a positive power supply line, and the anodes of the diodes 5, 7, 9 and the emitters of the driving transistors 13, 14, 15 are connected to each other. Grounded. The other ends of the drive coils 1 to 3 are input to a filter circuit 16, and the output of the filter circuit 16 is input to a conduction switching circuit 17. The output of the current switching circuit 17 is input to the bases of the drive transistors 10 to 15, respectively.

The operation of the conventional brushless motor driving device configured as described above will be described below.

FIG. 9 is an explanatory diagram of the operation in FIG. 8, and U ₀ , V ₀ , W ₀
Is the waveform of the current flowing through the drive coils 1, 2, and 3. The conduction waveform U ₀ ,
V ₀ and W ₀ are converted into F ₁ , F ₂ , and F ₃ , respectively, with the harmonic components removed by the filter circuit 16 and the phase delayed by 90 °. Note that the filter circuit 16 is a primary filter, and is composed of, for example, an RC passive filter, a primary mirror integration circuit, and the like, and its cutoff frequency is set sufficiently lower than the frequency of the drive coil conduction waveform. The filter circuit
The outputs F ₁ , F ₂ , and F ₃ of 16 are supplied to the U _H , U _L , V _H , V
_L , W _H , and W _L are logically processed, and the driving transistors 10 to 15 are processed.
Is switched. At this time, the switching operation is performed so that the motor driving torque is always generated in one direction, and the motor is driven.

However, in the above-described configuration, a filter circuit having a low cutoff frequency characteristic is required for each phase of the drive coil, and thus a large number of large-capacity capacitors are required.

When the inductance of the drive coil is large, the current supplied to the drive coil is delayed with time after the drive transistor is turned on, and the permanent magnetic field is demagnetized by the magnetic field generated by the drive coil itself. There is a so-called armature reaction.

In such a case, it is known that when the drive coil is energized at the timing shown in FIG. 8, the efficiency is reduced.
Its slightly Advances the phase of F _1, F _2, F ₃ of the signal as a remedy,
Japanese Patent Laid-Open Publication No. Sho 52-80415 discloses a method of operating a drive transistor so as to compensate for a delay in energization due to an armature reaction. However, in order to realize this, components such as a capacitor are further required. The drive coil conduction waveforms U ₀ , V ₀ , W ₀ include spike noise generated when the drive transistor is turned off, power supply voltage fluctuations, current fluctuations due to load fluctuations, and the like, and U ₀ , V ₀ , W ₀ It is often difficult to accurately obtain an energization switching signal using a filter circuit from the energization waveform. As a countermeasure, a system as disclosed in JP-B-59-36519 has been proposed.

However, the method of obtaining an energization switching signal from a drive coil energization waveform using a filter circuit basically has the following problems. That is, the current drop when the drive coil is energized, the voltage drop generated by the internal impedance of the drive coil, and the spike noise generated immediately after the current is stopped are superimposed on the fundamental wave (back electromotive voltage) of the drive coil current waveform. It fluctuates constantly with fluctuations in power supply voltage and load. Therefore, when the energization switching signal is obtained by filtering the energization waveform of the drive coil, an error occurs due to the above-described component that is constantly fluctuating and superimposed on the fundamental wave (back electromotive force) of the energization waveform, and the energization of the drive coil is accurate. Becomes difficult.

In order to solve the above problems, various methods for accurately obtaining the energization switching signal have been conventionally proposed. However, basically, the phase difference between the drive coil back electromotive voltage and the energization switching signal is kept constant. The adjustment is performed around the filter circuit, and the adjustment is extremely troublesome. In addition, a large number of capacitors are required in addition to the filter circuit configuration. Therefore, the number of external parts and the number of pins are increased in the case of an IC, which is expensive. A method of digitally obtaining an energization switching signal using a microcomputer or the like without using a filter circuit is described in Japanese Patent Application Laid-Open No. 61-293191, but it is still expensive.

As described above, the conventional brushless motor driving device obtains an energization switching signal having a fixed phase relationship with respect to the position of the mover by a filter circuit from the energization waveform of the driving coil, and utilizes the driving coil to drive the driving coil by using the signal. Since it is configured to energize sequentially, voltage drop of the drive coil due to spike noise and energizing current included in the energizing waveform of the driving coil,
It is difficult to obtain an accurate energization switching signal due to fluctuations of these superimposed components due to fluctuations in the power supply voltage and load, and further to the effects of armature reaction and the like. In addition, a large number of large-capacity capacitors are required when configuring a filter circuit.
In such a case, the number of external parts and the number of pins increase, which is disadvantageous in terms of price.

Therefore, as shown in JP-B-61-3193, the back electromotive voltage generated in the drive coil is shaped and the PLL is adjusted.
There has been proposed a method of generating an appropriate phase pulse using a circuit, sequentially energizing a drive coil, and driving a motor.
That is, with the configuration as shown in FIG. 10, the back electromotive voltages A, B, and C generated in the drive coil are pulse-shaped and arithmetically processed to obtain a pulse signal G, which is provided at the output of the voltage-controlled oscillator. The phase of the pulse output G is compared with that of the frequency divider output I, and the comparison output is fed back to the voltage-controlled oscillator to synchronize the phases of the signals I and G. A method of generating a signal and driving a motor is shown. FIG. 11 shows the appearance of signals at various parts in this system. However, in such a method, as described above, the back electromotive force generated in the drive coil includes a voltage drop caused by the current flowing when the drive coil is energized and the internal impedance of the drive coil, and a spike generated immediately after the energization is stopped. Since noise and the like are superimposed, it is extremely difficult to obtain a pulse signal by performing waveform shaping and arithmetic processing on the back electromotive voltage generated in the drive coil. In fact, in the configuration shown in FIG. 10, the pulse signal G as shown in FIG. 11 cannot be obtained, and the influence of spike noise generated immediately after the drive coil is energized always occurs. Therefore, the phase comparison with the frequency divider output I becomes impossible, and the phase synchronization of the two signals I and G becomes impossible. Therefore, in the method disclosed in Japanese Patent Publication No. 61-3193, the back electromotive force of the drive coil is simply subjected to pulse shaping and arithmetic processing.

As described above, the conventional brushless motor driving device has various problems.

In view of the above problems, the present invention eliminates a large number of capacitors required in the conventional filter circuit configuration by obtaining a drive coil conduction switching signal without using a filter circuit, and simultaneously includes the drive coil conduction waveform in a drive coil conduction waveform. It is an object of the present invention to provide a novel brushless motor drive device capable of sequentially energizing and driving a drive coil without being affected by spike noise, power supply voltage fluctuation, load fluctuation and armature reaction.

Means for Solving the Problems In order to solve the above problems, a brushless motor driving device according to the present invention includes a motor driving coil having a plurality of phases, a plurality of driving transistors connected to the driving coil, and energization of the driving coil. An energization switching circuit for sequentially transmitting a switching signal to the driving transistor; a voltage controlled oscillator for inputting a signal having an appropriate frequency to the energization switching circuit; A phase error detector that detects a phase difference between the electromotive voltage and the energization switching signal of the drive coil, an error amplifier that amplifies an output of the phase error detector and inputs the voltage-controlled oscillator, and an output of the error amplifier. An error amplifier output clamping circuit that clamps at an appropriate level, and the error amplifier outputs when the output of the error amplifier reaches the limit of the effective operating range. The output of the difference amplifier is started, and when the output of the error amplifier is clamped by the error amplifier output clamp circuit, the reset circuit terminates the initialization of the output of the error amplifier.

According to the present invention, the synchronous motor starts operating at a frequency corresponding to the lowest oscillating frequency of the voltage-controlled oscillator according to the above-described configuration. The phase difference is detected, the frequency and phase of the energization switching signal are controlled in accordance with the detected phase difference, and a feedback loop or a phase control loop (PLL) is provided so that the energization switching signal maintains a constant phase relationship with the position of the mover.
(L loop), the filter circuit conventionally required becomes unnecessary, and thus all the various problems caused by having the filter circuit can be eliminated.

In addition, since the phase difference between the back electromotive voltage generated in the motor drive coil and the energization switching signal of the coil is detected during the energization suspension period, accurate phase difference detection is possible, and the above-described phase control loop can operate stably. Becomes

Further, by providing a reset circuit for initializing the output of the error amplifier, the output of the error amplifier is clamped at a level at which the error amplifier output clamp circuit operates when power is turned on or when the phase control loop is out of synchronization. By doing so, the oscillation frequency of the voltage-controlled oscillator is started to rise from a low frequency, so that the phase control loop can be reliably locked in phase.

Embodiment A brushless motor driving device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram of a brushless motor driving device according to an embodiment of the present invention. In FIG. 1, portions having the same functions as those of the conventional brushless motor driving device of FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 1, the bases of the driving transistors 10 to 15 are connected to the output of a power amplifier 43, respectively, and the input of the power amplifier 43 is connected to the output of a logic circuit 42. Here, the logic circuit 42 and the power amplifier 43 constitute a conduction switching circuit 44. Said input of the logic circuit 42 is connected to the output D ₁ of the frequency divider 41, the input of the frequency divider 41 is connected to the output of the voltage controlled oscillator 40. The other output D ₂ of the divider 41 outputs _{U 1, U 2, V 1} , V 2, W 1, W 2 of the logic circuit 42 is input to the phase difference detecting pulse generating circuit 28, the driving coil 1 , 2,3
One end U ₀ , V ₀ , W ₀ is input to buffer circuits 21, 22, 23. Each output U _B of the buffer circuit 21, 22, 23, V _B, W _B are commonly connected through a resistor 24, 25 is inputted to the comparator 27, the common connection point N _B is the comparison Input to the container 27. The output PD of the comparator 27 is controlled by the output of the phase difference detection pulse generation circuit 28. Where each of the components
21 to 28 constitute a phase error detector 20, and the output PD is an output of the phase error detector 20. An output PD of the phase error detector 20 is connected to an inverting input terminal of an operational amplifier 31 via a resistor 32, and a series circuit of a resistor 33 and a capacitor 34 is provided between the inverting input terminal of the operational amplifier 31 and the output terminal. And the capacitor 35 are inserted. A constant bias voltage is applied to the non-inverting input terminal of the operational amplifier 31 by resistors 36 and 37. Here, by each of the components 31 to 37,
An error amplifier 30 is configured, and an output EAO of the error amplifier 30 is connected to an input of the voltage controlled oscillator 40.

Further, a lowest frequency setting circuit 50 is connected to the voltage controlled oscillator 40, and an error amplifier output clamp circuit 53 is connected to the error amplifier 30.

The inverting input terminal of the operational amplifier 31 and the output of the error amplifier output clamp circuit 53 are input to a reset circuit 60, and the output of the reset circuit 60 controls the output PD of the comparator 27. ing.

The operation of the brushless motor driving device configured as described above will be described below.

FIG. 2 is an explanatory view of the operation principle of the present invention, and shows the phase relationship between the drive coil back electromotive voltage and the drive coil conduction waveform. FIG. 2A shows a case where the phase relationship between the back electromotive voltage (broken line) and the conduction waveform (solid line) is in an optimum state, and FIGS. The case where the state deviates from the state is shown. In FIG. 1, the output of the voltage controlled oscillator 40 is transmitted to the driving coils 1 to 3 through the frequency dividing circuit 41, the conduction switching circuit 44, and the driving transistors 10 to 15. Therefore, there is a certain phase relationship between the output of the voltage controlled oscillator 40 and the energization waveform of the drive coils 1 to 3. That is, by controlling the oscillation frequency and phase of the voltage-controlled oscillator, it is possible to control the phase difference between the drive coil back electromotive voltage and the drive coil conduction waveform. Therefore, as shown in FIGS. 2 (b) and 2 (c), when a deviation of the phase angle の 間 に occurs between the drive coil back electromotive voltage and the drive coil energization waveform, the phase error ψ is detected as a phase error. By providing a phase control loop for controlling the oscillation frequency and phase of the voltage-controlled oscillator 40 so as to be detected and amplified by the amplifier 20 and the error amplifier 30 so that ψ becomes zero, the optimum energizing state as shown in FIG. Can be secured. Therefore, the motor driving torque can always be generated stably and efficiently, and the motor is driven.

Note that the lowest frequency setting circuit 50 generates a rotating magnetic field in the drive coil that can be followed by the mover when the motor is started, thereby enabling the motor to be started.

As a specific configuration of the phase error detector 20, for example, the configuration shown in FIG. 3 can be considered. In FIG. 3, parts having the same functions as those in FIG. 1 are given the same symbols.
That is, one ends U ₀ , V ₀ , W ₀ of the drive coils 1, 2, 3 are input to buffer circuits 21, 22, 23, respectively, and the buffer circuit 2
1,22,23 output U _B, V _B, W _B are commonly connected via respective resistors 24, 25, 26, the common connection point N _B comparison circuit 100, 120,
It is connected to the inverting input terminal 140 and the non-inverting input terminals of the comparing circuits 110, 130, 150. The output U _B of the buffer circuit 21 is connected to the inverting input terminal of the non-inverting input terminal and the comparator circuit 110 of the comparator circuit 100, the output V _B of the buffer circuit 22
Is the non-inverting input terminal of the comparing circuit 120 and the comparing circuit 130
Of the buffer circuit 23.
W _B is the non-inverting said input terminal comparator circuit 1 of the comparator circuit 140
Connected to 50 inverting input terminals. The comparison circuit 100,
Each output of 110,120,130,140,150 is transistor 101,111,1
The collectors of the transistors 101, 111, 121, 131, 141, and 151 are commonly connected to the collector of the transistor 161 to form a phase error detector output PD. The transistor 161
Is connected to the base and collector of transistor 162, and is also connected to the collector of transistor 164 and the collector of transistor 169 which operates as a constant current source. The stabilized power supply voltage Vreg is applied to the emitter of the transistor 162 via the resistor 163, and the stabilized power supply voltage Vreg is applied to the emitters of the transistors 161 and 164. The base of the transistor 164 is connected to the emitter via a resistor 166 and to the collector of a transistor 167 whose emitter is grounded via a resistor 165. Base of the transistor 167 is output S ₀ of the phase difference detecting pulse generating circuit 28 via the resistor 168 is connected. Another output of the phase difference detection pulse generation circuit 28
S ₁ , S ₂ , S ₃ , S ₄ , S ₅ , S ₆ are resistors 171,173,175,177,17 respectively
Transistors 170 and 17 emitter-connected via 9,181
The collectors of the transistors 170, 172, 174, 176, 178, 180 are connected to the bases of the transistors 101, 111, 121, 131, 141, 151, respectively. The phase difference detection pulse generation circuit 28
Are connected to the respective outputs U ₁ , U ₂ , V ₁ , V ₂ ,
W ₁ and W ₂ and the output D ₂ of the frequency dividing circuit 41 are connected.

The operation of the phase error comparator configured as described above will be described below.

FIG. 4 is an explanatory diagram of the operation, and shows a state of detection of a phase error between the back electromotive voltage and the conduction waveform of the drive coil 1. In FIG. 1, FIG. 3, and FIG.
The driving coil 1 has divided outputs D ₁ , D
_The signals U ₁ and U ₂ (that is, U _H and U _L ) synchronized with ₂ are energized as energization command signals. Therefore, a period during which neither U ₁ nor U _{2 is} output is a power supply suspension period, during which the drive coil power supply waveform U ₀ matches the back electromotive voltage U _e . Energization pause period from Figure 4 during a period from when U ₁ is a Low to U ₂ is High, strikes the 1 4 clock of the clock or D ₂ of D _1. U ₂ is the U ₁ from the Low exists energization pause period also in the period until the High but for simplicity of explanation, consider only the period of the former. When the neutral point voltage N ₀ of each drive coil is compared with the drive coil energization waveform U ₀ during the power supply suspension period, when the phase difference U between U ₀ and the drive coil back electromotive voltage U _e is zero, N ₀ and U _{0 0} is the center of the power interruption period, that is,
U ₁ is matched from the Low after two clocks of D _2. If U ₀ lags U _e by a phase difference ψ, N ₀ and U ₀
U ₁ match from the Low to the two clocks after the previous D _2, U
_{If 0} leads U _e by the phase difference ψ, N ₀ and U ₀ are U ₁
match on or after after two clock of D ₂ from when the ow. Thus, U ₀ after 2 clocks D ₂ from when U ₁ is a Low
And N ₀ , the phase relationship between U ₀ and U _e can be known. Therefore, as a method of detecting the phase difference ψ, U ₁
Becomes Low to generate a phase error detection pulse signal S ₂ and S ₀ with appropriate width based on the two clocks after D ₂ from,
By comparing N ₀ and U ₀ only when S ₂ and S ₀ occur,
A comparator output PD having a duty corresponding to the phase difference ψ can be obtained. S ₂ and S ₀ in Fig. 4 occurs period of ± 1/2 clock D ₂ relative to the two clocks after D ₂ from when U ₁ is Low, the phase angle relative to U ₀ is U _e The case where it is delayed by ψ is shown.

Above, with respect to conduction waveform U ₀ of the driving coil 1, U ₁ is Low
Although U ₂ is explained the operating principle for the detection of the conduction pause period phase difference using ψ between until High from when the other conduction rest periods for U _0, i.e. U ₂ is Low
Period from when until U ₁ is High, and the other can also be similarly detected in the energizing waveform V _0, W ₀ of the drive coils 2 and 3, in this embodiment the phase by combining all of these Error detector output PD is obtained.

The buffer circuits 21, 22, and 23 are inverting amplifiers having a gain of 1/2, and the operating input voltage range of each of the comparison circuits 100, 110, 120, 130, 140, and 150 is set to each output U _B , V of the buffer circuits 21, 22, and 23.
_B, W _B are configured so as to satisfy.

FIG. 5 shows the operation waveforms of the respective components when the configuration shown in FIG. 3 is used as the phase error detector 20 in FIG. 1, and the phase difference between the drive coil conduction waveform and the back electromotive voltage is zero. FIG. 6 shows how the oscillation frequency f of the voltage controlled oscillator is controlled so that

The error amplifier output clamp circuit 53 in FIG. 1 will be described.

The error amplifier output clamp circuit 53 includes an error amplifier 30.
Is operated to clamp the output of the phase control loop. That is, at startup, the error amplifier
By clamping the output EAO of 30 to a level at which the oscillation frequency of the voltage controlled oscillator 40 starts to rise,
The output of the phase error detector 20 from startup to steady state
The change in the PD can be smoothly transmitted as the change in the oscillation frequency f of the voltage controlled oscillator 40. Therefore, the phase control loop is quickly pulled in and the motor is driven.

As a specific configuration of the error amplifier output clamp circuit 53, for example, the configuration shown in FIG. 6A can be considered. That is, in FIG. 6A, the reference power source 51
A level clamp means for the output EAO of the error amplifier 30;
The comparison circuit 52 outputs the output EAO of the error amplifier 30 and the reference power supply 51.
Compares the output V _51, EAO detects this when drops to the level of V _51, EAO controls the inverting input of the operational amplifier 31 so as not less than the level of V _51. Thus lowering levels of EAO is limited to the level of V _51. Level where V ₅₁ is the increase start level of the oscillation frequency f of the voltage controlled oscillator 40, when the EAO is clamped at V _51, f is the frequency fmin is set at the lowest frequency setting circuit 50 equally, the EAO is slightly larger than V _51, f starts to rise. Such level V ₅₁ to clamp the EAO output, by waiting, rapidly enables transmission as a change in f the change in the output PD of the startup, and can pull rapid synchronization of the aforementioned phase-locked loop Become.

Although the clamp level of EAO was V _51, in consideration of the offset and the like of each unit circuit, V ₅₁ -ΔV (ΔV = number 10m
V) may be clamped.

FIG. 6B shows the relationship between the output EAO and the oscillation frequency f.

In FIG. 6 (b), V ₅₁ is clamped level of the output EAO, fmin is the minimum oscillation frequency due to the lowest frequency setting circuit.

The reset circuit 60 shown in FIG. 1 outputs the output EAO of the error amplifier 30 to the error amplifier 30 when the phase control loop is out of synchronization when the power is turned on or when the mover is restrained or for some other reason. Output clamp circuit 5
Initialization is performed by clamping at a clamp level of 3, thereby ensuring the phase synchronization of the above-described phase control loop, that is, starting the motor.

 The specific operation will be described below.

FIG. 7 shows a specific circuit configuration of the reset circuit 60. When the power is turned on or the phase control loop is out of synchronization, the output EAO of the error amplifier 30 generally corresponds to the rotation speed of the motor. I haven't. At this time, EAO is rising or falling according to the output PD of the phase error detector 20. When EAO has a downward trend, the oscillation frequency f of the voltage controlled oscillator 40 has a low frequency, and EAO tends to be naturally initialized. Becomes

In such a case, the EAO eventually becomes saturated, an imaginary short between the two input terminals of the operational amplifier 31 does not hold, and the inverting input terminal voltage of the operational amplifier becomes lower than the non-inverting input terminal voltage. This is detected by the comparator 80. That is, the output transistor 85 of the comparator 80 is configured to be turned on when the above-mentioned imaginary short circuit is not established.Once the transistor 85 is turned on, the transistor 64 is turned off by the latch circuit 61 and resets accordingly. The output transistor 67 of the circuit 60 turns on. The collector output S of the output transistor 67 is connected to the S terminal of the phase error detector 20 shown in FIG.
The output PD loses the current sinking ability when 67 is turned on. Therefore, the output PD has only the current discharge capability, and lowers the output EAO of the error amplifier 30. EAO falls until the error amplifier output clamp circuit 53 operates and clamps EAO. That is, when EAO is clamped, the transistor 55 conducts, and the above-described latch circuit 61
And the transistor 64 is turned off, and the transistor 64 is turned on. As a result, the output transistor 67 of the reset circuit 60 is turned off, the current sink capability of the output PD is restored, and the initialization of EAO is completed.

As described above, the reset circuit 60 controls the output of the error amplifier 30.
When the EAO rises and saturates, this is detected, the output PD of the phase error detector 20 is set to the current discharge capability only, and the EAO is lowered.When the EAO is clamped by the operation of the error amplifier output clamp circuit 53, the PD of the PD is detected. The current sink capability has been restored, and the EAO initialization has been completed.

Therefore, by providing the reset circuit 60, the output EAO of the error amplifier 30 is initialized even when the power is turned on or when the above-mentioned phase control loop is out of synchronization for some reason, and the motor is reliably started. Can be.

As described above, according to the present invention, the motor drive coil is energized based on the output of the voltage controlled oscillator, and the phase difference between the energized waveform and the motor drive coil back electromotive voltage is determined by the phase error detector during the energization suspension period. After detecting and amplifying the detected phase error signal by an error amplifier, the signal is input to a voltage-controlled oscillator, and a phase control loop for controlling the output of the voltage-controlled oscillator eliminates the need for a conventionally required filter circuit. Capacitor capacity can be greatly reduced, spike noise included in the drive coil conduction waveform, voltage drop due to conduction current and drive coil impedance, these fluctuations due to fluctuations in power supply voltage and load, and further reduction in efficiency due to armature reaction The output amplifier EAO level can be controlled by the voltage-controlled oscillator by providing the error amplifier output clamp circuit. The phase control loop can be quickly synchronized by clamping at the level at which the oscillation frequency of the oscillator starts rising, and the reset circuit is provided, so that when the power is turned on or the phase control loop loses synchronization. In this case, the output of the error amplifier can be initialized, and the motor can be reliably started. Further, by using an IC, it is possible to realize a brushless motor driving device having extremely excellent characteristics at a low cost with an extremely small number of external parts.

In the embodiment of the present invention, the case of the three-phase full-wave drive system has been described. A motor drive is feasible.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a brushless motor driving device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation principle of FIG. 1, FIG. 3 is a specific circuit configuration diagram of a phase error detector, FIG.
3 is an explanatory diagram of the operation in FIG. 3, FIG. 5 is an operation waveform diagram in the embodiment of the present invention, FIG. 6 is a specific circuit configuration diagram of an error amplifier and an error amplifier output clamp circuit, and FIG. FIG. 8 is a circuit diagram of a conventional brushless motor driving device, FIG. 9 is an operation explanatory diagram of FIG. 8, and FIG. 10 is a circuit diagram of another conventional brushless motor driving device. FIG. 11 is a configuration diagram, and FIG. 11 is an operation explanatory diagram of FIG. 1-3 drive coil, 10-15 drive transistor,
Reference numeral 20: phase error detector, 30: error amplifier, 40: voltage-controlled oscillator, 44: conduction switching circuit, 53: error amplifier output clamp circuit, 60: reset circuit

Claims (1)

(57) [Claims] 1. A motor drive coil of a plurality of phases, a plurality of drive transistors connected to the drive coil, a power supply switching circuit for sequentially transmitting a power supply switching signal of the drive coil to the drive transistor, and the power supply switching circuit A voltage-controlled oscillator for inputting a signal having an appropriate frequency, a back-EMF voltage generated in the drive coil during the power supply suspension period of the drive coil, and a phase error detection for detecting a phase difference between the power supply switching signal of the drive coil. An error amplifier for amplifying the output of the phase error detector and inputting the output to the voltage controlled oscillator, an error amplifier output clamp circuit for clamping the output of the error amplifier at an appropriate level, and an output of the error amplifier. When the limit of the effective operation range is reached, initialization of the output of the error amplifier is started, and the error amplifier output clamp circuit starts the error amplifier. If the output of the amplifier is clamped, a brushless motor driving device constructed in accordance with a reset circuit for terminating the initialization of the output of the error amplifier.