JPH01229496A - Gaas integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the leakage current of a transfer gate for prevention of wrong writing in a memory cell and to ensure the stable working of a GaAs integrated circuit by using a means which is connected to a 1st node which secures the connection between the sources of two normally-off type drive MESFETs and clamps the 1st node at a potential higher than the earth potential only when a word line is set under a non-selection state. CONSTITUTION:A clamp means 8 which clamps a 1st node 20 at a potential higher than the earth potential only when a word line is set under a non- selection state is connected to the node 20 which secures the connection between the sources of two normally-off type drive MESFETs forming a memory cell. In other words, the voltage of the low potential side node in a non-selection memory cell is clamped by the means 8 at a potential higher than the earth potential. Thus it is possible to keep a transfer gate under a reverse bias state even in case a low potential of about 0.1V is applied to the transfer gate and to reduce the leakage current.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to gallium arsenide integrated circuits, and particularly to MES
This relates to a static RAM using FET.

[Conventional technology]

Figure 10 shows, for example, the 1982 GaAs IC Symposium, Technical Digest (GaAs ICSy-m
posiu+s+Technical Iligest
) In Fig. 0, which shows the structure of the conventional gallium arsenide memory element shown in Fig. 1 of pp. 4, 1.
3 is a normally-on type MESFET, and 2.4.5.6 is a normally-off type MESFET. vDD is a positive power supply. B.

(2) are the bit line and hvA, respectively. WL is a word line and is connected to a word line drive circuit composed of a DCFL circuit or a super buffer circuit.

Normally-on type MESFETI and normally-off type MES
A flip-flop circuit is formed by connecting the outputs of two DCFL inverters composed of FET2, normally-on type MESFET3, and normally-off type MESFET74 to each other's gates, and
By connecting the output of the FL inverter to the left and right bit lines B and 75.6 through a normally-off type MESFE 75.6 as a transfer gate, a static memory cell consisting of 6 transistors is constructed.

This memory cell is set to “1” and “1” depending on which of the normally-off MESFETs 2 and 4 is in the on state.
0'' information is stored.

Information is read by setting the word line WL to a high potential, making the transfer gate 5.6 conductive, and transmitting the stored information of the memory cell to the bit line pair B and 100.

Furthermore, information is written by turning on the transfer gates 5 and 6 and transmitting input data from the data input buffer sofa to the memory cell via the bit line pair B and (2).

[Problem to be solved by the invention]

Conventionally, when this memory cell is formed on a gallium arsenide substrate, in a memory cell in which word line WL is in a low potential and non-selected state, leakage current flowing through transfer gates 5 and 6 causes bit line B and There has been a problem in that erroneous writing to the memory cells may occur, and information in the memory cells may be destroyed.

That is, in the non-selected state, the internal nodes of the memory cell shown in FIG. 10 have a high potential of about 0.6 V and a low potential of approximately ground potential. On the other hand, in a word line drive circuit composed of DCFL, the low level of the output is MESFE.
The value is about the dark value voltage of T. Therefore, the gate voltage of the transfer gates 5 and 6 connected to the word line WL in the non-selected state is approximately the threshold voltage of the MESFET, and since the low potential side of the memory cell internal node is approximately at ground potential, the gates are forward biased. state. In a gallium arsenide MESFET, the drain-source current Ids becomes minimum when the gate-source voltage Vgs is about 0.3V lower than the dark value voltage, and when Vgs is the threshold voltage, it is about 103 times or more of the minimum value. current flows. Therefore, when reading information from a memory cell in a selected state to a bit line, leakage current from other memory cells in an unselected state causes the bit line on the high potential side of the left and right bit line pair to There is a problem in that the potential drops and the potential of the bit line on the low potential side rises, resulting in erroneous writing to the selected memory cell.

In order to solve such problems, for example, as shown in FIG.
4-130. pp65. There is a circuit shown in FIG. This aims to reduce leakage current by setting the low level of the word line potential in the non-selected state to a deep negative value by using a level shift circuit, and by setting the gate voltage of the transfer gate 5.6 to a deep reverse bias state. It is. However, there was a drawback that the level shift circuit required two positive and negative power supplies.

This invention was made to solve the above-mentioned problems, and it provides a gallium arsenide integrated circuit that can reduce transfer gate leakage current, prevent erroneous writing to memory cells, and achieve stable operation. The purpose is to obtain.

[Means to solve the problem]

In the gallium arsenide integrated circuit according to the present invention, the first node connecting the sources of two normally-off drive MESFETs constituting a memory cell is grounded only when a word line is in a non-selected state. A clamping means for clamping to a higher potential than the potential is connected and provided.

[Effect]

In this invention, the voltage of the low potential side node in the unselected memory cell is clamped to a potential higher than the ground potential by the clamping means, so that the voltage at the low potential side node in the unselected memory cell is clamped to a potential higher than the ground potential. I
Even when a low potential of about V is applied, the gate can be maintained in a reverse bias state, and leakage current can be reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a gallium arsenide integrated circuit according to a first embodiment of the present invention, in which 1.3 is a normally-on type M
ESFET, 2, 4, 5.6 are normally-off type MESF
*VDD, which is ET, is the positive power supply. B and B are a bit line and B1vA, respectively. WL is a word line,
This is connected to a word line drive circuit composed of a DCFL circuit or a super buffer circuit. 7 is a normally-off MESFET, and 8 is a Schottky diode. One normally-off type MESFET and one Schottky diode 8 are provided for each memory cell, and the drain of the normally-off type MESFET 7 and the anode of the Schottky diode 8 are connected to the source of the memory cell driver MESFET 2゜4. 1
is connected to the node 20 of. Normally-off type MES
The source of FET 7 and the cathode of Schottky diode 8 are connected to ground potential. R3 is a row selection signal, which changes at the same level or in phase with WL.

Next, the operation will be explained.

(2) Assume that 1.5 (2) is applied to o0. In the selected state, the word line WL has a high potential of about 0.6 V, which is applied to the gates of transfer gates 5 and 6. At the same time, the row selection signal R3, which is the same or in-phase signal as WL, is applied to the normally-off MESFET 7. is applied to the gate, making MESFET 7 conductive and lowering the drain voltage to approximately ground potential. Since the drain of the normally-off MESFET 7 is connected to the first node 20, the internal node of the memory cell has a high potential side of about 0.6 V and a low potential side of approximately ground potential, and this potential is applied to the bit via the transfer gate. Bit line potentials are read or written by transferring bit line potentials to internal nodes of the memory cell.

In the non-selection signal, word line WL, row selection signal R3
Both have a low potential of about 0.1■. At this time, the normally-off MESFET 7 becomes non-conductive, and the drain voltage is clamped to a potential of about 0.6 V by the Schottky diode 8.

Therefore, the internal node of the memory cell is 1°2■ on the high potential side.
The potential on the low potential side is about 0.6 .

Regarding the bit line, depending on the bit line load (not shown), the voltage on the high potential side is approximately 0.6 V, and the voltage on the low potential side is approximately 0.4 V.
The potential will be approximately.

Therefore, in this embodiment, even when a potential of about O,'lV is applied to the gates of transfer gates 5 and 6, the low potential side of the internal node of the memory cell is connected to the Schottky diode 8 by about 0.6V. Since it is clamped to the potential, the gate will be in a deep reverse bias state,
Leakage current can be sufficiently reduced, and erroneous writing to memory cells can be prevented.

FIG. 2 shows a second embodiment of the invention, in which a resistive element 8' is used in place of the Schottky diode in FIG.

FIG. 3 shows a third embodiment of the present invention, in which one normally-off MESFET 7 is provided in each row, and one Schottky diode 8 is provided in each memory cell. Further, FIG. 4 shows a fourth embodiment in which a resistance element 8' is used in place of the Schottky diode 8 in FIG.

FIG. 5 shows a fifth embodiment of the present invention, in which one Schottky diode 8 is provided for each row, and one normally-off MESFET 7 is provided for each memory cell. Further, FIG. 6 shows a sixth embodiment in which a resistive element 8' is used in place of the Schottky diode in FIG.

FIG. 7 shows a seventh embodiment of the present invention, in which both a normally-off type MESFE 77 and a Schottky diode 8 are provided in each memory cell. Further, FIG. 8 shows an eighth embodiment in which a resistive element 8' is used in place of the Schottky diode in FIG. 7.

FIG. 9 shows a ninth embodiment of the present invention, which is an example in which the present invention is applied to a circuit that operates with a single negative power supply.

Note that the exchange of the positive power source and negative power source is also possible in the second to eighth embodiments.

Also in the second to ninth embodiments, the same effects as in the first embodiment described above can be achieved.

Note that in the first to ninth embodiments described above, Schottky diodes are used as diodes, but the same effects can be obtained even if PN diodes are used as diodes.

〔Effect of the invention〕

As described above, according to the present invention, one normally-on type load MESFET and one normally-off type drive MESFET
A flip-flop formed by cross-coupling the outputs of two inverter circuits consisting of SFETs to each other's gates;
In a gallium arsenide integrated circuit having two transfer gates respectively connecting the two inverter outputs to a pair of bit lines, a first node connecting the sources of the two normally-off drive MESFETs; Since a clamp means is connected to clamp the first node to a potential higher than the ground potential only when the word line is in a non-selected state, leakage current of the transfer gate of the memory cell can be reduced even under a single power supply. This has the effect of preventing erroneous writing to memory and cells, and achieving stable memory operation.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a gallium arsenide integrated circuit according to a first embodiment of the present invention, and FIGS. 2 to 9 are circuit diagrams showing gallium arsenide integrated circuits according to second to ninth embodiments of the present invention. , FIG. 10, and FIG. 11 are circuit diagrams showing conventional gallium arsenide integrated circuits, respectively. In the figure, 1.3 is a normally-on MESFET, 2
, 4.5, 6.7 are normally-off MESFETs, 8 is a Schottky diode, 8' is a resistive element, 20 is a first node, B is a bit line, 100 is a bit line, R3 is a row selection signal, WL is a word The line, vaD, is the positive power supply. Note that the same reference numerals in the figures indicate the same or equivalent parts. Patent applicant Kozo Iizuka, Director-General of the Agency of Industrial Science and Technology

Claims (1)

[Claims] (1) A flip-flop formed on a gallium arsenide substrate, in which the outputs of two inverter circuits each consisting of one normally-on load MESFET and one normally-off drive MESFET are cross-coupled to each other's gates; In a gallium arsenide integrated circuit having two transfer gates respectively connecting the two inverter outputs to a pair of bit lines, a first node connecting the sources of the two normally-off drive MESFETs; gallium arsenide, comprising clamping means that clamps the first node to a potential higher than a ground potential only when the word line connected to the two transfer gates is in a non-selected state. integrated circuit.