JPH01229229A - Thin-film transistor of amorphous silicon and production thereof - Google Patents
Thin-film transistor of amorphous silicon and production thereofInfo
- Publication number
- JPH01229229A JPH01229229A JP63055877A JP5587788A JPH01229229A JP H01229229 A JPH01229229 A JP H01229229A JP 63055877 A JP63055877 A JP 63055877A JP 5587788 A JP5587788 A JP 5587788A JP H01229229 A JPH01229229 A JP H01229229A
- Authority
- JP
- Japan
- Prior art keywords
- polymer layer
- layer
- heat
- organic polymer
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021417 amorphous silicon Inorganic materials 0.000 title claims description 16
- 239000010409 thin film Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229920000642 polymer Polymers 0.000 claims abstract description 9
- 229920000620 organic polymer Polymers 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 10
- 239000004642 Polyimide Substances 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 229920000592 inorganic polymer Polymers 0.000 claims 1
- 230000001678 irradiating effect Effects 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 230000002950 deficient Effects 0.000 abstract 2
- 206010034972 Photosensitivity reaction Diseases 0.000 abstract 1
- 230000036211 photosensitivity Effects 0.000 abstract 1
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 6
- 238000010304 firing Methods 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［産業−１二の利用分Ｗ］
本発明は、アクティブマトリクス型ｉｆｋ品表示器のス
イッチング素子等に用いられる、非晶質シリコン（以下
、ａ−３ｉという）薄膜トランジスタ（以下、ＴＰＴと
いう）およびその製造方法に関するものである。Detailed Description of the Invention [Industry-12 Applications W] The present invention relates to an amorphous silicon (hereinafter referred to as A-3I) thin film transistor (hereinafter referred to as A-3I) used as a switching element of an active matrix type IFK product display. (hereinafter referred to as TPT) and its manufacturing method.
［従来の技術］
ａ−５ｉＴＦＴは、アクティブマトリクス型液晶表示器
のスイッチング素子として、各所で研究開発か行われて
いる。[Prior Art] A-5i TFT is being researched and developed in various places as a switching element for active matrix liquid crystal displays.
第６図は、上記アクティブマトリクス型液晶表示器の構
成例を示した電気回路図である。ゲート配線２−のうち
例えばＸｌが選択されると、これに連なるＴＰＴ２１の
ゲートは一斉にオンし、これらオンしたＴＰＴ２１のソ
ースを通して、ソース配線１１より画像情報に対応した
信号電圧かＴＰＴ２１のトレインに伝達される。このド
レインには画素電極１２が接続され、この画素電極１２
と、液晶層２２を挟んで対向した基板上に形成された対
向電極２３との電圧差により、液晶層２２の光透過率を
変化させて画像表示を行う。また、上記ゲートがオフし
た後も、１−副画素電極１２と対向電極２３との電圧差
は、次に同一のＴＰＴ２１か選択されるまで、液晶層２
２の容Ｍ成分により保持されるため、液晶層２２は原理
的にスタティック駆動されることになり、高品質の画像
表示を得ることができる。FIG. 6 is an electrical circuit diagram showing an example of the configuration of the active matrix type liquid crystal display. When, for example, Xl is selected among the gate wirings 2-, the gates of the TPTs 21 connected to it are turned on all at once, and a signal voltage corresponding to image information is transmitted from the source wiring 11 to the train of the TPTs 21 through the sources of these turned-on TPTs 21. communicated. A pixel electrode 12 is connected to this drain, and this pixel electrode 12
The light transmittance of the liquid crystal layer 22 is changed by a voltage difference between the liquid crystal layer 22 and a counter electrode 23 formed on a substrate opposite to each other with the liquid crystal layer 22 in between, thereby displaying an image. Further, even after the gate is turned off, the voltage difference between the 1-subpixel electrode 12 and the counter electrode 23 remains constant until the same TPT 21 is selected next time.
Since the liquid crystal layer 22 is held by the capacity M component of 2, the liquid crystal layer 22 is statically driven in principle, and a high-quality image display can be obtained.
第７図は、上記ＴＰＴに用いられるａ−８ｉＴＦＴの一
例を示した断面図である。同図において、１は絶縁性基
板、２はゲート電極、４はケート絶縁層となる無機絶縁
層、８は非晶質シリコン層、９はソース電極、１０はド
レイン電極、１１はソース配線、１２は画素電極である
。FIG. 7 is a sectional view showing an example of an a-8i TFT used in the TPT. In the figure, 1 is an insulating substrate, 2 is a gate electrode, 4 is an inorganic insulating layer serving as a gate insulating layer, 8 is an amorphous silicon layer, 9 is a source electrode, 10 is a drain electrode, 11 is a source wiring, 12 is the pixel electrode.
［発明が解決しようとする課題］
」１記ａ−３ｉＴＦＴでは、ゲート電極２とソース電極
９、ゲート電極２とドレイン電極１ｏのオーバーラツプ
部分で絶縁不良を生じることがあり、ａ−３ｉＴＦＴの
歩留りに対し悪影響をＩｊえている。特にゲート電極２
の段差部分では、無機絶縁層４の膜厚が薄くなるため、
」１記絶縁不良を生じる確率が、他の部分に比べて圧倒
的に高い。[Problems to be Solved by the Invention] In the a-3i TFT described in 1., insulation defects may occur in the overlapped portions of the gate electrode 2 and the source electrode 9, and the gate electrode 2 and the drain electrode 1o, which reduces the yield of the a-3i TFT. On the other hand, it has a negative impact. Especially gate electrode 2
Because the thickness of the inorganic insulating layer 4 becomes thinner in the stepped portion,
``The probability of occurrence of insulation failure in item 1 is overwhelmingly higher than in other parts.
また、ａ−８ｉＴＦＴをアクティブマトリクス型液晶表
示器に用いる場合、ゲート配線とソース配線の交差部で
も絶縁不良を生じる。Furthermore, when the a-8i TFT is used in an active matrix type liquid crystal display, insulation failure also occurs at the intersection of the gate wiring and the source wiring.
第８図は上記ゲート配線とソース配線の交差部を示した
断面図である。同図において１は絶縁性基板、２′はゲ
ート配線、４は無機絶縁層、１１はソース配線である。FIG. 8 is a sectional view showing the intersection of the gate wiring and the source wiring. In the figure, 1 is an insulating substrate, 2' is a gate wiring, 4 is an inorganic insulating layer, and 11 is a source wiring.
この場合においても、絶縁破壊の生じる部分は、ゲート
配線２′の段差部が圧倒的に多い。Even in this case, the portion where dielectric breakdown occurs is overwhelmingly the stepped portion of the gate wiring 2'.
以上述べたように、ゲート電極あるいはゲート配線（以
下、特にことわらない限り、両者をまとめてゲート電極
という）の段差部での絶縁破壊は、ａ−８ｉＴＦＴの製
造歩留りを大幅に低下させていた。As mentioned above, dielectric breakdown at the stepped portion of the gate electrode or gate wiring (hereinafter, unless otherwise specified, both are collectively referred to as the gate electrode) significantly reduced the manufacturing yield of a-8i TFTs. .
本発明は、上記従来の課題に対してなされたものであり
、ゲート電極の段差部での絶縁破壊の生じる確率を低減
させることをｌ」的としている。The present invention has been made to solve the above-mentioned conventional problems, and its objective is to reduce the probability of dielectric breakdown occurring at the stepped portion of the gate electrode.
［課題を解決するための手段］
本発明は、ゲート電極か形成された絶縁性」１（板−１
−に、耐熱性何機高分子層が、−１−化ゲート電極によ
る段差を平坦化するようにして形成され、この耐熱性有
機高分子層」二に、無機絶縁層か形成されていることを
特徴とする非晶質シリコン薄膜トランジスタを提供する
ことにより、−に記課題を解決するものである。[Means for Solving the Problems] The present invention provides an insulating material 1 (plate-1) formed with a gate electrode.
- a heat-resistant organic polymer layer is formed to flatten the step caused by the -1- gate electrode; and second, an inorganic insulating layer is formed. By providing an amorphous silicon thin film transistor characterized by the following, the problems described in - are solved.
この場合、無機絶縁層を耐熱性何機高分子層よりもオー
バーサイズで形成することが好ましく、また耐熱性有機
高分子層を感光性のものとし、基板裏面より光を照射し
て露光し、現像することによりゲート電極上の同層を除
去することがゲート電極段差を平坦化する」二でより好
ましい。In this case, it is preferable to form the inorganic insulating layer in an oversized size than the heat-resistant organic polymer layer, and the heat-resistant organic polymer layer is photosensitive, and the layer is exposed to light from the back side of the substrate. It is more preferable to remove the same layer on the gate electrode by developing to flatten the gate electrode step.
さらに無機絶縁層として少なくとも窒化シリコン層を用
いることにより信頼性がより向」ニする。Furthermore, reliability is further improved by using at least a silicon nitride layer as the inorganic insulating layer.
［実施例］ 以下、本発明における実施例を図面に基いて説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.
第１図および第２図において、１は絶縁性基板、２はゲ
ート電極、３は耐熱性有機高分子層、４は無機絶縁層、
５は無機絶縁層の第１層を形成する窒化シリコン層、６
は第２層を形成する酸化シリコン層、７は紫外光、１３
はマスクである。1 and 2, 1 is an insulating substrate, 2 is a gate electrode, 3 is a heat-resistant organic polymer layer, 4 is an inorganic insulating layer,
5 is a silicon nitride layer forming the first layer of the inorganic insulating layer; 6
is a silicon oxide layer forming the second layer, 7 is ultraviolet light, 13
is a mask.
以下、第１図および第２図における（ａ）、（ｂ）、（
ｃ）で示した工程順に従い説明を行う。Hereinafter, (a), (b), (
The explanation will be given according to the process order shown in c).
（ａ）クロム等を用いた厚さ２００ ｎ ｍのゲート電
極２か形成された絶縁性基板１上に、感光性を有した耐
熱性有機高分子層３として、耐熱性ポリイミド溶液をス
ピナーにより塗布し、これを窒素雰囲気中、８０°Ｃで
３０分間プリベークした後、所定の形状を有したマスク
１３により基板周辺部をマスクして、紫外光７により露
光する。(a) A heat-resistant polyimide solution is applied using a spinner as a photosensitive heat-resistant organic polymer layer 3 on an insulating substrate 1 on which a 200 nm thick gate electrode 2 made of chromium or the like is formed. After prebaking this at 80° C. for 30 minutes in a nitrogen atmosphere, the peripheral portion of the substrate is masked with a mask 13 having a predetermined shape, and exposed to ultraviolet light 7.
（ｂ）露光された耐熱性有機高分子層３を、Ｎ−メチル
−ピロリドン溶液により現像して、基板周辺部の耐熱性
有機高分子層３を除去し、イソプロピルアルコールによ
りリンスを行い、乾燥後、窒素雰囲気中、２００°Ｃて
３０分間仮焼成し、さらに４００°Ｃて１時間本焼成を
する。(b) The exposed heat-resistant organic polymer layer 3 is developed with an N-methyl-pyrrolidone solution to remove the heat-resistant organic polymer layer 3 around the substrate, rinsed with isopropyl alcohol, and dried. , pre-baking at 200°C for 30 minutes in a nitrogen atmosphere, and then main firing at 400°C for 1 hour.
本焼成後の耐熱性高分子層３の膜厚はゲート電極２１ユ
て７０ ｎ ｍ、これ以外の部分で２００ ｎ ｍであ
り、両者間の段差は非常に緩かになっている。The film thickness of the heat-resistant polymer layer 3 after main firing is 70 nm at the gate electrode 21 and 200 nm at other parts, and the difference in level between the two is very gentle.
なお、本焼成の温度は、以後のＴＰＴ作成の最高温度（
通常は３００°Ｃ前後）よりも高くすることが重要であ
る。The temperature of the main firing is the highest temperature for subsequent TPT production (
It is important to keep the temperature higher than 300°C (usually around 300°C).
（ｃ）無機絶縁層４として、窒化シリコン層５を７Ｑｎ
ｍ、酸化シリコン層６を２Ｑ Ｑ ｎ ｍ、基板温度３
００°Ｃにて、プラズマＣＶＤ法により形成する。この
時、上記無機絶縁層４は、耐熱性何機高分子層３よりも
オーバーサイズで形成する。(c) As the inorganic insulating layer 4, the silicon nitride layer 5 is 7Qn
m, silicon oxide layer 6 2Q Q n m, substrate temperature 3
It is formed by plasma CVD method at 00°C. At this time, the inorganic insulating layer 4 is formed to be larger than the heat-resistant organic polymer layer 3.
これは以後のエツチング工程のとき無機絶縁層４により
、エツチング液から耐熱性有機高分子層３を保護するた
めである。また窒化シリコン層５は、耐熱性有機高分子
層３に含まれるアルカリイオンの移動を遮断するために
設けられたものであり、ａ−３ｉＴＦＴの信頼性の観点
から重要である。This is to protect the heat-resistant organic polymer layer 3 from the etching solution by the inorganic insulating layer 4 during the subsequent etching process. Furthermore, the silicon nitride layer 5 is provided to block movement of alkali ions contained in the heat-resistant organic polymer layer 3, and is important from the viewpoint of reliability of the a-3i TFT.
なお、無機絶縁層４は必ずしも多層にする必要はないか
、少なくとも窒化シリコン層は、」Ｌ記理由により設け
ることか好ましい。Note that the inorganic insulating layer 4 does not necessarily have to be multilayered, or at least a silicon nitride layer is preferably provided for the reasons listed in "L."
第３図および第４図は、」−記第１の実施例によりゲー
ト絶縁層を形成したときのａ−８ｉＴＦＴの断面図と、
ゲート配線の断面図である。８は非晶質シリコン層、９
はソース電極、１０はトレイン電極、１１はソース配線
、１２は画素電極である。耐熱性有機高分子層３を設け
たことにより、無機絶縁層４が平坦化されるため、ケー
ト電極２およびゲート配線２′の段差部においても、無
機絶縁層の膜厚はほぼ均一である。従って上記段差部で
の絶縁不良の発生確率は大幅に低減する。3 and 4 are cross-sectional views of an a-8i TFT when a gate insulating layer is formed according to the first embodiment, and
FIG. 3 is a cross-sectional view of gate wiring. 8 is an amorphous silicon layer, 9
1 is a source electrode, 10 is a train electrode, 11 is a source wiring, and 12 is a pixel electrode. Since the inorganic insulating layer 4 is planarized by providing the heat-resistant organic polymer layer 3, the thickness of the inorganic insulating layer is almost uniform even at the stepped portions of the gate electrode 2 and the gate wiring 2'. Therefore, the probability of occurrence of insulation failure at the stepped portion is significantly reduced.
第５図は、本発明における第２の実施例を示した工程断
面図である。FIG. 5 is a process sectional view showing a second embodiment of the present invention.
（ａ）クロム等を用いた厚さ２００ｎｍのゲート電極２
が形成された透光性の絶縁性基板１にに、感光性を有し
た耐熱性有機高分子層３として、耐熱性ポリイミド溶液
をスピナーにより塗布し、これを窒素雰囲気中、８０°
Ｃて３０分間プリベークし、絶縁性基板１の裏面より紫
外光７を照射する。このとき耐熱性有機高分子層３は、
紫外光７を遮断するゲート電極２か形成された部分以外
が露光される。(a) Gate electrode 2 with a thickness of 200 nm using chromium etc.
A heat-resistant polyimide solution is applied as a photosensitive heat-resistant organic polymer layer 3 to the light-transmissive insulating substrate 1 on which is formed a heat-resistant polyimide solution using a spinner.
After prebaking for 30 minutes at C, ultraviolet light 7 is irradiated from the back surface of the insulating substrate 1. At this time, the heat-resistant organic polymer layer 3 is
The portion other than the portion where the gate electrode 2 that blocks ultraviolet light 7 is formed is exposed.
（ｂ）露光された耐熱性有機高分子層３を、Ｎ−メチル
−ピロリドン溶液により現像して、ゲート電極２上の耐
熱性有機高分子層３を除去し、イソプロピルアルコール
によりリンスを行って、乾燥後、窒素雰囲気中、２００
°Ｃて３０分間仮焼成し、さらに４００°Ｃで１時間本
焼成する。本焼成後の耐熱性有機高分子層３の膜厚は２
００ｎｍであり、これはゲート電極２の膜ｊψと等しい
。(b) Developing the exposed heat-resistant organic polymer layer 3 with an N-methyl-pyrrolidone solution to remove the heat-resistant organic polymer layer 3 on the gate electrode 2, rinsing with isopropyl alcohol, After drying, in a nitrogen atmosphere, 200
Preliminary firing was performed at 400°C for 30 minutes, and then main firing was performed at 400°C for 1 hour. The film thickness of the heat-resistant organic polymer layer 3 after main firing is 2
00 nm, which is equal to the film jψ of the gate electrode 2.
（ｃ）無機絶縁層４として、窒化シリコン層５を７０ｎ
ｍ、酸化シリコン層６を２００ｎｍ、基板温度３００°
Ｃにて、プラズマＣＶＤ法により形成する。(c) As the inorganic insulating layer 4, a silicon nitride layer 5 of 70nm is used.
m, silicon oxide layer 6 200 nm, substrate temperature 300°
It is formed by plasma CVD method at C.
以１−のようにして形成されたものは、ゲート電極２」
二の耐熱性有機高分子層３が除去されているため、無機
絶縁層４は、はぼ完全な平坦化か可能となる。従って実
施例１よりもさらに絶縁不良対策として有効である。The gate electrode 2 is formed as described in 1- below.
Since the second heat-resistant organic polymer layer 3 is removed, the inorganic insulating layer 4 can be almost completely planarized. Therefore, this embodiment is more effective than the first embodiment as a countermeasure against insulation defects.
［発明の効果］
本発明によれば、耐熱性有機高分子層を設けることによ
り、無機絶縁層の平坦化がはがれるため、ゲート電極の
段差部での絶縁不良の発生確率が大幅に減少するため、
製造歩留りを大幅に向上することができる。[Effects of the Invention] According to the present invention, by providing a heat-resistant organic polymer layer, the flattening of the inorganic insulating layer is peeled off, so the probability of occurrence of insulation failure at the stepped portion of the gate electrode is significantly reduced. ,
Manufacturing yield can be significantly improved.
また、無機絶縁層を耐熱性有機高分子層よりもオーバー
サイズで形成することにより、エツチング工程での耐熱
性有機高分子層の保護が可能となる。Furthermore, by forming the inorganic insulating layer to be larger than the heat-resistant organic polymer layer, the heat-resistant organic polymer layer can be protected during the etching process.
さらに、無機絶縁層の少なくとも１層を窒化シリコン層
とすることにより、耐熱性有機高分子層に含まれるアル
カリイオンの遮断が可能となり、非晶質シリコン薄膜ト
ランジスタの信頼性を損うことはない。Furthermore, by using a silicon nitride layer as at least one of the inorganic insulating layers, alkali ions contained in the heat-resistant organic polymer layer can be blocked, and the reliability of the amorphous silicon thin film transistor is not impaired.
感光性を有した耐熱性有機高分子層を基板裏面より露光
して、ゲート電極上の耐熱性有機高分子層を除去する工
程を有して製造される非晶質シリコンＮＩＭ！トランジ
スタでは、無機絶縁層をほぼ完全に平坦化することが可
能となるため、絶縁不良の確率はさらに減少し、−層の
歩留り向」二が達成できる。Amorphous silicon NIM manufactured by exposing a photosensitive heat-resistant organic polymer layer from the back side of the substrate and removing the heat-resistant organic polymer layer on the gate electrode! In transistors, it is possible to almost completely planarize the inorganic insulating layer, so the probability of insulation defects is further reduced, and an improved layer yield ratio can be achieved.
第１図は本発明における第１の実施例を示した工程の断
面図、第２図は工程の斜視図、第３図および第４図はそ
れぞれ上記第１の実施例における工程で形成された非晶
質シリコン薄膜トランジスタおよびゲート配線の断面図
、第５図は本発明における第２の実施例を示した工程の
断面図、第６図はアクティブマトリクス型液晶表示器の
構成を示した電気回路図、第７図および第８図はそれぞ
れ従来技術によるゲート絶縁層を用いた非晶質シリコン
薄膜トランジスタおよびゲート配線の断面図である。
１・・・絶縁性基板
２・・ゲート電極
３・・・耐熱性有機高分子層
４・・・無機絶縁層
５・・・窒化シリコン層
６・・・酸化シリコン層
７・・・紫外光
ぐ−〈フ一一Fig. 1 is a cross-sectional view of the process showing the first embodiment of the present invention, Fig. 2 is a perspective view of the process, and Figs. 3 and 4 are each formed in the process of the above first embodiment. 5 is a sectional view of an amorphous silicon thin film transistor and gate wiring, FIG. 5 is a sectional view of a process showing a second embodiment of the present invention, and FIG. 6 is an electric circuit diagram showing the configuration of an active matrix liquid crystal display. , 7 and 8 are cross-sectional views of an amorphous silicon thin film transistor using a gate insulating layer and a gate wiring according to the prior art, respectively. 1... Insulating substrate 2... Gate electrode 3... Heat resistant organic polymer layer 4... Inorganic insulating layer 5... Silicon nitride layer 6... Silicon oxide layer 7... Ultraviolet light −〈Fuichiichi
Claims (7)
機高分子層が、上記ゲート電極による段差を平坦化する
ようにして形成され、この耐熱性有機高分子層上に、無
機絶縁層が形成されていることを特徴とする非晶質シリ
コン薄膜トランジスタ。(1) A heat-resistant organic polymer layer is formed on the insulating substrate on which the gate electrode is formed so as to flatten the step caused by the gate electrode, and an inorganic insulating layer is formed on the heat-resistant organic polymer layer. An amorphous silicon thin film transistor characterized in that it is formed with.
もオーバーサイズで形成されていることを特徴とする請
求項１記載の非晶質シリコン薄膜トランジスタ。(2) The amorphous silicon thin film transistor according to claim 1, wherein the inorganic insulating layer is formed to be larger than the heat-resistant organic polymer layer.
とを特徴とする請求項１または２記載の非晶質シリコン
薄膜トランジスタ。(3) The amorphous silicon thin film transistor according to claim 1 or 2, wherein the heat-resistant organic polymer layer is photosensitive.
り形成されていることを特徴とする請求項１または２記
載の非晶質シリコン薄膜トランジスタ。(4) The amorphous silicon thin film transistor according to claim 1 or 2, wherein the heat-resistant organic polymer layer is formed of heat-resistant polyimide.
くとも１層以上の絶縁層により形成されていることを特
徴とする請求項１または２記載の非晶質シリコン薄膜ト
ランジスタ。(5) The amorphous silicon thin film transistor according to claim 1 or 2, wherein the inorganic insulating layer is formed of at least one insulating layer including a silicon nitride layer.
を有した有機高分子層を形成する工程と、この耐熱性有
機高分子層を所定の形状に露光、現像する工程と、この
露光、現像された耐熱性高分子層上に、無機絶縁層を、
上記露光、現像された耐熱性有機高分子層よりもオーバ
ーサイズで形成する工程とからなる非晶質シリコン薄膜
トランジスタの製造方法。(6) A step of forming a photosensitive organic polymer layer on the insulating substrate on which the gate electrode is formed, a step of exposing and developing this heat-resistant organic polymer layer into a predetermined shape, and An inorganic insulating layer is placed on the exposed and developed heat-resistant polymer layer.
A method for manufacturing an amorphous silicon thin film transistor comprising the step of forming an oversized heat-resistant organic polymer layer than the exposed and developed heat-resistant organic polymer layer.
、感光性を有した耐熱性有機高分子層を形成する工程と
、上記透光性の絶縁性基板の裏面より光を照射して、上
記ゲート電極が形成されていない部分の上記耐熱性有機
高分子層を露光する工程と、この耐熱性有機高分子層を
現像する工程と、この現像された有機高分子層上に無機
絶縁層を形成する工程とからなる非晶質シリコン薄膜ト
ランジスタの製造方法。(7) Forming a photosensitive, heat-resistant organic polymer layer on the light-transmitting insulating substrate on which the gate electrode is formed, and irradiating light from the back side of the light-transmitting insulating substrate. Then, a step of exposing the heat-resistant organic polymer layer in the portion where the gate electrode is not formed, a step of developing this heat-resistant organic polymer layer, and an inorganic polymer layer on the developed organic polymer layer. A method for manufacturing an amorphous silicon thin film transistor, which comprises a step of forming an insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63055877A JPH01229229A (en) | 1988-03-09 | 1988-03-09 | Thin-film transistor of amorphous silicon and production thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63055877A JPH01229229A (en) | 1988-03-09 | 1988-03-09 | Thin-film transistor of amorphous silicon and production thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01229229A true JPH01229229A (en) | 1989-09-12 |
Family
ID=13011325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63055877A Pending JPH01229229A (en) | 1988-03-09 | 1988-03-09 | Thin-film transistor of amorphous silicon and production thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01229229A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5550390A (en) * | 1991-08-08 | 1996-08-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| US5859444A (en) * | 1991-08-08 | 1999-01-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US6018181A (en) * | 1990-10-12 | 2000-01-25 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor and manufacturing method thereof |
| JP2004241528A (en) * | 2003-02-05 | 2004-08-26 | Ricoh Co Ltd | Organic semiconductor device and display element having it |
| US6975296B1 (en) | 1991-06-14 | 2005-12-13 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
| JP2007513512A (en) * | 2003-12-08 | 2007-05-24 | コミッサリヤ ア レネルジ アトミック | Method for molecular crosslinking of electronic components on polymer films |
| US7973905B2 (en) | 1996-11-26 | 2011-07-05 | Samsung Electronics Co., Ltd. | Liquid crystal displays using organic insulating material and manufacturing methods thereof |
| CN103943633A (en) * | 2014-03-06 | 2014-07-23 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method and display device thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61151614A (en) * | 1984-12-26 | 1986-07-10 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
| JPS61173286A (en) * | 1985-01-29 | 1986-08-04 | 株式会社東芝 | Display unit |
-
1988
- 1988-03-09 JP JP63055877A patent/JPH01229229A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61151614A (en) * | 1984-12-26 | 1986-07-10 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
| JPS61173286A (en) * | 1985-01-29 | 1986-08-04 | 株式会社東芝 | Display unit |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6018181A (en) * | 1990-10-12 | 2000-01-25 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor and manufacturing method thereof |
| US6975296B1 (en) | 1991-06-14 | 2005-12-13 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
| US5550390A (en) * | 1991-08-08 | 1996-08-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| US5859444A (en) * | 1991-08-08 | 1999-01-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US7973905B2 (en) | 1996-11-26 | 2011-07-05 | Samsung Electronics Co., Ltd. | Liquid crystal displays using organic insulating material and manufacturing methods thereof |
| JP2004241528A (en) * | 2003-02-05 | 2004-08-26 | Ricoh Co Ltd | Organic semiconductor device and display element having it |
| JP2007513512A (en) * | 2003-12-08 | 2007-05-24 | コミッサリヤ ア レネルジ アトミック | Method for molecular crosslinking of electronic components on polymer films |
| CN103943633A (en) * | 2014-03-06 | 2014-07-23 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method and display device thereof |
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