JPH01223557A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To assign a task without increasing the load of a general processor or a sub-processor by assigning the task to an optimum sub-processor at high speed by the unified processor when the task to be newly processed occurs. CONSTITUTION:The general processor 1, when a task to be newly processed occurs,outputs the priority level to a communication line 3. Respective sub- processors 21, 22,...,2n calculate the difference between the new priority level and the a value (for example, priority level of task) related to the task during the present execution and send the value of the largest difference and the identification number of the sub-processor onto the communication line 3. The general processor 1 knows the sub-processor to assign the new task by the information to return by the communication line 3. Thus,without increasing the load of the general processor 1 or the sub-processors 21,...,2n, the assignment of the new task can be realized with a simple constitution and at high speed.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a multiprocessor system in which a plurality of subprocessors are connected to one overall processor, and particularly when a new task is generated, This provides a method for allocating this new task to the optimal subprocessor.

<Prior Art> In a multiprocessor system in which at least one or more subprocessors are connected to a master processor, when a task to be executed occurs immediately, the master processor executes a task that is currently being executed by each subprocessor. Information about the task was retrieved from memory, and the subprocessor to which the new task should be assigned was determined by sequential comparison.

<Problems to be Solved by the Invention> However, the above-described task allocation method takes time and has the problem of increasing the load on the supervising processor.

The present invention has been made with this in mind, and it is an object of the present invention to realize an i&appropriate method for allocating a new task to a subprocessor when a new task to be processed occurs.

Means for Solving the Problems> The present invention, which has solved the above problems, communicates between the supervising processor and each subprocessor the priority level of a new task and the value (for example, priority level) related to the currently executing task. The specific configuration is as follows.

That is, in a multiprocessor system in which at least one or more subprocessors are connected to a central processor, a communication line that circulates from the central processor to all the subprocessors and returns is sterilized, and each of the subprocessors is provided with the information currently being executed. a holding means in which a value PLi related to the task is set; and a difference DF between the value PLi and the priority level Nl of the new task sent from the supervising processor.
i, and when the priority level of a new task is sent from the supervising processor, the largest difference DFi and the identification number IDi of the subprocessor that outputs this difference are always displayed on the communication line. A multiprocessor system characterized by transmitting data and returning it to the central processor
It is a system.

Operation> The multiprocessor system of the present invention operates as follows.

When a new task to be processed is generated, the supervising processor outputs its priority level to the communication line.

Each subprocessor calculates the difference between this new priority level and the value associated with the currently executing task (for example, the priority level of that task), and sends the value of the largest difference and the identification number of that subprocessor over the communication line. and send out.

The supervising processor learns the subprocessor to which a new task should be assigned based on the information returned via the communication line.

<Embodiment> FIG. 1 is a diagram showing the configuration of a multiprocessor system in which the present invention is implemented.

In FIG. 1, 1 is the general processor, 21°22, .
. . , 2n is a sub-processor, 3 is a sub-processor from the supervising processor 1 to the sub-processor 21 . Sub-processor 22. ...,
This is a communication line that circulates with the sub-processor 2n and returns to the central processor 1.

Each sub-processor 21.22. . . , 2n is an interface unit II that exchanges information with the communication line 3.

I2. ..., has In.

FIG. 2 shows a specific configuration of the interface section It in the sub-processor 21, and its operation will be explained.

In the interface part If, 41 is a register in which fia (for example, priority level) P L i related to the task currently being executed by this subprocessor 21 is set;
42 is a comparator for comparing various values generated within this interface section II; 43 is a comparator calculated by the comparator 42;
Priority level NL and value PL held in register 41
a register that holds the difference DFi from i; 44 is a register in which the identification number IDi of this subprocessor 21 is set;
Reference numeral 45 denotes a sending section that sends the information processed within this interface section Ii onto the communication line 3.

Now, the operation of the system of the present invention configured as described above will be explained next.

First, when a new task to be processed occurs, the supervisory processor 1 sends its priority level information in the form of 3-byte information.

In this 3-byte information, the first byte is the priority level NL of the newly processed task, the second byte is "0", and the third byte is the identification number IDO of the supervising processor 1 itself.

Such 3-byte information is sent to subprocessor 2 (i-1)
When it comes to this sub-processor 21, the first
Byte is at priority level NL, and subprocessor 2h (h
The third byte of the difference DFh (referred to as df) generated in <i) is the identification number IDh of the subprocessor 2h.

The processing of 3-byte information in this interface section It will be described in detail below.

For the priority level N L of the first byte, comparator 4
2, calculate (NL-PLi) and use the result as the difference DFi
It is held in the register 43 as .

Next, the comparator 42 checks the magnitude of the value DFi.

When DFi≦0, 3-byte information from communication line 3 (priority level NL, difference df (=DFh), identification number DFhl
is sent as is to the next sub-processor 2 (i+1).

When DFi>0, first, the priority level NL is output as the first byte.

Next, the comparator 42 calculates (DFi-df) from the given second byte information df (=DFh).

When (DFi-df)≦0, the information (difference df (=DFh>, m-specific number IDh+) given from the sub-processor 2 (i-1) is sent as is for both the second and third bytes.

That is, when DFi>0 and (D'FI-df)≦0, the 3-byte information sent onto the communication line 3 and given to the subprocessor 2(i+1) is (priority level N L , difference d
f (=DFh), identification number IDh).

When (DFi-df)>O, the value DF is used as the second byte.
The identification number IDi of this sub-processor 21 is sent with i as the third byte.

That is, when DFi>0 and (DFi-df)>O, the 3-byte information sent onto the communication line 3 and given to the subprocessor 2(i+1) is (priority level NL, difference df(
=DFi), identification number ID1).

By performing such operations, the 3-byte information is transmitted to all sub-processors 21, 22 . ..., it cycles through 2n.

The supervising processor 1 can know which sub-processor is currently executing the lowest level task based on the circulation result of this 3-byte information, and allocates a new task to this sub-processor.

In addition, in order to easily realize the comparator 42 etc. installed in the interface section 1i and to minimize the delay time due to processing,
Outputs the first byte of the 3-byte information starting with the LSB,
The second byte may be output from the MSB.

In addition, in the explanation of the embodiment, the priority of the task currently being executed in each subprocessor is used as the return criterion for allocating a new task, but the priority is not limited to this, and any value related to the currently executing task can be used. anything is fine.

Furthermore, although the size of the information issued from the central processor 1 is assumed to be 3 bytes, it is not limited to this number of bytes.

<Effects of the Invention> As described above, according to the system of the present invention, when a new task to be processed occurs, this task can be quickly assigned to the optimal sub-processor, and New task assignment can be realized with a simple configuration without increasing the load on the processor.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a multiprocessor system embodying the present invention, and FIG. 2 is a diagram showing the configuration of an interface section Ti within a sub-processor 21 in the system of the present invention. 1: Supervisory processor, 21, 22. ..., 2 j. ..., 2n; sub-processor, II, I2. ..., Ii. ..., In: interface section, 3: communication line, 41.43.44; register, 42: comparator, 45: sending section.

Claims (1)

[Claims] (1) In a multiprocessor system in which at least one or more subprocessors are connected to a central processor, a communication line is installed that circulates from the central processor to all the subprocessors and returns, and the current A holding means in which a value PLi related to the task being executed is set, and a difference DFi between the value PLi and the priority level NL of a new task sent from the supervising processor.
and when the priority level of a new task is sent from the supervising processor, the largest difference DFi and the identification number IDi of the subprocessor that outputs this difference are always sent on the communication line. A multiprocessor system characterized in that the data is sent back to the supervising processor.