JPH01221685A - Inspection equipment for semiconductor storage circuit device - Google Patents

Abstract

PURPOSE:To display a defective bit in conformity with a physical cell layout even when the physical cell layout is divided into plural sections in data bits by regarding an X-address side binary counter and a data-side binary counter as one binary counter and performing address conversion. CONSTITUTION:Pieces of address information of X-side and Y-side address generation parts 1 and 2 are converted by address conversion parts 3 and 4 into physical addresses, which are supplied to a storage circuit 5 to be inspected. Storage contents of cells corresponding to the addresses are outputted to data terminals D0 and D1. An inspection part 6 compares outputs D0 and D1 of the storage circuit 5 with expected values E0 and E1 and outputs defect signals F0 and F1 when they are different. Defect information on the storage circuit 5 is stored in a defect bit storage part 11 in bit correspondence relation. Binary counters 7, 8 and 9 generate outputs which specify an X address, a Y address, and a data terminal. An address conversion part 13 performs conversion while regarding the counters 8 and 9 as one counter and sends its output to an address conversion part 10 and a data selection part 12. A selection part 20 selects output terminals B0 and B1 of a storage part 11 and sends data to a display device.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a semiconductor memory circuit device testing device for testing functions such as writing and reading by applying error signals to the semiconductor memory circuit device. The present invention relates to a so-called defective pit map function that stores inspection results in a defective bit recording section for each memory cell and outputs the contents of the defective bit storage section to a display device to display a defective image.

[Prior Art] Conventionally, this type of testing apparatus for semiconductor memory circuit devices supplies address information generated in an address generation section to the memory circuit device under test, performs a read test on the memory circuit device under test, and checks the memory. It has a so-called defective bitmap function that stores inspection results on a cell-by-cell basis and displays a defective image on a display device.

Furthermore, the defective bitmap function has an address conversion unit that associates a logical image with a physical image based on cell coordinates.

On the other hand, in the circuit arrangement of conventional main semiconductor memory circuit devices, data bits are often divided into one group, and as shown in FIG.
1, and next to it D2, and so on.

FIG. 3 is a device block diagram of a conventional testing device for semiconductor memory circuit devices. For convenience of explanation, a small configuration model will be set below to explain the operation.

In FIG. 3, 1 is a 1-bit X address generator, 2 is a 1-bit X address generator, 3 is a 2-bit x 2-word X address converter, and 4 is a 2-bit x 2-word X address converter.
5 is a storage circuit device to be tested with 2 data bits x 4 words and 1 data bit is 2 bits in X and 2 bits in Y; 6 is a test unit;
7, 8゜9 are binary counters of X address, data bit, and X address, each consisting of 1 bit, 10
11 is 2 data bits) x 4 words, and the configuration of 1 data bit is
is a 2-bit defective bit storage section, and Y is a 2-bit defective bit storage section, and 12 is a data selection section with 1 output x 1 set made by two people.

First, when the write data of the memory circuit device to be tested (No. 5) has been determined, the read test is performed in one test until the test results are stored in the defective bit storage section (No. 11) for each storage cell. The operation will be explained step by step. 1
and 2 are address generation units for Y and X, respectively, which generate logical address information to be added to the storage circuit device under test in 5 in an arbitrary order, and input it to address conversion units for X and Y in 3 and 4. , 10 input terminals manually. 3 and 4 are Y and X address conversion units, respectively, which generate address information based on the address information from the address generation units 1 and 2 in accordance with the physical element arrangement of the storage circuit device to be tested β.

Now, Figure 4 is an image of the chip coordinates of the storage circuit device to be tested and the display coordinates on the display device:
] This is a positional relationship diagram for convenience.

In the figure, coordinate A is (0,0) and coordinate B is (1,0)
Next, C, D, E, F, G, H are (
2゜0), (3,O), (0,1), (L 1), (
2,1), (3,1).

Assume now that there is a storage circuit device to be tested which is logically arranged as a cell i device as shown in FIG. That is, the image seen from outside the package is, for example, information a at coordinate A, information IPtb at coordinate B, followed by C9D, E, F, and so on.
G, H to C, (1, e, f, g, h
Suppose that is written. Here, information a is x=0°Y=
If O is manually entered as an address, it can be read out to the Do data terminal. At this time, information 15c whose X and X addresses are common can also be read to the D1 data terminal. in this way,
Since b and d, e and g, and f and h share the same X and X addresses, they can be accessed at the same time, and a, b,
e, f to DO data terminal, C* d+ g
* h can be read to the DI data terminal. In the case of the cell arrangement as shown in FIG. 5, since the logical image and the physical image match, there is no need for address translation by the Y and X address translation units 3 and 4. Therefore, it is preferable that the conversion information of the address conversion section is set so that the manual data and the output data are the same as shown in Table 1.

Normally, the Y and X address conversion sections 3 and 4 are composed of memory circuit elements, and, for example, the address conversion section for an n-bit address generation section is composed of n bits x 2 words to the 0th power. The storage circuit device under test 5 includes an address conversion section 3
, 4 output read data to the inspection section 6 upon receiving the generated address conversion information and a control signal (not shown).

The inspection section 6 manually inputs the read data of the storage circuit device S to be inspected to one input and the expected value data (not shown) to the other input, and compares, for example, DO, EOLDl, and El, and determines whether the result is incorrect. If they match, FO or Fl is generated as a defect signal in association with each bit. When storing the test results, the selection section 10 operates to add address information from the address generation sections 1 and 2 to the defective bit storage section 11 in response to a cell signal from a control section (not shown).

The defective bit storage section 11 is divided into groups in units of data bits and is configured as shown in FIG. A defective bit is memorized by a control signal that does not exist.

By the way, in actual storage circuit devices to be tested, the structure of the decoder and wiring routes inside the device are generally not uniform due to access time and chip area.
In some cases, the cell arrangement is as shown in the figure. In such a case, coordinate A with respect to DO (or coordinate C with respect to DI) considering the physical image.

To access in the order of B (or D), E (or G), and F (or H), connect the X address generation section 1 at the top and the X address generation section 2 at the bottom, and then increment. operation, and then input the data shown in Table 2 to Y and X.
The address information from the address generating section 1.2 is transferred to the address converting sections 3 and 4 and added to the memory circuit device under test 5, while the address information from the address generating section 1.2 is transferred to the defective bit storage section via the address selecting section 10. Add to 11. If a mismatch activation signal is generated from the inspection section 6 during this series of operations, defective information is written to the corresponding address in the defective bit storage section 11. Therefore, the image of the address and data stored in the defective bit storage section 11 is as shown in FIG. That is, the information in Figure 7 $5a, b, c, d,
Defect information for e, f, and g is shown in a of Figure 8.
'Hb', C' + d'! e'
+ f ” + g°.

Next, operations from reading out the stored test results from the defective bit storage section 11 to outputting defective bit information to a display device (not shown) will be explained in order. Numerals 7, 8, and 9 are binary counters, respectively, which generate a read address for the defective bit storage section 11 based on a CP signal from a control section (not shown). Note that the binary counter 7 corresponds in hit configuration to the X address generation section 1, and the binary counter 9 corresponds in bit configuration to the X address generation section 2. When reading the test results, the address selection section 10 operates so that the Y and X address information of the binary counter 7.9 is added to the defective bit storage section 11 by a cell signal from a control section (not shown). The data selection section 12 selectively selects the read information of the defective bit storage section 11 using the output signal DO of the binary counter 8, and displays the coordinates A, B, C, D, etc. on a display device (not shown).
E, F.

Serial signal B of l bit width in the order of G, H,
Output as S. That is, it is possible to display the arrangement image as shown in FIG. 7.

[Problems to be Solved by the Invention] In the case of the storage circuit device under test 5 described so far, the physical cell arrangement between data bits is divided into one group in units of data bits, as shown in FIG. , a topological transformation of X and/or Y was performed within the data bits. However, in a case as shown in FIG. 11, where the physical cell arrangement is divided into a plurality of parts within one data bit, and the data bits are also arranged separately, the X Address 5 and X
There was a problem that the means for converting address 5 could not support display.

[Differences between the invention and the prior art] The conventional testing device for a semiconductor memory circuit device described above only had a Y address translation section and an X address translation section, whereas the semiconductor memory circuit device of the present invention has When reading the defective bit storage section and outputting it to the display device, the device inspection device treats the binary counter on the X address side and the binary counter on the data side as one binary counter, and compares them with the address conversion section. are arranged in pairs, and the X address of conversion 5 is input to the defective bit storage section through the address selection section, and the D data of conversion 5 is input as a selection control signal of the data selection section to select data bits. , even if the physical cell arrangement is divided into a plurality of parts within the data bit, there is a difference that can be easily displayed.

[Means for Solving the Problems] The testing device for a semiconductor memory circuit device of the present invention reads data from a defective bit storage section and outputs it to a display device as a 1-bit width serial signal, by checking the binary data on the X address side. The counter, the binary counter on the data side, the binary counter on the X address side, and the binary counter on the data side are treated as one binary counter. An address selection section selectively supplies data to the defective bit storage section, and read data from the defective bit storage section is selectively selected based on the weight information of the data selection bit in the converted address of the address conversion section, and is converted into a 1-bit wide serial signal. and a data selection section that outputs the data to the display device as a display device.

[Embodiment] First Embodiment FIG. 1 is a block diagram of an apparatus showing a first embodiment of the present invention. For convenience of explanation, a small configuration model will be set below to explain the operation.

In the figure, 1 is a 1-bit X address generation section, 2
is a 1-bit X address generator, and 3 is a 2-bit)
4 is an X address conversion unit with a word configuration, 4 is an X address conversion unit with a 2 bit x 2 word configuration, and 5 is a 2 data bit x 4
It is a word and the configuration of 1 data bit is 2 bits for X and 2 bits for Y.
is a 2-bit memory circuit device to be tested, 6 is a testing section, and ? ,
8. 9 is a binary counter of Y address and data bit X is 2
Bit, Y is a 2-bit defective bit storage section, 12 is a data selection section with 2 manual outputs x 1 set, 13 is a binary counter on the X address side and a binary counter on the data side.
This is an RX address converter that is regarded as one binary counter.

Now, a case as shown in FIG. 6 in which the physical cell arrangement is divided into a plurality of parts within a data bit will be explained.

First, when the write data of the storage circuit device under test 5 has been determined, a read test is performed and the test results are stored in the defective bit storage section 11 for each memory cell. Since the operating procedure is the same as that of the conventional technique, the explanation will be omitted. However, in this case, Table 3 conversion table will be used for convenience. Therefore, the image of the address and data stored in the defective bit storage section 11 is as shown in FIG. 9, as shown in the conventional example.

Next, the operation from reading out the stored test results from the defective bit storage section 11 to outputting defective bit information to a display device (not shown) will be described. Numerals 7, 8, and 9 are binary counters, respectively, which generate a read address for the defective bit storage section 11 based on a CP signal from a control section (not shown). Note that the binary counter 7 corresponds in bit configuration to the Y address generation section 1, and the binary counter 9 corresponds in bit configuration to the X address generation section 2.

By the way, when the semiconductor memory circuit device testing device of this embodiment reads out the defective bit storage section and outputs it to the display device, it combines the binary counter on the X address side and the binary counter on the data side as one binary counter. For example, these and the address converter are configured as a pair, and the converted 50X address is passed through the address selector into the defective bit storage section, and the D data of the converter 5 is manually input as a selection control signal for the data selector. A selection of data bits can be made. Therefore, the conversion information in Table 3 is expanded to the RX address conversion section 13 and the defective bit storage section 1 is expanded.
1 is read and the data string appearing at the output of the data selection section 12 is verified.

Binary counter? , 8. When the content of 9 is "0", according to the conversion information in Table 3, the data information in the output of the RX address converter 13 is "1P", the X address information is "1P", and the Y address is "0". It is.

Therefore, the X address information is "1" in the defective bit storage unit 11 that has previously taken in the defective information as shown in FIG.
Then, °'0'' is added to the Y address, and the read data b' and d9 appear at BO and 81, respectively, and are input to the data selection section 12.

Then, the data selection section 12 selects and outputs Bl, that is, d', based on the data information t*'lvs output from the RX address conversion section 13. Similarly, a', b''.

Since c', h', e', f'+g' are output, it is output as a 1-bit wide serial signal as if the data had been written in the defective bit storage unit 11 as shown in Figure 6. . That is, it is possible to display the layout image as shown in FIG. 6.

FIG. 2 is a block diagram of an apparatus showing a second embodiment of the present invention. For convenience of explanation, a small configuration model will be set below to explain the operation. In the first embodiment and the conventional example, address information is generated by replacing the address information with a physical address when testing the storage circuit device 5 to be tested, whereas in the second embodiment, the storage circuit device 5 to be tested is generated by replacing the address information with a physical address. This is an example in which address information is added as a logical address when inspecting, and coordinates are converted to a physical image when reading out the defective bit storage section 5.

In Fig. 2, 1 is an X address generation section with a 1-bit configuration, 2 is an
A memory circuit device to be tested in which Y is 2 bits, 6 is a testing section, and 7. 8. 9 each has an X address, a data bit, and an X address binary counter, each consisting of 1 bit; 10, 2 manual outputs x 2 sets of address selectors; and 11, 2 data bits x 4 words, each consisting of 1 data bit. Defective bit storage section with 2 bits for X and 2 bits for Y, 1
2 is a 2-manpower 1 output x 1 silk data selection section, 13 is an RX address conversion section that considers the binary counter on the X address side and the binary counter on the data side as one binary counter, and 14 is the RYX address conversion section. .

Now, a case as shown in FIG. 6 in which the physical cell arrangement is divided into a plurality of parts within a data bit will be explained.

First, a read test is performed on the storage circuit device 5 to be tested, and whether the test results are good or bad for each memory cell is stored in the defective bit storage section 1.
In the read operation when storing in the defective bit storage unit 11, since there is no X address conversion unit or X address conversion unit, the image of the address and data stored in the defective bit storage unit 11 is The situation shown in FIG. 9 is as shown in the conventional example.

Next, the stored test results are expanded into the conversion information in Table 1 in the RX address conversion unit 13, and the RYX address conversion unit 1
When the conversion information with a 1:1 ratio of 4 inputs and outputs is developed and read from the defective hit storage section 11, the same operation as in the first embodiment is performed.

Therefore, the arrangement image shown in FIG. 6 can be displayed as is.

What do Figures 1 and 2 mean? , 8. 9 each
Data binary counter 8
is positioned above the X address binary counter 9, but the X address binary counter 9 is positioned above the data binary counter 8, and the corresponding binary counter 13 on the X address side and binary counter on the data side RX that considers and as one binary counter
It is clear that the same effect can be obtained even if it is configured with an address translation section.

[Effects of the Invention] As explained above, the semiconductor memory circuit device testing device of the present invention reads the defective bit storage section and outputs it to the display device? At this time, the binary counter on the X address side and the binary counter on the data side are combined as one binary counter, and they are configured to be paired with the address conversion section, and the X address of conversion 5 is is input to the defective bit storage unit through the address selection unit, and the D data of conversion 5 is input as a selection control signal to the data selection unit to select the data bit, so the physical cell arrangement is divided into multiple parts within the data bit. It has the effect that it can be easily displayed even when it is arranged.

Table 2 Table 2 expression

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention,
FIG. 2 is a block diagram showing the configuration of the second embodiment, FIG. 3 is a block diagram showing the configuration of a conventional semiconductor memory circuit device testing device, and FIG. 4 is a coordinate and display of the chip of the storage circuit device to be tested. Figures 5, 6, and 7 are positional relationship diagrams for imagining the display coordinates on the device, and Figure 8 is a layout diagram showing the physical layout of the cells of the storage circuit device to be tested. FIG. 9 is a state diagram showing the storage state stored in the defective bit storage section, No. 10.
11A and 11B are layout diagrams showing the physical layout of data bits in the storage circuit device under test. 1...X address generation unit, 2...X address generation unit, 3...X address conversion unit, 4...X address conversion unit, 5... Memory circuit device to be tested, 6...inspection section, 7, 8. 9...Binary counter, 10...
Address selection unit, 11...Failure bit storage unit, 12...Data selection unit, 13...RX7) Response conversion unit. Patent Applicant: NEC Corporation Representative, Patent Attorney Kiyoshi Kuwai - , il

Claims (1)

[Claims] A semiconductor memory circuit device is inspected by applying an electrical signal, data regarding a defective bit is held in a defective bit storage section, and data from the defective bit storage section is read out to generate a 1-bit width serial signal. In a testing device for a semiconductor memory circuit device that outputs data to a display device, a binary counter on the X address side, a binary counter on the data side, and a binary counter on the X address side and a binary counter on the data side are regarded as one binary counter. an address selection section that selectively supplies the weight information of the X address among the addresses converted by the address conversion section to the defective bit storage section; A testing device for a semiconductor memory circuit device, comprising a data selection section that selectively selects data based on weight information of data selection bits and outputs the selected data to a display device as a 1-bit width serial signal.