JPH01220850A - Electrode structure of semiconductor device - Google Patents
Electrode structure of semiconductor deviceInfo
- Publication number
- JPH01220850A JPH01220850A JP63047291A JP4729188A JPH01220850A JP H01220850 A JPH01220850 A JP H01220850A JP 63047291 A JP63047291 A JP 63047291A JP 4729188 A JP4729188 A JP 4729188A JP H01220850 A JPH01220850 A JP H01220850A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- insulating layer
- wire
- film
- metal electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 42
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 29
- 230000001681 protective effect Effects 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 11
- 238000002161 passivation Methods 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 229910052802 copper Inorganic materials 0.000 abstract description 9
- 239000010949 copper Substances 0.000 abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 5
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 9
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 6
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- -1 phospho Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
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- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
(イ)産業上の利用分野
この発明はワイヤボンディングされる単導体装置の電極
部の構造に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to the structure of an electrode portion of a single conductor device to be wire bonded.
(ロ)従来の技術
従来ICチップのような半導体装置の電極部においては
、半導体基板上にP S G (phospho 5i
licate glass)やB P S G (bo
ro phospho silicateglass)
のようなCV D (chemical vapor
deposition)絶縁膜または熱酸化シリコン膜
から成る絶縁層を介してアルミニウムまたはアルミニウ
ムシリコンから成る金属電極が形成され、その金属電極
にAuワイヤを用いてワイヤボンディングを行うように
している。(b) Conventional technology Conventionally, in the electrode part of a semiconductor device such as an IC chip, PSG (phospho 5i) is used on a semiconductor substrate.
licate glass) and B P S G (bo
ro phospho silicate glass)
CV D (chemical vapor) like
A metal electrode made of aluminum or aluminum silicon is formed through an insulating layer made of an insulating film or a thermally oxidized silicon film, and wire bonding is performed using an Au wire to the metal electrode.
(ハ)発明が解決しようとする課題
Auワイヤを用いたワイヤボンディングにおいては、A
uが柔らかく延性に優れているため、金属電極の下部に
存在する絶縁層は、PSGやBPSGというような機械
的に脆い層であっても、ワイヤボンディングによるクラ
ックの発生は見られなかった。しかしながら、銅ワイヤ
を用いてワイヤボンディングする場合には、銅ワイヤは
Auワイヤに比べて硬く、また延性に劣るため、ワイヤ
ボンディング時に電極下部の絶縁層がクラックを生じた
り、ワイヤ先端のポールが金属電極中に入り込んで下部
絶縁層にクラックを発生させるという問題があった。(c) Problems to be solved by the invention In wire bonding using Au wire, A
Since u is soft and has excellent ductility, no cracks were observed in the insulating layer under the metal electrode due to wire bonding, even if it was a mechanically fragile layer such as PSG or BPSG. However, when wire bonding is performed using copper wire, copper wire is harder and less ductile than Au wire, so the insulating layer under the electrode may crack during wire bonding, or the pole at the tip of the wire may be made of metal. There was a problem that it penetrated into the electrode and caused cracks in the lower insulating layer.
この発明はこのような事情を考慮してなされたもので、
銅ワイヤを用いてワイヤボンディングを行っても、電極
下部の絶縁層がクラックを発生することのない半導体装
置の電極構造を提供するしのである。This invention was made in consideration of these circumstances,
The present invention provides an electrode structure for a semiconductor device in which the insulating layer under the electrode does not crack even when wire bonding is performed using copper wire.
(ニ)課題を解決するための手段
この発明は、半導体基板上に絶縁層を介して設けられた
金属電極に銅ワイヤを用いてボールボンディング法によ
りワイヤボンディングする電極構造において、ワイヤボ
ンデング時に加わる外力から絶縁層を保護する保護膜を
金属電極と絶縁層との間に介在させたことを特徴とする
半導体装置の電匪溝造である。保護膜は厚さ0.05〜
0.6μmのチッ化シリコン膜または厚さ0.1〜0.
6μmのTi−W膜であることが好ましい。(d) Means for Solving the Problems This invention provides an electrode structure in which a metal electrode provided on a semiconductor substrate via an insulating layer is wire-bonded by a ball bonding method using a copper wire. This is a semiconductor device characterized by interposing a protective film between a metal electrode and an insulating layer to protect the insulating layer from external forces. The thickness of the protective film is 0.05~
Silicon nitride film of 0.6 μm or thickness of 0.1-0.
Preferably, it is a 6 μm Ti-W film.
更にこの発明は、半導体基板上に絶縁層を介して設けら
れた金属電極に銅ワイヤを用いてボールボンディング法
によりワイヤボンディングする電極構造において、ワイ
ヤボンディング時の金属電極中に金属電極よりも硬度の
高い金属を含有させ、金属電極の硬度を増大させたこと
を特徴とする半導体装置の電極構造である。アルミニウ
ムやアルミニウム・シリコンの金属電極には、銅を含有
さ仕ることか好ましい。Furthermore, the present invention provides an electrode structure in which a copper wire is wire-bonded to a metal electrode provided on a semiconductor substrate through an insulating layer by a ball bonding method. This is an electrode structure for a semiconductor device characterized by containing a high amount of metal and increasing the hardness of the metal electrode. It is preferable that aluminum or aluminum-silicon metal electrodes contain copper.
またこの発明は、半導体基板上に絶縁層を介して設けら
れf二金属電極に銅ワイヤを用いてホールホンディング
法によりワイヤボンディングする電極構造において、金
属電極の変形を抑制する保護膜を銅ワイヤ先端のポール
部と金属電極との接合面に部分的に介在さ仕たことを特
徴とする半導体装置の電極構造である。この保護膜とし
ては電極近傍のパッシベーション膜等の絶縁層を金属電
極上に延出して形成しても良いし、Ti−W膜またはW
膜を別に設けるようにしてもよい。The present invention also provides an electrode structure in which a copper wire is used as a metal electrode provided on a semiconductor substrate via an insulating layer and wire bonded by a hole bonding method. This is an electrode structure for a semiconductor device, characterized in that it is partially interposed at the joint surface between the pole portion at the tip and the metal electrode. This protective film may be formed by extending an insulating layer such as a passivation film near the electrode onto the metal electrode, or a Ti-W film or W film.
A separate membrane may be provided.
(ホ)作用
金属電極と絶縁層との間に保護膜を設けた場合には、ワ
イヤボンディング時に金属電極に加わる外力が絶縁層ま
で伝達されないので、絶縁層が機械的にもろい層であっ
てもクラックを生じることがほとんど無い。また、金属
電極中に金属電極よりも硬度の高い金属を含有させた場
合には、金属電極の硬度が増大しワイヤボンディング時
に金属電極が変形することがないので、その下部の絶縁
層に加えられるワイヤボンディング時の外力が金属電極
でさえぎられて絶縁層のクラックの発生が防止される。(e) If a protective film is provided between the working metal electrode and the insulating layer, the external force applied to the metal electrode during wire bonding will not be transmitted to the insulating layer, even if the insulating layer is mechanically fragile. Almost no cracks occur. In addition, when a metal with higher hardness than the metal electrode is contained in the metal electrode, the hardness of the metal electrode increases and the metal electrode is not deformed during wire bonding. External force during wire bonding is blocked by the metal electrode, preventing cracks from occurring in the insulating layer.
更に、ワイヤ先端のポール部と金属電極との接合面に部
分的に保護膜を設けた場合には、ワイヤボンディング時
の衝撃が保護膜によっ一緩和されワ、イヤ先端のホール
部が保護膜で支持され金属電極内に入り込むことが抑制
されるので金属電極下部の絶縁層のクラックの発生率が
低減される。Furthermore, if a protective film is partially provided on the bonding surface between the pole part at the tip of the wire and the metal electrode, the impact during wire bonding is alleviated by the protective film, and the hole part at the tip of the ear is covered with the protective film. Since the metal electrode is supported by the metal electrode and is prevented from entering the metal electrode, the occurrence rate of cracks in the insulating layer under the metal electrode is reduced.
(へ)実施例
以下、図面に示す実施例に基づいて、この発明を詳述す
る。これによって、この発明が限定されるものではない
。(f) Examples The present invention will now be described in detail based on examples shown in the drawings. This invention is not limited by this.
第1図に示す実施例において、lはシリコン基板、2は
基tit上に形成された厚さ0.7μmのLOG OS
(local oxidation of 5ili
con)酸化膜、3はLOGOS酸化膜2の上に形成さ
れた厚さ0.5pmのPSG、BPSG又は5iftか
ら成る絶縁層、4はアルミ・シリコンを用いて形成され
た厚さ1.0μmの電極、5は電極4と絶縁層3との間
に保護膜としてCVD法で形成された厚さ0.05〜0
6μmのチッ化シリコン膜、6は厚さ0.6μmのバッ
ソベーンヨン膜、7は電極4にボールボンディング法に
よってワイヤボンディングされた直径30μmの銅ワイ
ヤである。In the embodiment shown in FIG. 1, l is a silicon substrate, and 2 is a 0.7 μm thick LOG OS formed on a substrate.
(local oxidation of 5ili
con) oxide film, 3 is an insulating layer made of PSG, BPSG, or 5ift with a thickness of 0.5 pm formed on the LOGOS oxide film 2, 4 is an insulating layer with a thickness of 1.0 μm formed using aluminum silicon. The electrode 5 is formed as a protective film between the electrode 4 and the insulating layer 3 by the CVD method and has a thickness of 0.05 to 0.
A 6 μm silicon nitride film, 6 a 0.6 μm thick basso venillon film, and 7 a 30 μm diameter copper wire wire-bonded to the electrode 4 by ball bonding.
第2図に示す実施例において、シリコン基板11上に形
成された厚さ0.7μmのLOGOS酸化膜12上に、
CVD法で7さ0.05〜fl 、 hmのチッ化シリ
コン膜15が保護膜として形成される。その上に厚さ1
.0μmの電極14が形成され、更に、厚さ0.5μm
のPSGSBPSG又は5iftから成る絶縁層13及
び厚さ0.6μmのパッシベーション膜16が形成され
、電極r4の上面に銅ワイヤ17がボールボンディング
法によりワイヤボンディングされる。In the embodiment shown in FIG. 2, on a LOGOS oxide film 12 with a thickness of 0.7 μm formed on a silicon substrate 11,
A silicon nitride film 15 with a thickness of 0.05-fl, hm is formed as a protective film by the CVD method. On top of that, the thickness is 1
.. An electrode 14 with a thickness of 0 μm is formed, and an electrode 14 with a thickness of 0.5 μm is formed.
An insulating layer 13 made of PSGSBPSG or 5ift and a passivation film 16 with a thickness of 0.6 μm are formed, and a copper wire 17 is wire-bonded to the upper surface of the electrode r4 by a ball bonding method.
第3図に示す実施例において、シリコン基板21上に厚
さ0.1#Imのり、0COS酸化膜22が形成され、
更にその上に厚さ0.5μmのPSGSBPSG又はS
in、から成る絶縁層23が形成され、その上に保護膜
として厚さ0.1〜0.6μm/J)Ti−W膜25が
形成される。Ti−’vV膜25の真上にアルミニウム
・シリコンから成る厚さ1.0μmの電極24が形成さ
れ、電極24の上部以外は厚さ0.6μmのパッシベー
ション膜26によって被覆される。In the embodiment shown in FIG. 3, a 0.1 #Im thick 0COS oxide film 22 is formed on a silicon substrate 21,
Furthermore, on top of that, 0.5 μm thick PSGSBPSG or S
An insulating layer 23 consisting of In, is formed, and a Ti--W film 25 with a thickness of 0.1 to 0.6 μm/J) is formed thereon as a protective film. An electrode 24 made of aluminum silicon and having a thickness of 1.0 μm is formed directly above the Ti-'vV film 25, and the area other than the upper part of the electrode 24 is covered with a passivation film 26 having a thickness of 0.6 μm.
そして、電極24の上面には直径30umの銅ワイヤ2
7がボールボンディング法によってワイヤボンディング
される。A copper wire 2 with a diameter of 30 um is placed on the upper surface of the electrode 24.
7 is wire-bonded by the ball bonding method.
第4図に示す実施例においてはシリコン基板31の上に
厚さ0.1μrnのLOGOS酸化膜32が形成され、
その上に保護膜として厚さ0.1〜0,6μmのTi−
W膜35とP S G、B P S G又はSiO□か
ら成る厚さ0.5μmの絶縁層33が形成される。In the embodiment shown in FIG. 4, a LOGOS oxide film 32 with a thickness of 0.1 μrn is formed on a silicon substrate 31.
On top of that, as a protective film, a Ti-
A 0.5 μm thick insulating layer 33 made of W film 35 and PSG, BPSG, or SiO□ is formed.
そしてT i−W膜35の真上にはアルミニウム・シリ
コンから成る厚さl、0μmの電極34が形成され、l
l134以外には厚さ0.6μmのパッシベーション膜
36が形成される。そして、電極34の上面には直径3
0μmの銅ワイヤがボールボンディング法によりワイヤ
ボンディングされる。Immediately above the Ti-W film 35, an electrode 34 made of aluminum silicon and having a thickness l and 0 μm is formed.
A passivation film 36 with a thickness of 0.6 μm is formed in areas other than 1134. The upper surface of the electrode 34 has a diameter of 3 mm.
A 0 μm copper wire is wire-bonded by a ball bonding method.
第5図に示す実施例においては、シリコン基板4!の上
に厚さ0.1μmのLOGO9酸化膜42が形成され、
更にその上に厚さ0.5μmのPSG、BPSGまたは
5iOzから成る絶縁層43が形成され、その上面にア
ルミニウム・シリコンに銅を含有さけた金属(A I
−1%5i−2%Cu)から成る′@睡44が形成され
、電極44の上面を残して厚さ06μmのパッシベーシ
ョン膜46が形成される。そして、′電極44の上面に
は直径30μmの銅ワイヤ47の銅ボール45がボール
ボンディング法によってワイヤボンディングされる。In the embodiment shown in FIG. 5, the silicon substrate 4! A LOGO9 oxide film 42 with a thickness of 0.1 μm is formed on the
Furthermore, an insulating layer 43 made of PSG, BPSG, or 5iOz with a thickness of 0.5 μm is formed on the insulating layer 43, and a metal (A I
-1%5i-2%Cu) is formed, and a passivation film 46 with a thickness of 06 μm is formed leaving the upper surface of the electrode 44. Then, a copper ball 45 of a copper wire 47 having a diameter of 30 μm is wire-bonded to the upper surface of the 'electrode 44 by a ball bonding method.
第6図に示す実施例においては、シリコン基板51の上
に厚さ0.7μmのLOGOS酸化膜52が形成され、
更にその上に厚さ0,5μmのPSG、B’PSG又は
SiOxから成る絶縁層53が形成される。その上に厚
さ1 、04mのアルミニウム・シリコンから成る電極
54が形成され、その上から厚さ0.6μmのパッシベ
ーション膜56か形成される。In the embodiment shown in FIG. 6, a LOGOS oxide film 52 with a thickness of 0.7 μm is formed on a silicon substrate 51.
Furthermore, an insulating layer 53 made of PSG, B'PSG or SiOx with a thickness of 0.5 μm is formed thereon. An electrode 54 made of aluminum and silicon with a thickness of 1.04 m is formed thereon, and a passivation film 56 with a thickness of 0.6 μm is formed thereon.
そして、パッシベーション膜56は、電極54の上部周
辺を覆って形成されるので、直径30μmの銅ワイヤ5
7がワイヤボンデングされるきき、つまり銅ボール55
が電極54に接合される時、パッシベーション膜56の
一部が銅ボール55と電極54の間に部分的に介在する
ことになる第7図に示す実施例においては、シリコン基
板61の上に厚さL1μmのLOGOS酸化膜62が形
成され、更にその上に厚さ0.5μmのPSG、BPS
GまたはS i O2から伎る絶縁層63が形成される
。さらに、その絶縁層63の上にアルミニウム・シリ゛
コンから成る厚さ1.0μmの電極64か形成され、更
にその上から電極64の上面を残しテ厚さO,lBzm
のパッシベーション膜66が形成される。そして、電極
64の周縁上部には保護膜68が形成され、電極64の
上面に直径30μmの銅ワイヤ67がワイヤボンディン
グされると、銅ボール65は保護膜68を部分的に介し
て電極64の上面に接合されることになる。Since the passivation film 56 is formed to cover the upper periphery of the electrode 54, the copper wire 56 with a diameter of 30 μm
7 is wire bonded, that is, the copper ball 55
In the embodiment shown in FIG. 7, a portion of the passivation film 56 is partially interposed between the copper ball 55 and the electrode 54 when the copper ball 55 is bonded to the electrode 54. A LOGOS oxide film 62 with a thickness of L1 μm is formed, and PSG and BPS with a thickness of 0.5 μm are further formed on it.
An insulating layer 63 made of G or SiO2 is formed. Further, an electrode 64 made of aluminum silicon and having a thickness of 1.0 μm is formed on the insulating layer 63, and then an electrode 64 with a thickness of O, 1Bzm is formed on top of the insulating layer 63, leaving the upper surface of the electrode 64.
A passivation film 66 is formed. A protective film 68 is formed on the upper peripheral edge of the electrode 64, and when a copper wire 67 with a diameter of 30 μm is wire-bonded to the upper surface of the electrode 64, the copper ball 65 is attached to the electrode 64 through the protective film 68. It will be joined to the top surface.
第8図は第6図及び第7図の要部上面図であり、it極
と銅ボールとの間に部分的に介在するパッシベーション
膜56または保護膜68の形状例を示すものである。な
お、電極4,14,24.34゜54.64にはA1−
1%Siを使用した。FIG. 8 is a top view of the essential parts of FIGS. 6 and 7, and shows an example of the shape of the passivation film 56 or the protective film 68 partially interposed between the IT electrode and the copper ball. In addition, A1-
1% Si was used.
第1〜4図に示す実施例においては、電極と電極下部の
絶縁層との間に保護膜を設けたため、ワイヤボンディン
グ時に電極に加わる外力が絶縁層まで伝達され、絶縁層
が機械的にもろい層であってらクラックを生じることが
ほとんど無い。まf六第5図に示す実施例によれば、電
極中jこ電圧よjンら硬度の高い金属を含有させたので
、電極の硬度が増大しワイヤボンディング時に電極か変
形す4ことがなく、その下部の絶縁層に加えられるワイ
ヤボンディング時の外力が金属電極でさえぎられて電極
下部の絶縁層のクラックの発生が防止される。更に、第
6〜7図に示す実施例によれば、ワイヤ先端のボール部
と電極との接合面に部分的に保護膜を設けたため、ワイ
ヤボンディング時の衝撃が保護膜によって緩和され、ワ
イヤ先端のボール部が保護膜で支持され電極内に入り込
むことが抑制されろことにより、電極下部の絶縁層のク
ラックの発生率が低減される。In the embodiments shown in Figures 1 to 4, a protective film is provided between the electrode and the insulating layer below the electrode, so that the external force applied to the electrode during wire bonding is transmitted to the insulating layer, making the insulating layer mechanically fragile. Although it is a layer, cracks hardly occur. According to the embodiment shown in FIG. 5, since the electrode contains a metal with high hardness, including the voltage, the hardness of the electrode increases and the electrode does not deform during wire bonding. The external force applied to the insulating layer below the wire bonding is blocked by the metal electrode, thereby preventing the occurrence of cracks in the insulating layer below the electrode. Furthermore, according to the embodiment shown in FIGS. 6 and 7, since a protective film is partially provided on the bonding surface between the ball part of the wire tip and the electrode, the impact during wire bonding is alleviated by the protective film, and the wire tip The ball portion is supported by the protective film and is prevented from penetrating into the electrode, thereby reducing the incidence of cracks in the insulating layer below the electrode.
これらの実施例の電極構造におけるクラック発生の有無
を従来例と比較したが、従来の電極構造においてはクラ
ック発生率が70〜90%であるのに対し、これらの実
施例のクラック発生率はほとんど0%であることが確認
された。なお、クラック発生有無の確認は、ワイヤボン
ディングされた銅ワイヤを硝酸で除去した後、NaOH
水溶液で電極をエツチングし、更に、絶縁層のクラック
直下の基vL(シリコン単結晶)をエツチングし、クラ
ックを顕在化して、目視によってクラックの存在を確認
する方法を用いた。The presence or absence of cracks in the electrode structures of these examples was compared with conventional examples, and while in the conventional electrode structures the crack generation rate was 70 to 90%, the crack generation rate in these examples was almost 70% to 90%. It was confirmed that it was 0%. To check whether cracks have occurred, remove the wire-bonded copper wire with nitric acid, and then remove it with NaOH.
A method was used in which the electrodes were etched with an aqueous solution, and then the base VL (silicon single crystal) directly under the cracks in the insulating layer was etched to expose the cracks, and the presence of the cracks was visually confirmed.
(ト)発明の効果
この発明によれば、電極下部の絶縁層にクラックが発生
することがなく、歩留りの高い銅ワイヤボンディングが
可能となり、安価で信頼性の高い半導体装置を得ること
ができる。(G) Effects of the Invention According to the present invention, cracks do not occur in the insulating layer below the electrode, copper wire bonding can be performed with a high yield, and an inexpensive and highly reliable semiconductor device can be obtained.
第1図ないし第7図はこの発明の実施例を示す縦断面図
、第8図は第6図及び第7図に示す実施例の要部上面図
である。
1、II、21,31,41,51.61・・・・・・
基板、
2、+2.22.32,42.52.62・・・・・・
LOGOS酸化膜、
3.13,23,33,43.53.63・・・・・・
絶縁層、
6.16,26,36,46,56.66・・・・・・
パッシベーション膜、
4、+4.24,34.44,54.64・・・・・・
電極、
7.1?、27.37.47.57.67・・・・・・
銅ワイヤ、
5.15・・・・・・チッ化シリコン膜、25 、 3
5−−−−= T i −WM。
68・・・・・・保護膜。
第 1 図
第 3 図
! 4 図
第 5 図1 to 7 are longitudinal cross-sectional views showing embodiments of the present invention, and FIG. 8 is a top view of essential parts of the embodiment shown in FIGS. 6 and 7. 1, II, 21, 31, 41, 51.61...
Board, 2, +2.22.32, 42.52.62...
LOGOS oxide film, 3.13, 23, 33, 43.53.63...
Insulating layer, 6.16, 26, 36, 46, 56.66...
Passivation film, 4, +4.24, 34.44, 54.64...
Electrode, 7.1? , 27.37.47.57.67...
Copper wire, 5.15...Silicon nitride film, 25, 3
5----= T i -WM. 68...Protective film. Figure 1 Figure 3! Figure 4 Figure 5
Claims (1)
に銅ワイヤを用いてボールボンディング法によりワイヤ
ボンディングする電極構造において、ワイヤボンデング
時に加わる外力から絶縁層を保護する保護膜を金属電極
と絶縁層との間に介在させたことを特徴とする半導体装
置の電極構造。 2、半導体基板上に絶縁層を介して設けられた金属電極
に銅ワイヤを用いてボールボンディング法によりワイヤ
ボンディングする電極構造において、ワイヤボンディン
グ時の金属電極中に金属電極よりも硬度の高い金属を含
有させ、金属電極の硬度を増大させたことを特徴とする
半導体装置の電極構造。 3、半導体基板上に絶縁層を介して設けられた金属電極
に銅ワイヤを用いてボールボンディング法によりワイヤ
ボンディングする電極構造において、金属電極の変形を
抑制する保護膜を銅ワイヤ先端のボール部と金属電極と
の接合面に部分的に介在させたことを特徴とする半導体
装置の電極構造。[Claims] 1. In an electrode structure in which copper wire is wire-bonded to a metal electrode provided on a semiconductor substrate via an insulating layer by a ball bonding method, the insulating layer is protected from external force applied during wire bonding. An electrode structure for a semiconductor device, characterized in that a protective film is interposed between a metal electrode and an insulating layer. 2. In an electrode structure in which a copper wire is wire-bonded to a metal electrode provided on a semiconductor substrate through an insulating layer by a ball bonding method, a metal with a higher hardness than the metal electrode is used in the metal electrode during wire bonding. An electrode structure for a semiconductor device, characterized in that the hardness of the metal electrode is increased by containing the metal electrode. 3. In an electrode structure in which a copper wire is wire-bonded to a metal electrode provided on a semiconductor substrate through an insulating layer by a ball bonding method, a protective film that suppresses deformation of the metal electrode is attached to the ball portion of the tip of the copper wire. An electrode structure for a semiconductor device, characterized in that the electrode structure is partially interposed at a bonding surface with a metal electrode.
Priority Applications (1)
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JP63047291A JP2527457B2 (en) | 1988-02-29 | 1988-02-29 | Electrode structure of semiconductor device |
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JP63047291A JP2527457B2 (en) | 1988-02-29 | 1988-02-29 | Electrode structure of semiconductor device |
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Publication Number | Publication Date |
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JPH01220850A true JPH01220850A (en) | 1989-09-04 |
JP2527457B2 JP2527457B2 (en) | 1996-08-21 |
Family
ID=12771180
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JP63047291A Expired - Fee Related JP2527457B2 (en) | 1988-02-29 | 1988-02-29 | Electrode structure of semiconductor device |
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Cited By (8)
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DE4019848A1 (en) * | 1989-10-17 | 1991-04-25 | Mitsubishi Electric Corp | SEMICONDUCTOR DEVICE WITH A CONNECTING SURFACE HAVING A BUFFER LAYER |
DE4201792A1 (en) * | 1991-01-29 | 1992-08-06 | Mitsubishi Electric Corp | Improved corrosion-resistant plastic encapsulated integrated circuit - having elastic insulating layer on top of the passivation layer of the side sealing round the ball and and preventing moisture ingress |
JPH06204284A (en) * | 1993-01-08 | 1994-07-22 | Nec Yamagata Ltd | Semiconductor device |
US5891745A (en) * | 1994-10-28 | 1999-04-06 | Honeywell Inc. | Test and tear-away bond pad design |
EP2685511A1 (en) * | 2011-03-10 | 2014-01-15 | DOWA Electronics Materials Co., Ltd. | Semiconductor light-emitting element and method of manufacturing thereof |
JP2014082367A (en) * | 2012-10-17 | 2014-05-08 | Nippon Micrometal Corp | Power semiconductor device |
JP2017132163A (en) * | 2016-01-29 | 2017-08-03 | 株式会社沖データ | Light-emitting element unit, exposure device, image formation device, and manufacturing method for light-emitting element unit |
WO2018037736A1 (en) * | 2016-08-22 | 2018-03-01 | 三菱電機株式会社 | Semiconductor device |
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JPS57159035A (en) * | 1981-03-26 | 1982-10-01 | Yamagata Nippon Denki Kk | Manufacture of semiconductor device |
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Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5288661A (en) * | 1989-10-17 | 1994-02-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having bonding pad comprising buffer layer |
DE4019848A1 (en) * | 1989-10-17 | 1991-04-25 | Mitsubishi Electric Corp | SEMICONDUCTOR DEVICE WITH A CONNECTING SURFACE HAVING A BUFFER LAYER |
US5525546A (en) * | 1991-01-29 | 1996-06-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing thereof |
DE4201792A1 (en) * | 1991-01-29 | 1992-08-06 | Mitsubishi Electric Corp | Improved corrosion-resistant plastic encapsulated integrated circuit - having elastic insulating layer on top of the passivation layer of the side sealing round the ball and and preventing moisture ingress |
US5430329A (en) * | 1991-01-29 | 1995-07-04 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with bonding pad electrode |
DE4201792C2 (en) * | 1991-01-29 | 1996-05-15 | Mitsubishi Electric Corp | Terminal electrode structure and method of making the same |
JPH06204284A (en) * | 1993-01-08 | 1994-07-22 | Nec Yamagata Ltd | Semiconductor device |
US5891745A (en) * | 1994-10-28 | 1999-04-06 | Honeywell Inc. | Test and tear-away bond pad design |
EP2685511A1 (en) * | 2011-03-10 | 2014-01-15 | DOWA Electronics Materials Co., Ltd. | Semiconductor light-emitting element and method of manufacturing thereof |
EP2685511A4 (en) * | 2011-03-10 | 2014-08-13 | Dowa Electronics Materials Co | Semiconductor light-emitting element and method of manufacturing thereof |
US9172005B2 (en) | 2011-03-10 | 2015-10-27 | Dowa Electronics Materials Co., Ltd. | Semiconductor light emitting diode having a contact portion and a reflective portion |
JP2014082367A (en) * | 2012-10-17 | 2014-05-08 | Nippon Micrometal Corp | Power semiconductor device |
JP2017132163A (en) * | 2016-01-29 | 2017-08-03 | 株式会社沖データ | Light-emitting element unit, exposure device, image formation device, and manufacturing method for light-emitting element unit |
WO2018037736A1 (en) * | 2016-08-22 | 2018-03-01 | 三菱電機株式会社 | Semiconductor device |
JPWO2018037736A1 (en) * | 2016-08-22 | 2019-01-31 | 三菱電機株式会社 | Semiconductor device |
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