JPH01220468A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve electric reliability, by using only high impurity concentration layers for the drains of P-channel MISFETs in a protecting circuit, and using low impurity concentration layers for the end parts of the channel regions of a P-channel MISFET in an inner circuit. CONSTITUTION:The drains of P-channel MISFETs Qp1 and Qp2 constituting a protecting circuit are formed only of high impurity concentration layers (p<+> type semiconductor regions 11). The drain of a P-channel MISFET Qp3 in an inner circuit is formed as follows: the end parts on the side of a channel region are formed of low impurity concentration layers (p-type semiconductor region 9); the other parts are formed with high purity concentration layers (p<+> type semiconductor regions 10). In this constitution, the P-channel MISFETs Qp1 and Qp2 in the input protecting circuit and the P-channel MISFET in the output protecting circuit are not damaged with the high temperature yielded at the surrounding parts of the drains at the time of breakdown. Deterioration in junction breakdown strength is prevented. Meanwhile, in the P-channel MISFET Qp3 in the inner circuit, generation of hot carriers at the end part of the drain is suppressed, and the short channel effect is suppressed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit, and in particular,
The present invention relates to a technique that is effective when applied to a P-channel MISFET of a semiconductor integrated circuit device.

[Conventional technology]

In a semiconductor integrated circuit device having a P-channel MISFET and an N-channel MISFET, the N-channel MISFET
Connect the drain of S FET to L D D (Lightly
It is common to have a doped drain structure. In this case, the end of the drain on the channel side is made to have a low concentration, and the other parts are made to have a high concentration.

Incidentally, an input protection circuit and an output protection circuit are connected to the bonding pads of the semiconductor integrated circuit device in order to prevent internal MISFETs from being destroyed by static electricity.

The input protection circuit is composed of a so-called clamp MISFET configured in the form of a diode by connecting the gate electrodes of each of a P-channel MISFET and an N-channel MISFET to a source, and a resistance element. The output protection circuit is configured between the drains of the P-channel MISFET and N-channel MISFET in the final stage of the output buffer and the N-well region or P-well region where these are provided. The drains of the N-channel MISFETs constituting these input protection circuits or output protection circuits have a so-called single drain structure consisting only of a high impurity concentration layer (Japanese Patent Laid-Open No. 61-120459
Publication No.).

However, in order to minimize the number of manufacturing steps required for the P-channel MISFET, the drains of the P-channel MISFET of the input protection circuit and output protection circuit and the P-channel MISFET of the internal circuit are formed in the same process. At this time, since the diffusion coefficient of the p-type impurity for forming the drain of the P-channel MISFET is large, the gate? ! ! If ion implantation is performed after the pole is formed and then annealed to form the pole, in a P-channel MISFET whose internal circuit has a short gate length, the drain will go too deep under the gate electrode. Therefore, the drains of the input protection circuit, output protection circuit, and P-channel MISFET of the internal circuit were formed in the same process, and the drain of the P-channel MISFET of the internal circuit was formed too deep under the gate electrode. In order to prevent this, the p-type impurity ion implantation is performed after forming sidewalls on the side surfaces of the gate electrode. Then, the subsequent annealing is performed on the P channel M of the output protection circuit.
This is because the ISFET also serves as an output buffer circuit.

Since it is necessary to extend the drain to below the gate electrode, the implanted p-type impurity is largely diffused.

[Problems to be Solved by the Invention] As mentioned above, the present inventor has solved the problem by
When we experimented with the breakdown characteristics of P-channel MISFETs in the input protection circuit and output protection circuit formed in the same process as the ET, we found that the junction breakdown voltage deteriorated each time the drain breakdown occurred, and the maximum rated voltage (for example, 7V
) was found to increase the leakage current.

This deterioration of the junction breakdown voltage occurs in a first-order manner. That is, the drain of the P-channel MISFET is, as described above,
After forming the sidewalls on the sidewalls of the gate electrode, they were widely diffused to the bottom of the gate electrode.
The impurity concentration gradient becomes very gentle, and in the peripheral portion, the region substantially between the p-type and channel regions becomes a p-type offset region. This p-type part has a high resistance value, so when it breaks down due to static electricity, it becomes locally high temperature, and the junction breakdown voltage between the drain and the semiconductor substrate (or well region) deteriorates, causing leakage current. increase

An object of the present invention is to improve the electrical reliability of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

That is, a semiconductor integrated circuit device comprising a P-channel MISFET forming a protection circuit connected to an external electrode of a semiconductor integrated circuit device, and a P-channel MISFET forming an internal circuit inside the protection circuit of the semiconductor integrated circuit device. In the P channel M constituting the protection circuit
The drain of the ISFET is made up of only a high impurity concentration layer, and the drain of the P-channel MISFET of the internal circuit is made up of only a high impurity concentration layer.

The end of it on the channel region side is a low impurity concentration layer.

The other portions are made up of high impurity concentration layers.

[Effect]

According to the above-mentioned means, in the P-channel MISFET of the input protection circuit and the output protection circuit, since their drains consist only of a high impurity concentration layer and the concentration distribution is steep, the surrounding area of the drain is It is possible to prevent the bonding voltage from deteriorating because it is not damaged due to high temperature. On the other hand, in the P-channel MISFET of the internal circuit, since the end on the channel region side is a low impurity concentration layer, the generation of hot carriers at the drain end is suppressed and the short channel effect is suppressed. For these reasons, the electrical reliability of the semiconductor integrated circuit device can be improved.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit device according to an embodiment of the present invention will be described below with reference to the drawings.

1 is a plan view of an input protection circuit portion of a semiconductor integrated circuit device according to an embodiment of the present invention; FIG. 2 is a sectional view taken along the n-■ section line of the input protection circuit shown in FIG. 1; 3 is a plan view of the output protection circuit portion of the semiconductor integrated circuit device according to the embodiment of the present invention, FIG. 4 is a cross-sectional view of the output protection circuit shown in FIG. 5 is an equivalent circuit diagram of the input protection circuit shown in FIG. 1, and FIG. 6 is an equivalent circuit diagram of the output protection circuit shown in FIG. 3.

Note that in FIGS. 1 and 3, insulating films other than the field insulating film are not shown in order to make the configurations of the input protection circuit and the output protection circuit easier to understand.

In FIGS. 1, 2, and 5, BPI is a bonding pad, and Qply, Qp2+, and Qp3 are P-channel MISFETs and Qnl, respectively.

Qn2. Each of Qn3 is an N-channel MISFET,
R is a resistance element. P-channel MISFET QP1.
QP2. Qp3 is provided in the A-type well region 3 on the main surface of the p-type semiconductor substrate 1. Also, N-channel MI
SFETQnl, Qn2, Qn3 and resistance element R are p
- type well region 2. 4 is a field insulating film, and 5 is a p-type channel stopper region. The P-channel MISFETs QPI, Qp2. The N-channel MISFETs Qnl and Qn2 and the resistance element R constitute an input protection circuit. The circuit inside the input protection circuit is an internal circuit. For example, in a memory such as a mask ROM,
Internal circuits include an input buffer circuit, an address decoder circuit, a clock circuit, a sense amplifier circuit, and a word line driver circuit. The P-channel MISFET Qp3 and the N-channel MISFET Qn3 constitute one of the internal circuits, for example, an input cover sofa circuit. P-channel M I S F E 'r constituting the input protection circuit
Q p 1. .

Qp2 is a p° type semiconductor region 1 which becomes a source and a drain.
1, a gate electrode 7, and a gate insulating film 6. Since the p° type semiconductor region 11 is formed in the same process as the source and drain of the P channel MISFET of the output buffer circuit to be described later, the end portion on the channel region side is wrapped around under the gate electrode 7. The p° type semiconductor region 11 is designed to have an impurity concentration distribution as steep as possible. N channels M of the input protection circuit
ISFETQnl, Qn2 includes a gate electrode element, a gate insulating film 6, and a go-type semiconductor region 1 that becomes a source and a drain.
It is composed of 2. And the P channel MIS
FETQpl, Qp2, N-channel MISFETQnl
, Qn2, the gate length of each gate electrode 7 is 3.
The length is approximately 0 to 3.5 μm. The P-channel MISFET Qp3 of the internal circuit includes a gate electrode element, a gate insulating film 6, a p-type semiconductor region 9 forming the end of the source and drain on the channel region side, and the p-channel MISFET Qp3 of the source and drain.
A p° type semiconductor region 10 forming a portion other than the type semiconductor region 9
It is made up of. The N-channel MISFET Qn3 includes a gate electrode 7, a gate insulating film 6, an n-type semiconductor region 13 forming the end of the source and drain on the channel region side, and a portion of the source and drain other than the n-type semiconductor region 13. It is composed of an n° type semiconductor region 14. The gate lengths of the gate electrodes 7 of the P-channel MISFET QP3 and N-channel Mn3 in these internal circuits are extremely short, about 1.3 μm. The resistance element R is made of a Go-type semiconductor region formed integrally with an n°-type semiconductor region 12 that becomes the drain of the N-channel MISFET Qn2. Reference numeral 16 denotes a wiring for supplying power supply potential Vcc, for example, 5V. This wiring 16 connects the P-channel MISFET.
The gate electrodes 7 of Qpl and Qp2 and the p' type semiconductor region 11 serving as a source are connected through a connection port 15. p which becomes the drain of P channel MISFETQpl
A wiring 18 extending from the bonding pad BPI is connected to the type 0 half region 11 through the connection port 15 . Reference numeral 17 denotes a wiring for supplying the ground potential Vss, for example, Ov. With this wiring 17, N-channel MISFE
The gate electrode 7 of TQnl and Qn2 and the n
The °-type semiconductor regions 12 are connected through connection ports 15. Further, in the n° type semiconductor region 12 which becomes the drain of the N-channel MISFETQnl, there is a wire extending from the bonding pad BPI, f! 19 are connected.

This wiring 19 is also connected to the resistance element R. 20
p° is the drain of P-channel MISFET Qp2
type semiconductor region 11, d-type semiconductor region 12 which becomes the drain of N-channel MISFETQn2, and P-channel MISFET Qn2.
Gate electrode 7 of SFETQp3 and N-channel MISF
This is a wiring that connects each of the gate electrodes 7 of ETQn3. Reference numeral 21 denotes a wiring connecting between the p° type semiconductor region 10 which becomes part of the drain of the P channel MISFET and the n° type semiconductor region 14 which becomes part of the drain of the N channel MiSFET Qn3. Each of the wiring lines 16.degree.17, 18.19.20.21 and the bonding pad BP1 is made of an aluminum film.

22 is a first layer passivation film, which is made of, for example, a silicon oxide film. 23 and 24 are final passivation films, and the passivation film 23 is made of, for example, a silicon nitride film formed by plasma CVD. The passivation film 24 is made of, for example, a polyimide film.

Next, the configuration of the output protection circuit will be explained using FIGS. 3, 4, and 6.

In FIGS. 3, 4, and 6, Qp4 is a P-channel MISFET, and Qn4 is an N-channel MISFET.
It is an FET. These P-channel MISFETQp4 and N-channel MISFETQn4 constitute an output buffer. P-channel MISFET Qp4 is composed of a gate electrode 7, a gate insulating film 6, and a p'-type semiconductor region 11 serving as a source and a drain. The p° type semiconductor region 11 extends under the gate electrode 7, and its impurity concentration gradient is made as steep as possible.

The p° type semiconductor region 11 serving as a source has a power supply potential VQ
A wiring 16 for feeding power C is connected. A bonding pad BP2 is provided in the p type semiconductor region 11 which becomes the drain.
The wiring #I25 extending from the terminal is connected.

The N-channel MISFET Q n 4 is composed of a gate electrode 7, a gate insulating film 6, and a Go-type semiconductor region 12 that becomes a source and a drain. The n-type semiconductor region 12 is wrapped around under the gate electrode. The n° type semiconductor region 12 serving as a source has a ground potential V
A wiring 17 that supplies power to ss is connected. A bonding pad BP2 is provided in the Go-type semiconductor region 12 which becomes the drain.
A wiring 26 extending from is connected thereto. In this way, the P-channel MI constituting the final stage of the output buffer circuit
Source of SFETQp4.

The drain consists only of the p'-type semiconductor region 11 with a high impurity concentration, and the source and drain of the N-channel MISFET Qn4 consist of the n'-type semiconductor region 12 with a high impurity concentration.
It consists only of

The output protection circuit of the output buffer circuit includes a PN transistor formed between the p' type semiconductor region 11 and the n- type well region 3.
It is composed of a junction diode and a PN junction diode formed between the d-type semiconductor region 12 and the p-type well region 2. That is, the P-channel MZSFETQp4 and the N-channel MIS that constitute the output buffer circuit
FETQn4 also serves as an output protection circuit. and,
For example, in a memory such as a mask ROM, a sense amplifier circuit and a word line driver circuit are located inside the output sofa circuit.

An internal circuit such as a clock circuit is provided.

Next, connect the source and drain of the P-channel MISFET of the input protection circuit and output protection diode to p.

type semiconductor region only, i.e. single train (SD)
The electrical reliability will be compared between when the source and drain are made into an LDD structure or a double drain (DD) structure.

FIG. 7 is a diagram showing the failure rate with respect to the electrostatic breakdown voltage of a single drain, a drain with an LDD structure, or a double drain. The horizontal axis is the electrostatic breakdown voltage (V), and the vertical axis is the failure rate (%). ).

Figure 8 is a diagram showing the leakage current characteristics after breakdown of a single drain, a drain with an LDD structure, or a double drain, where the horizontal axis is the reverse bias voltage (■) and the vertical axis is the leakage current (μA). It is.

FIG. 9 is a diagram showing the deterioration time with respect to stress voltage for a single drain, a drain with an LDD structure, or a double drain. The horizontal axis is the stress voltage (V), and the vertical axis is the deterioration time (hr). .

As shown in Figure 7, the single drain (SD) is
MIS with LDD structure drain or double drain (DD)
It is less likely to cause defects due to electrostatic breakdown voltage than FETs. Furthermore, as shown in Figure 8, when static electricity is repeatedly applied, the leakage current characteristics of the LDD structure drain or double drain change from the initial leakage current characteristics shown by the solid line AO to the broken lines Al and A2. As such, the leakage current characteristics gradually deteriorate. On the other hand, in the case of a single drain, the initial leakage current characteristic shown by the solid line AO can be maintained even after the stress voltage is applied.

Furthermore, as shown in FIG.
D) is a drain with an LDD structure or a double drain (DD)
Therefore, the deterioration time can be increased relative to the stress voltage.

Next, the P-channel MISF constituting the input protection circuit
ETQpl, Qp2, N-channel MISF'ETQnl
, Qn2 and resistance element R, P channel M I S
FETQp 2, N-channel MISFETQ
n2 and resistance element R, and P that constitutes the input cover sofa circuit.
Channel MISFETQP3. N-channel MISFET
The manufacturing method of Qn3 will be explained.

10 to 19 show the P-channel MISFET
Qp2, N-channel MISFETQn2゜resistance element R, and P-channel MISFETQp3゜N-channel MISF
It is a diagram for explaining the manufacturing method of ETQn3, and the second
It is a sectional view of the same part as the figure. Note that the P-channel MISFETQp4 and N-channel MISFET that constitute the output buffer
The manufacturing method of SFETQ n 4 is the same as that of the P-channel MISFETs Qpl, Qp2 or the N-channel MISFETs Qnl, Qn2 of the input protection circuit, so the explanation will be omitted. In addition, the P-channel MI 5FET of the internal circuit
The manufacturing method of P-channel MISFET other than Qp3 is P
The method for manufacturing N-channel MISFETs other than the N-channel MISFET Qn3, which is the same as channel MISFET Qp3 and has an internal circuit, is the same as N-channel MISFET Qp3.
Same as Qn3. Furthermore, a memory cell such as a mask ROM is formed in the same manner as the N-channel MISFETQn3.

The method for manufacturing the semiconductor integrated circuit device includes first forming a p-type semiconductor substrate 1, a p-type well region 2, an n-type well region 3 . After forming each of the field insulating film 4 and the p-channel stopper region 5, the surfaces of the p-type well region 2 and type 1 well region 3 exposed from the field insulating film 4 are thermally oxidized to form a gate insulating film 6 ( Figure 10) is formed.

Next, a two-layer film (polycide film) consisting of, for example, a polycrystalline silicon film and a high melting point metal silicide film is formed on the entire surface of the semiconductor substrate 1, and this is patterned to form the respective layers as shown in FIG. A gate electrode 7 is formed. When forming this gate electrode 7, P-channel MISFETs Qpl, Qp2 . The gate length of N-channel MISFETQn1, Qn2 and P-channel MISFETQp4, N-channel MISFETQn4 that constitute the output buffer circuit is 3.0 to 3.5 μm.
The gate length of other MISFETs is 16
The thickness is about 3 μm. Next, the source and drain are LD
A mask 30 (FIG. 11) made of a resist film is formed on the semiconductor substrate 1 in order to form a portion with a low impurity concentration among the source and drain of the N-channel MI SFET Qn3 having a D structure. Next, as shown in FIG. 11, an n-type impurity 31, for example, phosphorus, is introduced by ion implantation into the region where the N-channel MISFET Qn3 is provided. The dose is I x 1013 atoms/d
to a certain degree. This ion implantation leads to N-channel MISF
This is a step of forming the n-type semiconductor region 13 of ETQn3. After this, the mask 30 is removed. Next, P of the internal circuit
In order to form a p-type semiconductor region 9, which is part of the source and drain of the channel MISFET Qp3, by ion implantation, a mask 32 (made of a resist film) is formed on the semiconductor substrate 1.
FIG. 12) is formed. Then, as shown in FIG. 12, a P-type impurity 33, such as boron nifluoride (
B F2) is introduced. The dose is 7 x 10”a
tones/aJ diameter.

This ion implantation is the step of forming the p-type semiconductor region 9 of the P-channel MISFET QP3.

After this, the mask 32 is removed. Next, N-channel MI
In order to form the source and drain of SFETQn2 by ion implantation, a mask 34 (FIG. 13) made of a resist film is formed on the semiconductor substrate 1.

Then, as shown in FIG. 13, the N-channel MISFE
An n-type impurity 351, such as phosphorus (P), is introduced by ion implantation into the region where TQn2 is provided.

The dose amount is approximately 5×10” atoms/aa.

This ion implantation is the step of forming the go-type semiconductor region 12 of the N-channel MISFETQn2.

After this, the mask 34 is removed. Then P channel MI
In order to form the source and drain of the 5FET Qp2 by ion implantation, a mask 36 (FIG. 14) made of a resist film is formed on the semiconductor substrate 1.

Then, as shown in FIG. 14, the P-channel MISFE
A p-type impurity 371, such as boron difluoride 37, is introduced by ion implantation into the region where TQp2 is provided. The dose amount is approximately 2×10”atoms/a1.

This ion implantation leads to P-channel MISFETQp 2
This is a step of forming a p° type semiconductor region 11. After this, the mask 36 is removed. Next, in order to form the sidewall 8, as shown in FIG. 15, a silicon oxide film 8A is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD.Next, the silicon oxide film 8A is subjected to reactive ion etching. Then, as shown in FIG. 16, a sidewall 8 is formed on the side surface of the gate electrode 7. next.

Perform Ar annealing and silicide oxidation. At this time, due to the heat applied to the semiconductor substrate 1, the impurities 31, 33, 35
．． 37 are slightly diffused to form a shallow junction depth n
type semiconductor region 13. p-type semiconductor region 9°p-type semiconductor region 11. An n″ type semiconductor region 12 is formed.Next, an N″ type semiconductor region 12 is formed.
A mask 38 (FIG. 17) made of a resist film is formed on the semiconductor substrate 1 in order to form the high concentration portions (n° type semiconductor region 14) of the source and drain of the channel MISFET Qn3 by ion implantation. Then, an n-type impurity 39, such as arsenic (A
s). The dose is 5 x 10”ato
Set it to about ms/cxi. This ion implantation is a step for forming the go-type semiconductor region 14 of the N-channel MISFET Q n 3. After this, mask 38
remove. Next, the highly doped portions of the source and drain of the P-channel MISFET QP3 (the p-type semiconductor region 10
) is formed by ion implantation, a mask 40 made of a resist film is formed on the semiconductor substrate 1. And P
A p-type impurity 411 such as boron difluoride (B
F2) is introduced. The dose is 2 x 101'at
oI! Set it to about ls/cJ. This ion implantation is the step of forming the p' type semiconductor region 11 of the P channel MISFET QP2. After this, the mask 40 is removed. next.

After annealing, each of the introduced impurities was removed by 31°3.
3, 35, 37, 39, 41 and diffused to a predetermined depth, the n-type semiconductor region 13. p-type semiconductor region9. r1'' type semiconductor region 12+p'' type semiconductor region 11. The r1' type semiconductor region 14* and the p'' type semiconductor region 10 are each completed.

As explained above, the P-channel MISFETQp1/Q constitutes the protection circuit connected to the external electrodes (ponding pads BPI, BP2) of the semiconductor integrated circuit device.
p2, and a P-channel MISFET Qp3 that constitutes an internal circuit inside the protection circuit of the semiconductor integrated circuit device.
In the semiconductor integrated circuit device, the drains of the P-channel MISFETs Qpl and Qp2 constituting the protection circuit are composed only of a high impurity concentration layer (p" type semiconductor region 11), and the drains of the P-channel MISFET Qpl and Qp2 of the internal circuit
The drain of p3 is formed by forming a low impurity concentration layer (p type semiconductor region) at the end on the channel region side and a high impurity concentration layer (p type semiconductor region 10) at the other part. The drains (p
Since the concentration distribution of the °-type semiconductor region 11) is steep, the surrounding area of the drain does not become hot and break during breakdown, so deterioration of the junction breakdown voltage can be prevented. On the other hand, the P-channel MISF of the internal circuit
In ETQp3, since the end on the channel region side is a low impurity concentration layer (p-type semiconductor region 9), the generation of hot carriers at the drain end is suppressed and the short channel effect is suppressed. For these reasons, the electrical reliability of the semiconductor integrated circuit device can be improved.

Note that the semiconductor integrated circuit device of the present invention may be formed as follows.

That is, each P channel M of the input protection circuit, output protection circuit (i.e., output sofa circuit), and internal circuit
The gate lengths of the gate electrodes 7 of the ISFETs are made the same and slightly longer than the gate lengths of the N-channel MISFETs in the internal circuit, and the sources and drains of the respective P-channel MISFETs are formed in the same process.

20 to 25 are diagrams for explaining a method of manufacturing a semiconductor integrated circuit device according to the present invention, which is different from the above-mentioned method.
FIG. 3 is a cross-sectional view of the same part as the figure in the manufacturing process.

Note that the P-channel MISFETQpl of the input protection circuit is the same as the P-channel MISFETQp2. Formed similarly to Qp3, N-channel M I S F E of the input protection circuit
T Q n 1 is formed in the same way as N-channel MISFET Qn2, so it will be omitted. Also, for example, mask RO
In memory such as M, memory cells are N-channel MISFE
Since it is formed in the same manner as TQn3, the explanation will be omitted.

In a method of manufacturing a semiconductor integrated circuit device that is different from the above embodiment, first, each gate electrode element (the 20th
form). Here, the gate length of N-channel MISFETQn2 constituting the input protection circuit is 3.0 to 3.0.
The P-channel M I S of the input protection circuit should be approximately 5 μm.
F E T Q p 2 and internal circuit P channel M
The gate length of ISFETQp3 is set to about 1.5 μm.

The gate length of the N-channel MISFET Qn3 in the internal circuit is set to about 1.degree. 3 .mu.m. Next, N channel M
A mask 42 made of a resist film is formed on the semiconductor substrate 1 in order to form the low concentration layer (n-type semiconductor region 13) of the ISFET Qn3 by ion implantation. Next, as shown in FIG. 20, an n-type impurity 43, for example, phosphorus, is introduced by ion implantation into the region where the N-channel MISFET Qn3 is provided. This ion implantation is a step for forming the n-type semiconductor region 13.

After this, the mask 42 is removed. Next, N-channel MI
n is the source and drain of SFETQn2.

In order to form the type semiconductor region 12 by ion implantation, a mask 43 (the 21st resist film) is formed on the semiconductor substrate 1.
form). Then, as shown in FIG. 21, an n-type impurity, for example, phosphorus, is introduced by 45° by ion implantation into the region where the N-channel MISFET Q n 2 is provided. This ion implantation is a process for forming the n' type semiconductor region 12. After this, the mask 43 is removed. Next, in order to form the sources and drains of P-channel MISFETQp2 (input protection circuit) and P-channel MISFETQp3 (internal circuit) by ion implantation, a mask 46 made of a resist film (
Section 22). And P channel MISFE
A p-type impurity 47, such as boron difluoride, is introduced by ion implantation into the region where TQp2°Qp3 is provided.

This ion implantation leads to P-channel MISFETQp 2
This is a step of forming +Q p 3. After this, the mask 46 is removed. Next, as shown in FIG. 23, a sidewall 8 made of a silicon oxide film is formed on the side surface of each gate electrode 7. At this time, the respective impurities are slightly diffused by the heat applied to the semiconductor substrate l, and the shallow junctions of the n-type semiconductor region 13 and the go-type semiconductor region 12yP
' type semiconductor regions 10.11 are formed. Next, a mask 48 (made of a resist film) (
Figure 24) is formed. Then, as shown in FIG. 24, n-type impurities 49,
For example, introducing arsenic. This ion implantation is the source.

This is a step of forming a high concentration layer for the drain. After this, mask 48 is removed. Next, annealing is performed to activate each of the previously introduced impurities, thereby forming the n-type semiconductor region 13. as shown in FIG. rl'' type semiconductor region 12.14. p' type semiconductor region 10.11
is completed.

As explained above, the P-channel MISFET of the output protection circuit and the input protection circuit, and the P-channel MISFET of the internal circuit
By making the gate lengths of the respective gate electrodes 7 of the ISFETs the same and longer than the gate lengths of the gate electrodes 7 of the N-channel MISFETs in the internal circuit, the drains of the respective P-channel MISFETs (p" type semiconductor Since the region 11) can be formed at the same time by ion implantation before forming the sidewall 8, the P-channel MISFET of the input protection circuit and output protection circuit can be formed simultaneously.
The breakdown characteristics can be improved, and the generation of short channel effects and hot carriers can be suppressed in the P-channel MISFET of the internal circuit. Furthermore, since the drains (including the sources) of each of the P-channel MISFETs can be formed in the same process,
The manufacturing process can be shortened.

Although the source and drain of the internal N-channel MISFET have an LDD structure, the source and drain may have a so-called double drain structure in which a high impurity concentration layer is provided within a low impurity concentration layer.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, in the second embodiment, the mask 42 is omitted.

In short, the manufacturing process can be shortened by introducing n-type impurities into the entire surface of the wafer to form the n-type semiconductor region 13.

(Effects of the Invention) The effects obtained by typical inventions disclosed in this application are briefly described below.

P-channel MISFET for input protection circuit and output protection circuit
In this case, since these drains consist only of a layer with high impurity concentration, and the concentration distribution is steep, the surrounding area of the train does not become hot and rupture during breakdown, and the junction breakdown voltage deteriorates. can be prevented. On the other hand, in the P-channel MISFET of the internal circuit, the edge on the channel region side is a low impurity concentration layer, so the generation of hot carriers at the drain edge is suppressed.
Also, short channel effects are suppressed. from these things,
The electrical reliability of the semiconductor integrated circuit device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view of the input protection circuit portion of the semiconductor integrated circuit device, FIG. 2 is a sectional view of the input protection circuit shown in FIG. FIG. 4 is a plan view of the output protection circuit portion of the semiconductor integrated circuit device; FIG. 4 is a sectional view taken along the line IV--■ of the output protection circuit shown in FIG. 3; Figure 5 is an equivalent circuit diagram of the input protection circuit shown in Figure 1, Figure 6 is an equivalent circuit diagram of the output protection circuit shown in Figure 3, and Figure 7 is an equivalent circuit diagram of the input protection circuit shown in Figure 3. Figure 8 is a diagram showing the failure rate with respect to electrostatic breakdown voltage of a drain or double drain. Figure 8 is a diagram showing leakage current characteristics after breakdown of a single drain and a drain of an LDD structure or a double drain. The figure shows the deterioration time of a single drain, a drain of an LDD structure, or a double drain with respect to stress voltage. 10 to 19 show the P-channel MISFET
Qp 2, N-channel MISFET Qn2, resistance element R
and P-channel MISFETQp3゜N-channel MIS
20 to 25 are diagrams for explaining a method for manufacturing the FETQn3, and FIGS. 20 to 25 are diagrams for explaining a method for manufacturing a semiconductor integrated circuit device that is different from the manufacturing method shown in FIGS. 10 to 19. be. In the figure, Q p 1 + Q p 2...P for input protection
Channel M I S F E T , Q n 1 ,
Q n 2---N-channel MISFET for human power protection
, Qp3... P-channel MISFET of internal circuit, Q
n3... N-channel MISFET of internal circuit, 6...
- Gate insulating film, 7... Gate electrode, 8... Side wall, 9... P-type semiconductor region, 10, 11...
p° type semiconductor region, 12.14... n° type semiconductor region, 13... n type semiconductor region. (death

Claims (1)

[Claims] 1. A P-channel MISFET constituting a protection circuit connected to an external electrode of a semiconductor integrated circuit device, and a P-channel MISFET constituting an internal circuit inside the protection circuit of the semiconductor integrated circuit device. In the semiconductor integrated circuit device comprising: a P-channel MISF constituting the protection circuit;
The drain of the ET is composed of only a high impurity concentration layer, and the drain of the P-channel MISFET of the internal circuit is composed of a low impurity concentration layer at the end on the channel region side and a high impurity concentration layer at the other part. A semiconductor integrated circuit device characterized by: 2. A P-channel MISFET forming a protection circuit connected to an external electrode of the semiconductor integrated circuit device, a P-channel MISFET forming an internal circuit inside the protection circuit of the semiconductor integrated circuit device, and forming the internal circuit. In a semiconductor integrated circuit device having an N-channel MISFET, the gate lengths of the gate electrodes of the P-channel MISFET of the protection circuit and the P-channel MISFET of the internal circuit are made the same, and the N-channel MISFET of the internal circuit is
A semiconductor integrated circuit device characterized by having a gate length slightly longer than the gate length of a gate electrode of an SFET.