JPH01218062A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01218062A JPH01218062A JP63044801A JP4480188A JPH01218062A JP H01218062 A JPH01218062 A JP H01218062A JP 63044801 A JP63044801 A JP 63044801A JP 4480188 A JP4480188 A JP 4480188A JP H01218062 A JPH01218062 A JP H01218062A
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- Prior art keywords
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- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 150000001875 compounds Chemical class 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 238000001514 detection method Methods 0.000 abstract description 20
- 239000005083 Zinc sulfide Substances 0.000 abstract description 10
- 229910052984 zinc sulfide Inorganic materials 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 4
- DRDVZXDWVBGGMH-UHFFFAOYSA-N zinc;sulfide Chemical compound [S-2].[Zn+2] DRDVZXDWVBGGMH-UHFFFAOYSA-N 0.000 abstract description 4
- 229910004613 CdTe Inorganic materials 0.000 abstract 1
- 239000000969 carrier Substances 0.000 description 8
- RPPBZEBXAAZZJH-UHFFFAOYSA-N cadmium telluride Chemical compound [Te]=[Cd] RPPBZEBXAAZZJH-UHFFFAOYSA-N 0.000 description 6
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- 229910052793 cadmium Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052714 tellurium Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
赤外線検知素子と該検知素子の信号を信号処理する電荷
結合素子とを金属柱で接続した半導体装置に関し、
検知素子の信号がクロストークを生じるのを防止するの
を目的とし、
化合物半導体基板に形成した光電変換素子と、他方の半
導体基板に形成した半導体素子を金属柱にて接続形成し
た装置に於いて、前記化合物半導体基板に素子形成予定
領域を交互に凹凸状に形成し該凹凸状領域、或いは凹部
状領域に素子形成用不純物層を設けたことで構成する。[Detailed Description of the Invention] [Summary] A semiconductor device in which an infrared sensing element and a charge-coupled device that processes the signal of the sensing element are connected by a metal pillar, and the generation of crosstalk in the signals of the sensing element is prevented. For the purpose of It is constructed by forming a concavo-convex shape in the convex-concave region and providing an element-forming impurity layer in the concave-convex region or the concave region.
本発明は半導体装置に係り、特に光電変換素子と該素子
の信号を処理する電荷結合素子とを金属柱で一体化した
ハイブリッド型赤外線検知装置に関する。The present invention relates to a semiconductor device, and more particularly to a hybrid infrared detection device in which a photoelectric conversion element and a charge-coupled device for processing a signal from the element are integrated with a metal pillar.
赤外線に高感度を有し、エネルギーバンドギャップの狭
い水銀・カドミウム・テルル（Ｉｌｇ ＋ −１＋Ｃｄ
ＸＴｅ）のような化合物半導体基板に赤外線検知素子
のような光電変換素子を形成し、シリコン基板に該検知
素子で得られた信号を処理する電荷結合素子を形成し、
この赤外線検知素子と電荷結合素子とをインジウム等の
金属柱で接続形成したハイブリッド型赤外線検知装置は
周知である。Mercury, cadmium, tellurium (Ilg + -1+Cd) has high sensitivity to infrared rays and has a narrow energy band gap.
A photoelectric conversion element such as an infrared detection element is formed on a compound semiconductor substrate such as XTe), a charge-coupled device for processing a signal obtained by the detection element is formed on a silicon substrate,
A hybrid infrared detection device in which an infrared detection element and a charge-coupled device are connected by a metal column such as indium is well known.
このような赤外線検知装置を構成する検知素子は、その
解像度を高めるために高密度で形成することが要求され
ているが、該素子の高密度化を図ると素子で検知された
信号がクロストークを発生する問題があり、素子を高密
度で形成した場合でもクロストークを発生しないハイプ
リント型赤外線検知装置が望まれる。The detection elements that make up such an infrared detection device are required to be formed at high density in order to increase their resolution, but increasing the density of the elements causes crosstalk between the signals detected by the elements. Therefore, there is a need for a high-print type infrared detection device that does not cause crosstalk even when elements are formed at high density.
従来のハイブリッド型赤外線検知装置の要部の構造を第
４図に示す。FIG. 4 shows the structure of the main parts of a conventional hybrid infrared detection device.
図示するようにカドミウムテルル（ＣｄＴｅ）の基板ｌ
上に形成したＰ型のＨｇＩ−ｘ Ｃｄ、 Ｔｅのエピタ
キシャル層２の所定領域にボロン（Ｂ）原子をイオン注
入してＮ型層３を形成して光起電力型のホトダイオード
のような赤外線検知素子４をアレイ状に形成する。次い
でエピタキシャル層２上に硫化亜鉛（ＺｎＳ）よりなる
表面保護膜５を形成し、この保１！膜５のＮ型層３上を
開口してインジウム（Ｉｎ）を蒸着により形成してＩｎ
金属柱６を形成する。As shown in the figure, a cadmium tellurium (CdTe) substrate l
Boron (B) atoms are ion-implanted into a predetermined region of the P-type HgI-x Cd, Te epitaxial layer 2 formed above to form an N-type layer 3, which is used for infrared detection such as a photovoltaic photodiode. The elements 4 are formed in an array. Next, a surface protection film 5 made of zinc sulfide (ZnS) is formed on the epitaxial layer 2, and this protection 1! An opening is formed on the N-type layer 3 of the film 5 and indium (In) is formed by vapor deposition.
A metal column 6 is formed.
一方、図示しないがＰ型のシリコン（Ｓｉ）基板にこの
赤外線検知素子４で得られた信号を処理する電荷結合装
置を形成する。そして該Ｓｉ基板に燐等のＮ型の不純物
をイオン注入して形成したＮ型層、つまりこのＰ−Ｎ接
合部で形成される電荷結合素子の人力ダイオードに前記
したようにＩｎ金属柱を形成し、この金属柱と前記形成
したＩｎ金属柱６とを圧着接合して、前記化合物半導体
基板に形成した光電変換素子とＳｉ基板に形成した電荷
結合素子を一体化してハイブリッド型赤外線検知装置を
形成している。On the other hand, although not shown, a charge coupled device for processing the signal obtained by the infrared sensing element 4 is formed on a P-type silicon (Si) substrate. Then, an N-type layer formed by ion-implanting N-type impurities such as phosphorus into the Si substrate, that is, an In metal pillar is formed as described above in the charge-coupled device artificial diode formed at this P-N junction. Then, this metal column and the formed In metal column 6 are bonded together by pressure bonding, and the photoelectric conversion element formed on the compound semiconductor substrate and the charge coupled element formed on the Si substrate are integrated to form a hybrid infrared detection device. are doing.
然し、このようなハイブリッド型赤外線検知装置に於い
ては、ＣｄＴｅの基板１の背面側より赤外線を入射し、
そのＣｄＴｅの基板より導入された光が更にＨｇＩ−ｘ
ＣｄＸＴｅのエピタキシャルＮ２に導入され、ＣｄＴ
ｅ１板１１との界面付近（数μｍ）でキャリアが発生し
、このキャリアは拡散により検知素子４に到達する。However, in such a hybrid infrared detection device, infrared rays are incident on the back side of the CdTe substrate 1, and
The light introduced from the CdTe substrate is further HgI-x
introduced into the epitaxial N2 of CdXTe, CdT
Carriers are generated near the interface (several μm) with the e1 plate 11, and these carriers reach the sensing element 4 by diffusion.
従って第４図に示すように、ホトダイオードのような素
子４Ａ、４Ｂの中間の位置に導入された少数キャリア７
は検知素子４＾、４Ｂの両方にまたがって導入されるよ
うになり、素子で検知される信号にクロストークを生じ
るようになり、検知装置の解像度が悪くなって精度良く
基板に入射された赤外線を検知することは困難である。Therefore, as shown in FIG.
is now introduced across both detection elements 4^ and 4B, causing crosstalk in the signals detected by the elements, and the resolution of the detection device deteriorates, causing infrared rays incident on the board to be accurately detected. is difficult to detect.
本発明は上記した問題点を解決し、検知信号のクロスト
ークの発生を少なくした新規な半導体装置の提供を目的
する。An object of the present invention is to solve the above-mentioned problems and provide a novel semiconductor device that reduces the occurrence of crosstalk of detection signals.
上記目的を達成するための本発明の半導体装置は、第１
図に示すように化合物半導体基板に形成した光電変換素
子と、他方の半導体基板に形成した半導体素子を金属柱
にて接続形成した装置に於いて、前記化合物半導体基板
１２に素子形成予定領域１３Ａ、 １３Ｂ、 １３Ｇを
交互に凹凸状に形成し該凹凸状領域、或いは凹部状領域
に素子形成用不純物層１４八。A semiconductor device of the present invention for achieving the above object includes a first
As shown in the figure, in a device in which a photoelectric conversion element formed on a compound semiconductor substrate and a semiconductor element formed on the other semiconductor substrate are connected by a metal pillar, an area 13A where an element is to be formed on the compound semiconductor substrate 12, 13B and 13G are alternately formed in a concave and convex shape, and an impurity layer 148 for forming an element is formed in the concavo-convex region or the concave region.
１４Ｂ、 １４Ｃを設ける。14B and 14C are provided.
本発明の半導体装置は、化合物半導体基板に形成される
素子形成予定領域を一列状に交互に凹凸状に形成するか
、或いは素子形成予定領域を基板表面に千鳥状に凹凸状
に形成し、素子間に導入された少数キャリアが、該キャ
リアに近接する凹部素子形成領域の不純物導入層に導入
されるようにしてクロストークの発生を少なくする。In the semiconductor device of the present invention, the regions where the elements are to be formed on the compound semiconductor substrate are formed in a concave and convex shape alternately in a row, or the regions where the elements are to be formed are formed in a staggered manner on the surface of the substrate. The minority carriers introduced between the carriers are introduced into the impurity-introduced layer in the concave element formation region adjacent to the carriers, thereby reducing the occurrence of crosstalk.
以下、図面を用いて本発明の半導体装置の一実施例につ
き詳細に説明する。Hereinafter, one embodiment of the semiconductor device of the present invention will be described in detail with reference to the drawings.
第１図は本発明の半導体装置の第１の実施例に於ける光
電変換素子側の断面図である。FIG. 1 is a sectional view of the photoelectric conversion element side in a first embodiment of the semiconductor device of the present invention.
図示するようにＣｄＴｅの基板１１上にＰ型のＨｇＩ−
ｘＣｄ、 Ｔｅのエピタキシャル層１２が形成され、該
エピタキシャル層１２の素子形成予定領域１３Ａ、 １
３Ｂ、 １３Ｃが交互に列状に凹凸状に形成され、その
凹部の素子形成予定領域１３Ｂ、或いは凸部の素子形成
予定領域１３Ａ、１３Ｇの両方に素子形成用不純物を導
入して不純物導入層としてのＮ型層１４Ｂおよび１４Ａ
、１４Ｃが形成されている。更に凹部の素子形成予定領
域１３Ｂの側壁部には硫化亜鉛（ＺｎＳ）よりなる絶縁
膜１５が形成され、更に四部の素子形成予定領域１３Ａ
にはＩｎ金属柱１６が埋設形成され、凸部の素子形成予
定領域１３ＨにＩｎ金属柱１７が形成されている。As shown in the figure, a P-type HgI-
An epitaxial layer 12 of xCd, Te is formed, and device formation regions 13A and 1 of the epitaxial layer 12 are formed.
3B and 13C are formed alternately in rows in a concave and convex shape, and an impurity for forming an element is introduced into both the concave part of the region 13B where the element is to be formed, or the convex part of which is intended to be the element formation region 13A and 13G, to form an impurity-introduced layer. N-type layers 14B and 14A of
, 14C are formed. Further, an insulating film 15 made of zinc sulfide (ZnS) is formed on the side wall of the concave element formation area 13B, and furthermore, an insulating film 15 made of zinc sulfide (ZnS) is formed on the side wall of the element formation area 13B of the concave portion.
An In metal column 16 is embedded in the area, and an In metal column 17 is formed in a region 13H where an element is to be formed in the convex portion.
また図示しないが他方のＳｔ基板に電荷結合素子を形成
し、その入力ダイオードにＩｎ金属柱を形成し、前記し
たＩｎ金属柱１６．１７と圧着接合して赤外線検知装置
を得る。Further, although not shown, a charge-coupled device is formed on the other St substrate, and an In metal column is formed on its input diode, and the infrared detection device is obtained by pressure bonding with the aforementioned In metal columns 16 and 17.
このようにすれば、検知素子間に発生する少数キャリア
７は凹部の素子形成予定領域に形成されたＮ型層１４Ｂ
が距離が近いために、該Ｎ型層１４Ｂに導入されること
になり、隣接する凸部素子形成予定領域１３Ａと凹部素
子形成予定領域１３Ｂで形成された画素子間に跨がって
導入されることが無くなり、クロストークを発生するこ
とが無くなる。In this way, the minority carriers 7 generated between the sensing elements are removed from the N-type layer 14B formed in the concave element formation area.
Since the distance is short, it is introduced into the N-type layer 14B, and is introduced across the pixel elements formed in the adjacent convex element formation area 13A and concave element formation area 13B. This eliminates the occurrence of crosstalk.
尚、本実施例の他に凹部素子形成予定領域１３Ｂにのみ
、不純物導入層１４１３を設けても良い。In addition to this embodiment, the impurity-introduced layer 1413 may be provided only in the region 13B where the concave element is to be formed.
第２図に本発明の赤外線検知装置の第２実施例の平面図
を示す。FIG. 2 shows a plan view of a second embodiment of the infrared detection device of the present invention.
図で斜線を施した四角の箇所は化合物半導体基板２１の
表面に形成した凹部素子形成予定領域２２で、斜線を施
さない四角の箇所は凸部素子形成予定領域２３で図示す
るように凹部素子形成予定領域２２、および凸部素子形
成予定領域２３が二次元的に千鳥状に交互に形成されて
いる。In the figure, the square area with diagonal lines is a region 22 where a concave element will be formed on the surface of the compound semiconductor substrate 21, and the square area without diagonal lines is the area where a convex element will be formed, as shown in the figure. The planned regions 22 and the planned convex element formation regions 23 are two-dimensionally formed alternately in a staggered manner.
このようにすれば素子間に導入されたキャリアが画素子
間に跨がって導入されず、凹部素子形成領域にのみ導入
されるのでクロストークを発生しない高信軌度の赤外線
検知装置が得られる。In this way, the carrier introduced between the elements will not be introduced across the pixels, but will be introduced only into the concave element formation region, resulting in a high-fidelity infrared detection device that does not cause crosstalk. It will be done.
このような本発明の半導体装置の製造方法に付いて述べ
る。A method of manufacturing such a semiconductor device of the present invention will be described.
第３図（ａ）に示すようにＣｄＴｅの基板１１上に厚さ
が２０ ａ ｍ程度のｔ１ｇ＋−ｘ Ｃｄｘ Ｔｅのエ
ピタキシャル層１２をＭＯＣＶＤ法（有機金属気相成長
方法）等を用いて形成する。このエピタキシャル層１２
上に所定のパターンのレジスト膜３１を形成し、該レジ
スト膜３１をマスクとしてブロム（Ｂｒｚ）とメチルア
ルコールを主体とせるエツチング液を用いてエピタキシ
ャル層１２を深さがＩＯμｍ程度にエツチングし、凹部
素子形成予定領域１３Ｂを形成する。As shown in FIG. 3(a), an epitaxial layer 12 of t1g+-x Cdx Te with a thickness of about 20 am is formed on a CdTe substrate 11 using MOCVD (metal organic chemical vapor deposition) or the like. . This epitaxial layer 12
A resist film 31 with a predetermined pattern is formed thereon, and using the resist film 31 as a mask, the epitaxial layer 12 is etched to a depth of about IO μm using an etching solution mainly containing bromine (Brz) and methyl alcohol to form recesses. An element formation planned region 13B is formed.
この凹部素子形成予定領域１３Ｂは第４図に示した従来
の赤外線検知素子に示した素子形成領域４Ａ。This concave element forming area 13B is the element forming area 4A shown in the conventional infrared sensing element shown in FIG.
４Ｂ間のピッチ２の２倍の寸法に対応した寸法とする。The dimension corresponds to twice the dimension of pitch 2 between 4B.
次いで第３図ら）に示すように、上記したレジスト膜３
１を除去した後、蒸着方法によりＺｎＳよりなる絶縁膜
３２をエピタキシャル層１２０表面に形成する。Next, as shown in FIG. 3, etc., the resist film 3 described above is
1, an insulating film 32 made of ZnS is formed on the surface of the epitaxial layer 120 by a vapor deposition method.
次いでＮ型の不純物の導入用マスクとなるレジスト膜３
３を所定のパターンに形成する。Next, a resist film 3 is formed to serve as a mask for introducing N-type impurities.
3 into a predetermined pattern.
次いで第３図（Ｃ）に示すように、該レジスト膜３３を
マスクとして用いて例えばボロンイオン（Ｂ“）のイオ
ン注入によりＮ型層１４Ａ、および１４Ｂを形成する。Next, as shown in FIG. 3C, N-type layers 14A and 14B are formed by implanting, for example, boron ions (B'') using the resist film 33 as a mask.
次いでレジスト膜３３をマスクとして基板上よりＩｎの
金属膜３４を蒸着により形成した後、該レジスト膜３３
を除去するとともに、その上のＩｎ＃Ｌ属膜３４をもリ
フトオフ法で除去して第１図に示したような赤外線検知
素子を得る。Next, an In metal film 34 is formed on the substrate by vapor deposition using the resist film 33 as a mask, and then the resist film 33 is
At the same time, the In#L metal film 34 thereon is also removed by a lift-off method to obtain an infrared sensing element as shown in FIG.
このような本発明の装置によれば隣接する画素子間に導
入されたキャリアは、最も近接する四部素子形成領域に
導入されるので、隣接する画素子間に跨がって導入され
ることが無くなり、クロストークを発生することが無く
なる。According to the apparatus of the present invention, carriers introduced between adjacent pixel elements are introduced into the nearest four-part element formation region, so that carriers cannot be introduced across adjacent pixel elements. This eliminates the occurrence of crosstalk.
尚、本実施例ではＣｄＴｅの化合物半導体基板の上にｆ
ｉｇ、、 Ｃｄ、 Ｔｅのエピタキシャル層を形成し、
該エピタキシャル層に検知素子を形成したが、Ｈｇ＋−
ｘＣｄｘ Ｔｅの基板を用いて、該基板に素子形成用の
不純物原子を導入する構造を採っても良い。In this example, f is placed on a CdTe compound semiconductor substrate.
Form an epitaxial layer of ig, Cd, Te,
A sensing element was formed in the epitaxial layer, but Hg+-
A structure may be adopted in which an xCdx Te substrate is used and impurity atoms for element formation are introduced into the substrate.
以上の説明から明らかなように本発明によれば、クロス
トークの発生が少ない高信頼度の赤外線検知装置が得ら
れる。As is clear from the above description, according to the present invention, a highly reliable infrared detection device with less occurrence of crosstalk can be obtained.
第１図は本発明の半導体装置の第１実施例を示す断面図
、
第２図は本発明の半導体装置の第２実施例を示す平面図
、
第３図（ａ）より第３図（Ｃ）までは、本発明の装置の
製造方法を説明するための断面図、
第４図は従来の半導体装置の要部を示す断面図である。
図において、
１１はＣｄＴｅ基板、１２はｌ１ｇ＋−ｘ Ｃｄｘ Ｔ
ｅのエピタキシャル層、１３Ａ、 １３Ｂ、 １３Ｃは
素子形成領域、１４Ａ、 １４Ｂ。
１４Ｃは不純物導入層（Ｎ型層）、１５は絶縁膜、１６
．１７はＩｎ金属柱、２１は化合物半導体基板、２２は
凹部素子形成予定領域、２３は凸部素子形成予定領域、
３１゜３３はレジスト膜、３２はＺｎＳ膜、３４はＩｎ
金属膜を示す。
不発萌司暮シクＴ宅膨副っ折面ｍ
手ネａＮｎ装ジオ２史腕例Ｉ号子面ｍ
第２図
４４０月ｎ１１１ｔｐ＋ａＬＸ；＊乞ｂＡｔ＞ｙｔ＋
はＱσ第３図
従来／ｌ装置ら断面図
第４図1 is a sectional view showing a first embodiment of the semiconductor device of the present invention, FIG. 2 is a plan view showing a second embodiment of the semiconductor device of the present invention, and FIGS. ) are sectional views for explaining the method of manufacturing the device of the present invention, and FIG. 4 is a sectional view showing the main parts of a conventional semiconductor device. In the figure, 11 is a CdTe substrate, 12 is l1g+-x Cdx T
epitaxial layer 13A, 13B, 13C are element formation regions 14A, 14B; 14C is an impurity introduced layer (N-type layer), 15 is an insulating film, 16
．． 17 is an In metal column, 21 is a compound semiconductor substrate, 22 is a concave element formation area, 23 is a convex element formation area,
31° 33 is a resist film, 32 is a ZnS film, 34 is an In
Shows a metal film. Unexploited Moeshi Kurashiku T house expansion sub-folding surface m Handne aNn Sojio 2 history arm example I No. child surface m Fig. 2 440 month n111tp+aLX; *beggar bAt>yt+
is Qσ Fig. 3 Cross-sectional view of conventional/l device Fig. 4
Claims (2)
方の半導体基板に形成した半導体素子を金属柱にて接続
形成した装置に於いて、 前記化合物半導体基板（１２）に素子形成予定領域（１
３Ａ、１３Ｂ、１３Ｃ）を交互に凹凸状に形成し、該凹
凸状領域、或いは凹部状領域に素子形成用不純物層（１
４Ａ、１４Ｂ、１４Ｃ）を設けたことを特徴とする半導
体装置。(1) In an apparatus in which a photoelectric conversion element formed on a compound semiconductor substrate and a semiconductor element formed on the other semiconductor substrate are connected by a metal pillar, an area (1) where the element is to be formed is formed on the compound semiconductor substrate (12).
3A, 13B, 13C) are alternately formed in a concave and convex shape, and an impurity layer for element formation (1
4A, 14B, 14C).
）を化合物半導体基板（１２）に列状、或いは千鳥状に
設けたことを特徴とする請求項１記載の半導体装置。(2) The planned element formation areas (13A, 13B, 13C)
) are provided on the compound semiconductor substrate (12) in rows or in a staggered manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63044801A JPH01218062A (en) | 1988-02-26 | 1988-02-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63044801A JPH01218062A (en) | 1988-02-26 | 1988-02-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01218062A true JPH01218062A (en) | 1989-08-31 |
Family
ID=12701529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63044801A Pending JPH01218062A (en) | 1988-02-26 | 1988-02-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01218062A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60158206U (en) * | 1984-03-30 | 1985-10-21 | 日本電気株式会社 | taxiway |
| JPS6330913A (en) * | 1986-07-24 | 1988-02-09 | Nec Corp | Guide path for unmanned car |
-
1988
- 1988-02-26 JP JP63044801A patent/JPH01218062A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60158206U (en) * | 1984-03-30 | 1985-10-21 | 日本電気株式会社 | taxiway |
| JPS6330913A (en) * | 1986-07-24 | 1988-02-09 | Nec Corp | Guide path for unmanned car |
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