JPH01216858A - Recording device - Google Patents

Abstract

PURPOSE:To enable high-speed recording by providing so many number of memories corresponding to simultaneously driven blocks, reading data from each memory at the same time, and transmitting such data to each block. CONSTITUTION:Generation circuits 14, 15 generate addresses for reading simultaneously, when a specified number(equal to a single line) of data are stored in memories 11,12. The generation circuits 14 and 15 generate addresses of 0 to 1,023 and those from 1,024 to 2,047 respectively. Accordingly, as soon as the data which is read from the memory 11 is transferred to a shift register of a printing block 16, the data which is read from the memory 12 is transferred to a shift register 19 of a printing block 17. As a result, the time required for transferring data to all the printing blocks (in this case, two blocks) is the same as the time required for transmitting data to a single printing block. When all the data equal to a single line is stored in the shift registers of the printing blocks, data equal to a single line are printed(recorded) on thermosensitive electrode paper.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a recording device typified by a thermal recording device using a line-type thermal head.

[Conventional technology]

FIG. 2 is a block diagram of a conventional thermal recording device. In the figure, 21 is a memory, which stores input data. 22 and 23 are a write address generation circuit and a read address generation circuit, respectively, which generate write addresses and read addresses for the memory 21. 24 and 25 are first and second print blocks, each having shift registers 26 and 27.

The generation circuit 22 generates write addresses from O to 2047, for example, and supplies them to the memory 21.

The memory 21 stores the input data at this write address. When a predetermined number (2048 pieces) of data is stored in the memory 21, the 1 generation circuit 23 is 0 or 62047
Generates the read address up to.

The data is supplied to the memory 21. As a result, the data stored in the memory 21 is read out serially and sequentially.

Print blocks 25 and 24 are connected to memory 21 in series. Therefore, among the data read from the memory 21, 1024 data from addresses 0 to 1023 are stored in the shift register 26 of the print block 24 at address 1.
1024 pieces of data from 024 to 2047 are stored in the shift register 27 of the print block 25, respectively. When a predetermined number (1024 pieces) of data is stored in each register.

The printing blocks 24 and 25 simultaneously perform printing corresponding to the data stored in the shift registers 26 and 27. In this way, printing for one line (2048 dots) is completed.

Thereafter, new data is input in the same manner, and the next line is sequentially printed.

[Problem to be solved by the invention]

In this way, conventional devices connect multiple print blocks to the memory in series, read one line of data serially, and distribute the data corresponding to each print block, so the data transfer time is reduced. It has the disadvantage of being long. Therefore, since the recording speed is slowed down by the transfer time, it has been difficult to apply it to a gradation recording method that requires data transfer several dozen times to print one line.

Therefore, the present invention realizes a recording device that enables faster recording.

[Means to solve the problem]

The recording device of the present invention includes a write address generation circuit that generates a write address, and a first address of input data.
A first memory that stores data in a range of , at a write address generated by a write address generation circuit, and a second memory that stores data in a second range of input data at a write address generated by a write address generation circuit. a second memory; a first read address generation circuit that generates a read address for the first memory; and a second read address that simultaneously generates a read address for the second memory. It includes a generation circuit, a first block that performs recording corresponding to data read from the first memory, and a second block that performs recording corresponding to data read from the second memory.

[Effect]

The write address generation circuit first generates a write address for the first memory, and then generates a write address for the second memory. As a result, among the serially input data, the first range of data is stored in the first memory, and the subsequent second range of data is stored in the second memory. - Since the read address generation circuit and the second read address generation circuit of the power cylinder 1 generate read addresses at the same time, the data stored in the first memory and the second memory are simultaneously stored in the first block and the second block. Each is transferred to a block.

Therefore, the time required to transfer one line of data to each block can be shortened.

〔Example〕

FIG. 1 is a block diagram when the recording apparatus of the present invention is applied to a thermal recording apparatus. In the figure, 11 and 12 are memories each having a different address. Reference numeral 13 denotes a write address generation circuit that generates write addresses for the memories 11 and 12.

14 and 15 are read address generation circuits.

A read address for memory 11 and memory 12 is generated, respectively. Reference numerals 16 and 17 designate printing blocks that perform predetermined printing on a first range and a second range on one line of thermal recording paper (not shown) as a recording medium. Reference numerals 18 and 19 are shift registers built into each print block 16 and 17.

Next, the operation will be explained.1 Data output from a circuit (not shown) is supplied to both memories 11 and 12 at the same time. - The force generating circuit 13 sequentially generates addresses from 0 to 2047, for example. Of these, 0 to 1023 are addresses of the memory 11, and 1024 to 2047 are addresses of the memory 12.
Each address is set as the address of . Therefore, the first 1024 pieces of data input are stored in the memory 11, and the next 1024 pieces of data input are stored in the memory 12.

All data of a predetermined number (one line) are stored in memories 11 and 12.
0 generation circuit 14 generates a read address from 0 to 1023.
The 1 generation circuit 15 generates addresses from 1024 to 2047.
The addresses up to this point are generated respectively. Therefore, data read from memory 11 is transferred to shift register 18 of print block 16, and at the same time data read from memory 12 is transferred to shift register 19 of print block 17. As a result, the time required to transfer data to all of the multiple (in this case two) print blocks is 1
The time required to transfer data to one print block is the same.

When all the data for one line is stored in the shift register of each print block, printing (recording) for one line is simultaneously performed on the thermal recording paper.

Thereafter, new data is input in the same manner, and the next line is sequentially printed.

As mentioned above, one line has N numbers (in the above example, there are 2
In the case where the print block is composed of N (2) print blocks, N (2) memories can be provided corresponding to each print block. However, if N print blocks are divided into a predetermined number and driven in one time division, it is only necessary to provide a number of memories corresponding to the print blocks that are driven simultaneously.

〔Effect of the invention〕

As described above, according to the present invention, the number of memories corresponding to the blocks to be driven simultaneously is provided, and data is simultaneously read from each memory and transferred to each block, so that the data transfer time can be shortened. This enables high-speed recording.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a recording apparatus according to the present invention, and FIG. 2 is a block diagram of a conventional recording apparatus. 11.12...Memory 13...Write address generation circuit 14.15...Read address generation circuit 16.17
...Print block 18.19...Shift register 21...Memory 22...Write address generation circuit 23...Read address generation circuit 24.25...Print block 26.27...Shift register Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Scope of Claims] A write address generation circuit that generates a write address; a first memory that stores a first range of data among input data at a write address generated by the write address generation circuit; a second memory that stores a second range of data out of the data in a write address generated by a write address generation circuit; a first read address generation circuit that generates a read address of the first memory; a second read address generation circuit that generates a read address for the second memory simultaneously with the first read address generation circuit; and a first block that records data corresponding to data read from the first memory. , a second block that performs recording corresponding to data read from the second memory.