JPH01216546A - Mounting structure of ic chip on board - Google Patents
Mounting structure of ic chip on boardInfo
- Publication number
- JPH01216546A JPH01216546A JP4170288A JP4170288A JPH01216546A JP H01216546 A JPH01216546 A JP H01216546A JP 4170288 A JP4170288 A JP 4170288A JP 4170288 A JP4170288 A JP 4170288A JP H01216546 A JPH01216546 A JP H01216546A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- board
- wirings
- wiring
- wavelength
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 17
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 15
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 239000011521 glass Substances 0.000 abstract description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052753 mercury Inorganic materials 0.000 abstract description 2
- 239000002245 particle Substances 0.000 abstract description 2
- 239000005011 phenolic resin Substances 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- 238000010521 absorption reaction Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000007650 screen-printing Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
ｒ発明の利用分野」
この発明は、低コスト化、軽量化を図るために、サーマ
ルヘッド用発熱基板、イメージセンサ−用受光素子基板
、液晶表示基板上に直接半導体チップを搭載し、該素子
を駆動させる半導体装置を実装する新規な構造を提案す
るものである。[Detailed Description of the Invention] [Field of Application of the Invention] This invention is directed to the production of semiconductor chips directly on heat generating substrates for thermal heads, light receiving element substrates for image sensors, and liquid crystal display substrates in order to reduce costs and reduce weight. This paper proposes a new structure in which a semiconductor device is mounted to drive the device.
「従来の技術」
従来、サーマルヘッド、イメージセンサまたは液晶表示
基板等の電子デバイスを駆動する駆動回路はこれら電子
デバイスとは別に設けられたＰボード上に金属膜により
所定の回路を設け、そのＰボードの回路上に、パッケー
ジＩＣをハンダ付は等により、装着してＰボードの駆動
回路を完成しこのＰボードと、電子デバイスとをＦＰＣ
（フレキシブル・プリント・サーキット）等の接続を介
して接続を行っていた。このような場合、Ｐボード、接
続リード等の部品数が増し電子デバイスの製造コスト高
をまねいていた。"Prior Art" Conventionally, a drive circuit for driving an electronic device such as a thermal head, an image sensor, or a liquid crystal display board is provided with a predetermined circuit using a metal film on a P board provided separately from these electronic devices. A package IC is mounted on the circuit of the board by soldering, etc. to complete the drive circuit of the P board, and this P board and electronic device are connected to an FPC.
(flexible printed circuit), etc. In such a case, the number of components such as the P-board and connection leads increases, leading to an increase in the manufacturing cost of the electronic device.
また、このＰボードを省略し、電子デバイスが形成さて
いる基板上に直接駆動回路を描き、この基板に描かれた
配線に直接ＩＣチップを装着する技術が開発された。こ
の技術としては、ＩＣチッブをＴＡＢ法と呼ばれるポリ
イミド系の樹脂フィルムをベースとするフレキシブルな
基板上の配線に接続し、フィルム端部に設けられた電極
端子を表示基板上の配線の電極部に接続する方法、又フ
リップチップ法と呼ばれるＩＣのチップのバットにハン
ダのバンプを設け、かつ対抗する電極にハンダメツキを
設けてバンダーハンダ接続を行う方法等がある。In addition, a technique has been developed in which the P-board is omitted, a driving circuit is drawn directly on the substrate on which the electronic device is formed, and an IC chip is directly attached to the wiring drawn on this substrate. This technology involves connecting an IC chip to wiring on a flexible substrate based on a polyimide resin film using the TAB method, and connecting electrode terminals provided at the edges of the film to the electrodes of the wiring on the display substrate. There is also a method called the flip-chip method, in which a solder bump is provided on the butt of an IC chip and a solder plating is provided on the opposing electrode to perform bander solder connection.
このうち、ＴＡＢ法は軽量化を目的とした方法であるが
、使用するポリイミドテープに金属配線を形成するのに
コストがかかりすぎることが問題となっている。Among these, the TAB method is a method aimed at reducing weight, but the problem is that it costs too much to form metal wiring on the polyimide tape used.
又、フリップチップ法は熱を加えてＩＣチップと基板と
の接続を行い一度ハンダを溶かすので、ハンダバンプの
形成は隣接するバンプ同志のショートを回避する為にＩ
Ｃ基板上に形成する電極の集積度を上げられないことが
問題点である。In addition, in the flip-chip method, heat is applied to connect the IC chip and the board and once the solder is melted, the formation of solder bumps requires an I
The problem is that the degree of integration of electrodes formed on the C substrate cannot be increased.
さらにＩＣチップの電極パッド部分のみに金属性のバン
プを形成し、平らな基板上の電極部に圧接させて接着剤
により、固着する方法が知られている。この方法の場合
、バンプを配線に圧接するのみであるためバンプおよび
配線の高さの均一性が要求されるため、通常プロセスに
よる場合では接続部のコンタクト不良が多数発生し、高
さを均一にそろえるには、高度な技術が必要となりその
ため製造コストも高くなるという問題点があった。Furthermore, a method is known in which metal bumps are formed only on the electrode pads of an IC chip, and the bumps are pressed against the electrodes on a flat substrate and fixed with an adhesive. In this method, since the bumps are only pressure-bonded to the wiring, uniformity in the height of the bumps and wiring is required. Therefore, when using a normal process, many contact failures occur at the connection part, and it is difficult to make the height uniform. There was a problem in that highly sophisticated technology was required to prepare them, which led to high manufacturing costs.
本発明は前述の従来方法の問題点を解決するものであり
、低コストで製造歩留りの高い、ＩＣチップの実装構造
を提供するものであります。The present invention solves the problems of the conventional method described above, and provides an IC chip mounting structure that is low cost and has a high manufacturing yield.
本発明の構成は、電子デバイス等が形成された基板上に
導電性ペースト等により形成された金属配線を有し、そ
の金属配線のうち少なくともＩＣチップの金属バンプと
接する部分が、凹凸形状を有しており、ＩＣチップの金
属バンプに埋まっている形で、電気的に接続されている
ことを特徴とするものであります。The structure of the present invention has a metal wiring formed of a conductive paste or the like on a substrate on which an electronic device or the like is formed, and at least a portion of the metal wiring that contacts a metal bump of an IC chip has an uneven shape. It is characterized by being embedded in the metal bumps of the IC chip and electrically connected to it.
すなわちＩＣチップの金属バンプの高さが不揃いであっ
ても凹凸形状を持つ配線の凸部が高さの高い金属バンプ
に埋まるような形で圧接されるので、すべての金属バン
プと配線との接続が可能となるものであります。In other words, even if the heights of the metal bumps on the IC chip are uneven, the convex parts of the uneven wiring are pressed together so that they are buried in the taller metal bumps, so that all the metal bumps and wiring can be connected. is possible.
以下、実施例により本発明を説明する。The present invention will be explained below with reference to Examples.
「実施例」 第１図に本発明の断面構造を示す。"Example" FIG. 1 shows a cross-sectional structure of the present invention.
１．１−一厚で、３６５ｎ−の波長を透過するガラス基
板（１）ではコーニング１１７０５９を用いた上にＣｕ
からなる粒子を含んだフェノール樹脂ペーストをスクリ
ーン法により２５μｍ程度の厚さの印刷を行った後、１
５０℃Ｎ！３０分の焼成により電気配線ｅ）を設けた。1.1- For the glass substrate (1) that is one thickness and transmits a wavelength of 365n-, Corning 117059 is used and Cu
After printing a phenolic resin paste containing particles consisting of
50℃N! Electrical wiring e) was provided by firing for 30 minutes.
３６５ｎｓｅに光に吸収を持つ光硬化型エポキシ樹脂（
３）を、その出力端るメツキ法で設けた金よりなるバン
プ（５）を有する半導体チップ（４）上にディスペンス
し、該配線との位置合わせを行った後に、１２〜１３、
５Ｋｇ／ｃ■冨の荷重をかけて、基板（１）と半導体チ
ップ（４）を密着させた。A photocurable epoxy resin that absorbs light at 365nse (
3) is dispensed onto the semiconductor chip (4) having bumps (5) made of gold provided by the plating method at the output end, and after alignment with the wiring, steps 12 to 13 are performed.
The substrate (1) and the semiconductor chip (4) were brought into close contact with each other by applying a load of 5 kg/cm2.
その後、３６５ｎ−に発光ピークを有する高圧水銀ラン
プにより２０００ｍＪ／ｃｍ”のエネルギーを基板側よ
り照射し、ＩＣチップの実装を行った。Thereafter, an IC chip was mounted by irradiating energy of 2000 mJ/cm" from the substrate side using a high-pressure mercury lamp having an emission peak at 365 n-.
本実施例においては、配線（２）の凹凸を設ける手段と
しては、スクリーン印刷法によって配線（２）を形成す
ることで行った。In this example, the wiring (2) was formed by a screen printing method as a means for providing unevenness in the wiring (2).
すなわち、スクリーン印刷の版のメツシュがあるのでメ
ツシュに対応する凹凸が配線部に形成される。That is, since there is a mesh of the screen printing plate, unevenness corresponding to the mesh is formed in the wiring portion.
その他の方法によっても配線の接続部分に凹凸を形成す
ることが可能であるが、このスクリーン印刷による方法
が最も簡単で低コストな作製方法であった。Although it is possible to form irregularities on the connection portion of the wiring by other methods, this method using screen printing was the simplest and lowest cost manufacturing method.
（効果〕
本発明の構成をとることにより安価で製造歩留りの高い
ＩＣの実装を実現することができた。(Effects) By employing the configuration of the present invention, it was possible to realize IC mounting at low cost and with high manufacturing yield.
第１図は本発明の構造の概略断面図を示す。 FIG. 1 shows a schematic cross-sectional view of the structure of the invention.
Claims (1)
駆動用回路と前記駆動用回路を構成する配線とを有する
基板において、前記配線はＩＣチップの金属バンプと接
する部分において微小な凹凸形状を有しており、ＩＣチ
ップの金属バンプと圧着して電気的な接続を行い、前記
ＩＣチップは接着剤によって基板に装着されていること
を特徴とする基板上のＩＣチップの実装構造。 ２、特許請求の範囲第１項において、前記ＩＣチップの
金属バンプに前記配線の微小な凸部が埋まる状態で接続
されていることを特徴とする基板上のＩＣチップの実装
構造。[Scope of Claims] 1. A substrate having an electronic device, a driving circuit for driving the electronic device, and wiring constituting the driving circuit, wherein the wiring has a microscopic structure in a portion in contact with a metal bump of an IC chip. Mounting of an IC chip on a substrate, characterized in that the IC chip has a convex and concave shape and is electrically connected by pressure bonding to a metal bump of an IC chip, and the IC chip is attached to the substrate with an adhesive. structure. 2. The structure for mounting an IC chip on a substrate according to claim 1, wherein the wiring is connected to a metal bump of the IC chip in such a manner that a minute convex portion thereof is buried therein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4170288A JPH01216546A (en) | 1988-02-24 | 1988-02-24 | Mounting structure of ic chip on board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4170288A JPH01216546A (en) | 1988-02-24 | 1988-02-24 | Mounting structure of ic chip on board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01216546A true JPH01216546A (en) | 1989-08-30 |
Family
ID=12615756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4170288A Pending JPH01216546A (en) | 1988-02-24 | 1988-02-24 | Mounting structure of ic chip on board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01216546A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6586877B1 (en) | 1999-01-21 | 2003-07-01 | Hamamatsu Photonics K.K. | Electron tube |
-
1988
- 1988-02-24 JP JP4170288A patent/JPH01216546A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6586877B1 (en) | 1999-01-21 | 2003-07-01 | Hamamatsu Photonics K.K. | Electron tube |
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