JPH012157A - Data transfer abnormality detector of data recording device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data recording device, and more particularly to a means for detecting a data transfer abnormality when data is transferred with another device using a half-interlock method.

[Prior Art] Half-interlock type data transfer is controlled by a reference clock that is sent by the side that controls the timing of data transfer without receiving a response from the other party, and a response clock that the other party follows and sends back.

FIGS. 2(a) and 2(b) show an example of the operation timing of the reference clock and response clock for data transfer using the half-interlock method. When the side that controls the data transfer timing receives data, the response clock 13 becomes the strobe signal for the input data 14, and the clock 12 acts as a f-ta request signal that instructs the transfer timing. When the side that controls the timing transmits data, the reference clock 12 indicates the timing of transfer and serves as a strobe signal for the output data 11, and the response clock 13 acts as a confirmation signal to know that the output data has arrived. clock 12
is sent in advance, without waiting for a response from the other party, at a certain period of time Tc, and the response clock follows it and is sent at the same period after a delay of time Td, which is determined by the transfer distance between the devices performing data transfer and the data processing capacity of both devices. It will be returned at Tc. Conventionally, this type of data transfer abnormality detection has been performed by comparing the counts of the reference clock 12 and the response clock 13, and the conventional data transfer abnormality detector operates under the control of a data transfer control section.
A counting section that counts the reference clock and response clock separately and outputs each counted value as a pair, and a comparison and verification unit that compares and matches the pair of counted values at the timing specified by the control signal and generates an abnormal signal if they do not match. It consisted of a judgment department.

FIGS. 3(a), 3(b), and 3(c) show its functional blocks and operation timing corrector.

In FIG. 3(a), the data transfer control unit 1 is a block that has the original function of controlling data transfer and performs control regarding the original data transfer.

h[Number 7 is the control signal 17 output by the data control circuit 1
counts the effective amount reference clock 12 and outputs the counted value 71.Similarly, the response clock 13 is counted and the counted value 72 is output. Further, when the control signal 17 becomes invalid, each count value is initialized. The comparison/verification/judgment unit 8 is faced with the situation where the data transfer is completed and the control signal 17 becomes invalid] The numerical value 71 and the h4 numerical value 72 are compared and verified, and if they do not match, an abnormality signal 18 is sent.
is activated and reported to the data transfer control unit 1. FIG. 3(b) shows an example of the operation when the process ends normally, and FIG. 3(C) shows an example of the operation when the process ends abnormally.

[Problems to be Solved by the Invention] The above-mentioned conventional method of checking the counted value after the transfer is completed has the drawback that even if a timing problem occurs during the transfer, if the counted value finally matches, no abnormality can be detected. There is.

Furthermore, even if an abnormality can be detected, there is a drawback that there is a large time delay from the time the abnormality occurs until it is detected.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer abnormality detector that solves the above-mentioned problems.

[Means for Solving the Problems] The present invention performs data transfer with other devices using a half-interlock method, and is the side that controls the transfer timing, and uses a constant periodic standard that serves as a standard for data transfer. A data transfer abnormality detection device that is attached to the data transfer control unit of a device that sends a clock and controls data transfer by receiving a response clock of the same period that is returned in response to the clock, and operates with a control signal from the data transfer control unit. In the device, the time required for the response clock to be sent back with respect to the reference clock is measured, and the time difference is corrected to create a corrected reference clock and response equivalent to the reference clock, in which the corresponding change timings are regulated within a certain period of time. a timing correction section that generates a correction response clock equivalent to the clock; a g4 number section that separates the correction reference clock and correction response clock generated by the timing correction section and outputs each value as a pair; A comparison/verification/determination unit that compares and collates the pair of count values for an arbitrary number of bits between corresponding bits, sequentially determines whether or not they match at the data transfer cycle, and generates an abnormal signal when a discrepancy occurs. A data transfer abnormality detector for a data recording device, characterized in that the data transfer abnormality detector has the following features:

[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 1(a), the data transfer abnormality detector 2 of the present invention measures the time until the response clock 13 is returned with respect to the reference clock 12, corrects the time difference, and makes the corresponding change timing constant. a timing corrector 3 that generates a corrected reference clock 31 equivalent to the reference clock 12 and a corrected response clock 32 equivalent to the response clock 13, which are regulated within time; and a corrected reference clock generated by the timing corrector 3. 31
and correction response clock 32 separately and output each counted value as a pair, and a counting unit 4 that compares and collates the pair of counted values with respect to an arbitrary number of bits between corresponding bits, and calculates the match/mismatch in the data. It is comprised of a comparison and verification determination section 5 that sequentially performs determination at the transfer cycle and generates an abnormal image @16 when a mismatch occurs.

In FIGS. 1(a) and (b), the timing correction section 3
measures the delay time until the response clock 13 is returned from the reference clock 12, corrects the time difference, and sets the corresponding change timing to a correction standard equivalent to the reference clock 12 regulated within a certain time. A correction response clock 32 equivalent to clock 31 and response clock 13 is generated.

The counting unit 4 counts the correction reference clock 31 and the correction response clock 32 separately according to the designation of the control signal 15, and outputs the count value 41 of the correction reference clock 31 and the count value 42 of the correction response clock 32 to the comparison comparison determination unit 5. do. Further, the count value is initialized by specifying the control signal 15.

The correction reference clock 31 and the correction response clock 32 are corrected so that they change at approximately the same timing, and the pair of old teaching value 41 and count value 42 output from the S1 number section 4 also change at the same timing. The comparison/verification/judgment unit 5 successively compares the IT numerical value 41 and the count value 42 at a timing synchronized with the correction reference clock 31, and upon detecting a mismatch, immediately activates the abnormality image @16 and reports it to the data transfer control unit 1. In addition, in the timing correction section 3, the reference clock 12
The delay of the response clock 13 to the timing corrector 3
If the capacity of the clock is exceeded or if no response clock 13 is returned at all, a no-response abnormality signal 33 is generated to issue a warning.

In addition to the abnormality due to the discrepancy of the count value 41.42, the comparison verification determination unit 5 also detects the abnormal image @1 when receiving the no-response abnormal image @33.
6 becomes active and reports to the data transfer control unit 1.

FIG. 4 shows an embodiment of the timing corrector 3. As shown in FIG.

In this embodiment, the response clock 1 to the reference clock 12 is
This control clock has a frequency four times that of the reference clock 12 on which the data transfer control section controls the timing of the reference clock 12 in order to measure the delay time of No. 3. The control unit @15b is used as a time base. The D-type F/Fs 301 to 306 are shift register circuits operated by the control signal 15b, and shift the reference clock 12. When the period of the reference clock 12 is tc, D type F/F
Delayed reference clocks having a delay of 1/4 fc relative to the reference clock 12 are output to 301 to 306 in numerical order. AND gates 315 to 319 are reference clock 1
Starting from the shipping start point of 2, 1/4 between 11/d tc
tc and opens a 1/dtC width window in numerical order of AND gates 315 to 319. These and gate 3
Outputs 15 to 319 become D inputs of D type F/Fs 308 to 312. Response clock 1 for reference clock 12
When 3 is returned, the D type F/F 307 is set at the same time as the response clock 13 arrives, and maintains this state until the end of the transfer. The rise of the output of the D type F/F 307 indicates the arrival point of the response clock 13, and the output is
The window states set by the aforementioned AND gates 315 to 319 are input to the C inputs of the type F/Fs 308 to 312. Therefore, when the response clock 13 arrives, the F/F whose D input window is open among the D type F/Fs 30a to 312, that is, the reference clock 1
The F/F corresponding to the delay of the response clock 13 with respect to 2 is set. When any of the D-type F/Fs 308 to 312 is set, the AND gates 320 to 324 and the OR gate 325 convert the set F/F, that is, the delay clock according to the delay of the response clock, to the D-type F/F 301 described above. 306 is selected and outputted as the correction reference clock 31. This correction reference clock 3
1 is 1/4tc with respect to the response clock 13 in order to absorb the operation variations of the circuit elements that constitute the timing correction section.
A delayed reference clock delayed by ~1/2tC is selected. Therefore, in order to reduce the difference, the response clock 13 is delayed by the delay line 314 to become the correction response clock 32.

By delaying by 3/8tc, it is possible to obtain the correction reference clock 31 and correction response clock 32 in which the difference in the corresponding change timing is within ±1/8tCmaX.

Figure 5 shows 1/2tC to 3/8t with respect to the reference clock 12.
An example of the operation when the response clock 13 is returned with a delay within the range of c is shown. The correction ability of the embodiment of FIG. 4 is such that the delay of the response clock 13 with respect to the reference clock 12 is 117.
When it is up to 4tc and exceeds it, D type F/F307 is not set to Sera 1~ even when the last window closes, and AND gate 32 is activated at the timing when the last window closes.
When the output of 6 becomes active, the control signal 15 at that time
D type l"/F313 is set at a. Its output is the no-response abnormal signal 33. 34 to 38 indicate the output signals of the AND gates 32o to 323. In the embodiment shown in FIG. 4, the correction ability is 11. Although the delay is up to /4 tc, the ability to correct the delay can be improved by increasing the number of shift register stages, the number of windows, and the number of selection gates with the same configuration.

Further, the correction accuracy can be improved by shortening the clock cycle of the time-based control signal 15b. FIG. 6 shows an embodiment of the counting section 4 and the comparing and matching determining section 5. The counting unit 4 is composed of general 4-bit binary counters 401 and 402, and the binary counter 401 measures the number of clocks of the correction reference clock 31, and the binary counter 4
02 repeatedly counts the number of clocks of the correction response clock 32 between 0 and 15.

In the configuration of the present invention, it is not necessary to compare the total number of transfer locks and it is possible to detect an abnormality with just one bit. However, in the embodiment shown in FIG. In order to practically eliminate the probability that the clock is counting period x n + 1, the lower 2 bits are compared and the old 2° bits 41a and 21 bits 41b of the binary counter 401 count value and the biprecounter 4 are compared.
Count value 42 of 02 bit 42a and 21 bit 42
b is sent to the comparison/verification/judgment section 5. Also, the control signal 15a
When becomes invalid, the count value is initialized and no counting is performed.

In the comparison/verification/judgment section 5, the two ita exclusive OR gates 501 and 502 and the OR gate 503 are the 2 bits 41a, 20 bits 42b and 2 of the two count values.
A logic is constructed to check whether bit 41b and 21 bit 42b match, and when a mismatch occurs, a mismatch signal 51 becomes active. The inverter 504 and the D-type F/F 505 generate a mismatch abnormality signal 52 which is taken in and shaped into a waveform at a timing when the count value is stable and the mismatch signal @51 is established. The OR gate 506 activates the abnormality signal 16 and reports it to the data transfer control section 1 when either the mismatch abnormality signal 52 or the non-response abnormality signal 33 generated in the timing correction section described above becomes active. Figure 7(a), (
b) shows the operation when there is a shortage of responses and when there is an extra response in this embodiment.

[Effects of the Invention] As explained above, the present invention generates a corrected reference clock and a corrected response clock in which the reference clock and the response clock are corrected so that they are equivalent and change at the same timing, and uses them as targets for counting and comparison. By using the reference clock as a comparison timing clock, even if the delay time from the reference clock to the return of the response clock differs depending on the processing capacity of the other device and the transfer distance, it can be quickly resolved when a timing problem occurs during data transfer. It has the effect of detecting abnormalities.

Therefore, there is no large time delay between the occurrence of an abnormality and the detection of the abnormality as in the conventional case, and there is an effect that unnecessary data transfer after the occurrence of an abnormality can be omitted.

Furthermore, when the number of bits to be compared in the count values is the same, there is an effect that the probability of failure to be detected can be extremely reduced.

[Brief explanation of drawings]

FIG. 1(a) is a functional block diagram showing the configuration of the present invention, FIG. 1(b) is an operation timing chart, and FIG. 2(a)
, (b) is an explanatory diagram of the data transfer timing of the half-in clock method, Figure 3 (a) is a functional block diagram of a conventional data transfer abnormality detector, and Figures 3 (b) and (C) are operation timing charts. 4 is a block diagram showing an embodiment of the timing correction section of the data transfer abnormality detector of the present invention, and FIG. 5 is a timing diagram of an example of the operation of the timing correction section of FIG. FIG. 6 is an operation timing chart diagram illustrating an embodiment of the counting section and comparison/verification/judgment section of the data transfer abnormality detector of the present invention when detecting an error. 301-313.505...D type flip-flop 314...Delay line 315-324...3-person gate 325...
5-man power OR gate 326...And gate 401, 402...4-bit binary counter 501
, 502... Ita exclusive or gout 503, 5
06...OR gate 504...Inverter

Claims (1)

[Claims] (1) Data transfer with other devices is performed using a half-interlock method, and the side that controls the transfer timing sends a reference clock with a fixed cycle that serves as the reference for data transfer, and returns it in response. In a data transfer abnormality detector that is attached to the data transfer control section of a device that controls data transfer in response to a response clock of the same cycle as that of Measures the time until the clock is returned and corrects the time difference to generate a corrected reference clock equivalent to the reference clock and a corrected response clock equivalent to the response clock, whose corresponding change timings are regulated within a certain time. a timing correction section; a counting section that separately counts the correction reference clock and the correction response clock generated in the timing correction section and outputs each count value as a pair; A comparison and verification determination section that compares and verifies the number of bits of the data, sequentially determines whether or not they match in a data transfer cycle, and generates an abnormal signal when a discrepancy occurs. Transfer anomaly detector.