JPH012156A - Data retention control device for non-volatile memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention provides an M-door device that writes data to and reads data from a non-volatile memory, and when an unexpected power cut occurs, even data that is being written is You can reduce the instability of written data by writing to memory correctly and then finishing the process, or by writing up to a predetermined amount of data, and then interrupting writing of unstable data and storing only correct data. I'm trying to remove the condition.

[Industrial application field]

The present invention relates to a data retention control device for non-volatile memory, and in particular, a data retention control device that is capable of storing data in the non-volatile memory without destroying data that is being written to a well-defined point in the event of an unexpected power cut. This relates to a control device.

[Conventional technology]

Even if the power supplied from the outside is cut off,
BACKGROUND OF THE INVENTION Nonvolatile memories capable of retaining data stored by a bank-up power source (battery) within a device are well known. In the nonvolatile memory control device according to the prior art.

In order to protect memory data, the external power supply voltage supplied to the memory is constantly monitored by a voltage monitoring device, and when the voltage drop falls below a predetermined value outside of a predetermined sequence, the condition is detected. Once detected, the chip selection signal for the memory element is turned off or the write enable signal is turned off to control the memory data so that it is not destroyed.

[Problem that the invention seeks to solve]

However, in the non-volatile memory control device according to the above-mentioned conventional method, control is performed to control the detection signal generated by detecting an external power supply voltage drop due to a cause other than the normal predetermined power-off sequence and the data to the memory. The signals are not directly related in terms of timing, so the memory chip select signal or write enable signal is
It is turned off by the detection signal and is controlled without being temporally related to the control signal. Therefore, when writing to memory is being performed when the power is unexpectedly cut off, the width of the write pulse becomes unstable, and as a result, the data written to memory is half-finished. .

On the other hand, if data written to memory in such an unstable state is continuously output from the stored address when the external power supply is restored, it is generally detected by an error detection code. , is now detected as an error. However, if the read data is written in a correlation with the error detection code that makes correct detection incorrect, it will be considered to be correct data and will not be detected as error data. Become.

Furthermore, when the information being written to the memory is not data but information with special properties such as flag information or a pointer.

The information read later may not only result in a read error, but may also result in all data in the memory area specified by the flag information or pointer being an error, or a specific range of memory area being an error or being unusable. In some cases, it became.

[Means for solving problems]

The present invention solves the above problems. FIG. 1 is a basic configuration diagram of the present invention. When the low DC power applied to the control means of the non-volatile memory is stably supplied, the first
There is a power supply control circuit (1) that generates a first signal (PWRDY0) that takes a value of , and takes a second value when an unexpected power cutoff occurs, and a second value of the first signal. a second signal (PWRDY1) obtained by synchronizing with the system clock and delaying the first signal.
The third signal (PWD
OWN) and cuts off the memory write enable signal at the falling edge of the signal, and after the third signal is generated, the external power supply is cut off. a fourth signal (PWOF) that changes from the first value to the second value when the low DC power source drops to a predetermined value;
There is a voltage monitoring circuit that generates F), and when the power is unexpectedly cut off, the write enable signal is cut off at the falling edge of the third signal to ensure that the data being written is correct via the gate circuit (4). The data is controlled so that it is stored in memory up to the specified location.

[Effect]

In FIG. 1, a second value (
The third signal (P) generated from the flip-flop circuit in the memory control cutoff circuit (2)
a fourth signal (P) that changes from the first value detected by the voltage monitoring circuit (3) to the second value;
Hold the write enable signal until the falling edge of the third signal, and then turn off the system clock at the second value (falling edge) of the fourth signal, before WOFF) becomes the second value. The data being written is interrupted at well-defined points, allowing the data to be stored in the memory in a stable state.

〔Example〕

FIG. 2 shows the configuration of the embodiment of the present invention, and FIG. 3 shows the timing of each signal generated from each part of the device.

In FIG. 2, 1 is a power supply control circuit which generates a high DC power supply voltage from an external AC power supply and then generates a low DC power supply voltage V.
Generates the cc and PWRDYO signals. Reference numeral 2 denotes a memory control cutoff circuit, which outputs PWRDYI obtained by delaying the PWRDYO signal via a delay device 13.
It has a power cutoff detection circuit 5 and a logic gate circuit 6, which are made up of first and second flip-flops that generate a PWDOWN signal from the PWRDYI signal using the PWRDYI signal. 3 is a voltage monitoring circuit that monitors and detects a state in which the low DC power supply voltage drops to a predetermined value when the external AC'FiiJ is cut off. 7 is a data buffer, 8 is an AND gate circuit, 9 is an open collector circuit, 10 is a non-volatile memory, 11 is a bank up power supply (panteri), 12 is a backup power source using the bank up power supply, 13 is a delay device, and 4 is a A memory control circuit is shown.

4 shows a detailed diagram of the power supply control circuit 1 of FIG. 2, and FIG. 5 shows a detailed diagram of the memory control cutoff circuit 2.

Next, the operation of the apparatus of the present invention configured as shown in FIG. 2 will be explained with reference to the timing shown in FIG.

In the power supply control circuit 1, an AC power supply (for example, 200v)
An iDC power supply voltage (for example, 250V) is generated from the iDC power supply voltage (for example, 250V), and this is lowered to a low DC power supply voltage (for example, 5V) and output. is applied to the cutoff detection circuit 5 in the memory control cutoff circuit 2, and PWDOWN
Generate a signal. It should be noted that the PWRDYO signal is generated when the low DC power supply voltage Vcc is stabilized by the high DC power supply rising to a certain value, and is turned off with some delay when there is an unexpected interruption of the AC power supply. Therefore PWRDYl(
No. 8 will also be turned off after a certain time delay from PWRDYO. P
The WDOWN signal is a signal generated from the falling relationship between PWRDYO and PWRDYI, and the chip selection signal CS generated from the memory control circuit 4 is controlled from on to off at the falling edge of this signal. ing. The chip selection signal CS and the CUTC8 signal generated from the memory control cutoff circuit 2 to turn off the chip selection signal are applied to one input of the open collector circuit 9 via the AND gate circuit 8. .

The other input of the circuit 9 is connected to receive the output from the voltage monitoring circuit 3. and voltage monitoring circuit 3
is the value 5 just before other circuits start malfunctioning when the AC power is cut off or the T4# voltage drops below a predetermined value. For example, 5 indicates a state where the low DC power supply voltage is stable. The open collector circuit 9 outputs an off signal when the voltage drops from 4.5■ to 4.5■.As long as the input is at O level, the output of the open collector circuit 9 is stable, so the output is connected to the pull amplifier resistor. The voltage V of the backup voltage 1i1t via R. By connecting it to , the memory chip selection signal cs' is turned off after PWOFF.

The CUTC3 signal turns off the chip select signal.

Since there is variation in each memory leaf, the rise time also changes, but it is turned off at the fall of the PWDOWN signal. On the other hand, the memory write enable signal is.

CUTC3 before the PWOFF signal becomes less than the predetermined value.
The signal is turned off at the end of writing one data to the memory or before writing the next data to prevent unstable data writing or data corruption. After being stored in memory in this way, PWOFF
When the signal is turned off, the system clock is also cut off.

After Vcc is turned off, ■ from the back amplifier voltage 'a11. The memory is bank-amplified by minimizing memory power consumption. Needless to say.

Under conditions where no unexpected power cutoff occurs, the chip selection signal C8 from the memory control circuit 14 is output to the AND gate circuit 8.
or via the oven collector circuit 9.

It is supplied as the above-mentioned chip selection signal C3', and read/write is performed.

In addition, as shown in FIG. 4, ACii [low DC after cutoff]
The holding time of the power supply is determined by the capacitance values of the illustrated capacitors C+, Ct in the high DCiittA and low DC power supplies. In addition, in the device of the present invention, PWRDYO
The PWRDYI signal is generated by delaying the signal by a predetermined time (1), but this delay time is the time to secure the write enable signal to the memory.On the other hand, the delay in the memory control cutoff circuit 2 in FIG. τ = ((FF-A) + (FF-B) + (CS on period) + (FF-C) + × (memory cycle time). However, the memory group is one leaf and does not increment. Make it not exist.

In this way, as long as the PWRDYI signal is on, the chip selection signal cs' is on, and the PWRDYI signal is on.
When the I signal is turned off, cs' is turned off and the R/W operation to the memory is stopped. Note that in reality, when the CUTC3 signal is immediately turned off by the PWRDYI signal, an inconvenient phenomenon 1, for example, noise is generated, but in order to prevent this from occurring, the PWRDYI signal and C
A predetermined delay is provided between the signal and the UTC3 signal.

〔Effect of the invention〕

As described above, according to the present invention, when the AC power supplied to the device is unexpectedly cut off.

Before the low DC power supply voltage obtained from the AC power supply drops below a predetermined value, data is stored in the memory by appropriately controlling the off point of the write enable signal according to the state of the tB cutoff detection signal. It is possible to cut off the power at a well-defined time point, avoid writing unstable data, and prevent reading of error data after the power is restored.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of a data retention control device for a nonvolatile memory according to the present invention, and FIG. 2 is a configuration diagram of an embodiment of the present invention.
FIG. 3 is a timing diagram explaining the operation of the device shown in FIG. 2;
FIG. 4 shows a detailed diagram of the power supply control circuit of FIG. 2, and FIG. 5 shows a detailed diagram of the memory control cutoff circuit of FIG. 2. In the figure, ■ is a power supply control circuit, 2 is a memory control cutoff circuit, and 3 is a power supply control circuit.
indicate voltage monitoring circuits, respectively. $5 [Zl

Claims (1)

[Claims] The first value is taken when the low DC power applied to the control means of the nonvolatile memory is stably supplied, and the second value is taken when an unexpected power cutoff occurs. 1 signal (PWRD
Y0) and the second value of the second signal (PWRDY1) obtained by delaying the value of the first signal (PWRDY0). A memory control cutoff circuit (2) that generates the third signal (PWDOWN) and cuts off the memory write enable signal at the falling edge of the signal; and after the third signal (PWDOWN) is generated, the memory control cutoff circuit (2) a voltage monitoring circuit that generates a fourth signal (PWOFF) that changes from the first value to the second value when the voltage of the low DC power supply drops to a predetermined value due to power cutoff; (3), and the third
For a non-volatile memory, the data being written is controlled to be stored in the memory to an appropriate position via a gate circuit (4) by cutting off the write enable signal at the falling edge of the signal. data retention controller.