JPH01214016A - Semiconductor substrate - Google Patents
Semiconductor substrateInfo
- Publication number
- JPH01214016A JPH01214016A JP3926788A JP3926788A JPH01214016A JP H01214016 A JPH01214016 A JP H01214016A JP 3926788 A JP3926788 A JP 3926788A JP 3926788 A JP3926788 A JP 3926788A JP H01214016 A JPH01214016 A JP H01214016A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- stress
- insulating
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 title claims abstract description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 21
- 229910052710 silicon Inorganic materials 0.000 abstract description 21
- 239000010703 silicon Substances 0.000 abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 14
- 229910052681 coesite Inorganic materials 0.000 abstract description 8
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 8
- 229910052682 stishovite Inorganic materials 0.000 abstract description 8
- 229910052905 tridymite Inorganic materials 0.000 abstract description 8
- 239000000377 silicon dioxide Substances 0.000 abstract description 7
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- 239000013078 crystal Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 238000000926 separation method Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000001069 Raman spectroscopy Methods 0.000 description 1
- 229910007277 Si3 N4 Inorganic materials 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003245 coal Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、基体上に絶縁層を介して半導体１→が形成さ
れてなる半導体基板、すなわち所謂５ｏｉ（ｓｉｌｉｃ
ｏｎ ｏｎ １ｎｓｕｌａｔｏｒ）基板に関する。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a semiconductor substrate in which a semiconductor 1→ is formed on a base through an insulating layer, that is, a so-called 5oi (silic) substrate.
on on 1 insulator) substrate.
（発明の概要」
本発明は、基体上に絶縁層を介して半導体層が形成され
てなる半導体基板において、絶縁層を半導体１−に接す
る絶縁膜と、この絶縁膜の応力を相殺する膜による積ｒ
−膜で構成することによって、絶縁膜を実質的に薄（し
て絶縁膜の実効的な応力を少なくし、これによって半導
体層に発生する応力を低減するようにしたものである。(Summary of the Invention) The present invention provides a semiconductor substrate in which a semiconductor layer is formed on a base with an insulating layer interposed therebetween, in which the insulating layer is formed by an insulating film in contact with the semiconductor 1- and a film that cancels out the stress of this insulating film. product r
- By forming the insulating film with a film, the insulating film is made substantially thinner, thereby reducing the effective stress of the insulating film, thereby reducing the stress generated in the semiconductor layer.
近時、所謂ＳＯｔ基板を用イーＣＣＭＯＳ等（７）ＶＬ
ＳＩ（ｉｊｊ大規模集積回路）を作成する開発が進めら
れている（１９８６１Ｈｈｈ 、 １９６−ＩＥＤＭ８
６〜ｌｈＤＭ８６−１９９参照）、このＳｏｌ基撮とし
ては、例えば第３図に示すように、シリコン基板（１）
上に厚さ４０００人程度炭種 ｉ０２等の絶Ｉｉ層（２
）を被着形成し、シリコンの選択エピタキシャル成長に
よって絶縁層（２）上にシリコン半導体ｒｆｉ（３１を
形成するようにしたＳｏｌ基板！４１が知られている。Recently, the so-called SOt board is used for e-CCMOS, etc. (7) VL.
Development to create SI (ijj large-scale integrated circuit) is underway (19861Hhh, 196-IEDM8
6 to lhDM86-199), for example, as shown in FIG.
On top of this, there is an absolute Ii layer (2
) is deposited and a silicon semiconductor RFI (31) is formed on the insulating layer (2) by selective epitaxial growth of silicon.
このようなＳ ＯＩ ４ｉ１４１を形成する場合、選択
エピタキシャル成圏のためのマスクとなる絶縁ｒｆｉ（
２）としては、選択エピタキシャル成長形状から判１ｔ
ｌｒすると５ｉＯｚが最も良いという結果が得られてい
る。When forming such an SOI 4i141, an insulating rfi (
As for 2), the size is 1t from the selective epitaxial growth shape.
The results show that 5iOz is the best.
ところで、上述したＳｏｌ基扱（４）において、Ｓ ｉ
０２絶縁層（４）上に成長したシリコン平導体ｊ−すな
わちエピタキシャル層（３）の応力を調べると、強いテ
ンシルの力が働いていることが判明した。顕微ラマン法
によると、この応力は約１．３ Ｘ １０’ ｄｙｎｅ
／ｄ位であった。このような強い応力はＳｉとＳ ｉ０
２の膜の組み合せに起因するものであり、本構造をとる
限り避けられない。選択エピタキシャル成長（気相成長
、固相成長）で第３図のＳｏｌ基撮（４）を形成する場
合、エピタキシャルｒＭ （３１において５ｉ０２絶縁
層（２）上の両側よりの成長のぶつかり部に応力が本中
し、結晶欠陥が発生しやすく、この結晶欠陥がリーク電
流の原因となる。従って、このようなＳｏｌ基板（４）
は半導体デバイスの作成に使えなくなる。又、ＭＯＳな
どのデバイスを作成する場合にシリコン半導体ｔ＝ （
３１に応力が残っていると、後の工程で均一な酸化がで
きない。By the way, in the Sol-based treatment (4) mentioned above, S i
When the stress of the silicon flat conductor j-, that is, the epitaxial layer (3) grown on the 02 insulating layer (4) was investigated, it was found that a strong tensile force was acting. According to the micro-Raman method, this stress is approximately 1.3 x 10' dyne
/d position. Such strong stress is caused by Si and Si0
This is due to the combination of the two films, and cannot be avoided as long as this structure is adopted. When forming the Sol substrate (4) in Fig. 3 by selective epitaxial growth (vapor phase growth, solid phase growth), stress is generated at the collision portion of the growth from both sides on the 5i02 insulating layer (2) in the epitaxial rM (31). However, crystal defects are likely to occur, and these crystal defects cause leakage current.Therefore, such a Sol substrate (4)
can no longer be used to create semiconductor devices. Also, when creating devices such as MOS, silicon semiconductor t= (
If stress remains in 31, uniform oxidation will not be possible in subsequent steps.
一方、本発明者達はシリコンのエピタキシャル層に発生
ずる応力を低減するために第２図に示す構成のＳｏｌ基
機（６１を提案した。このＳＯ１基板（６）は、シリコ
ン基板（１１上に応力緩衝層となる所定パターンの多結
晶シリコン１−（又は非晶質シリコン層）（５）を形成
し、この多結晶シリコン層（５）上にＳ ｉ０２絶縁層
（２）を形成した後、選択エピタキシャル成長してシリ
コン半導体層（３）を形成して構成するものである。On the other hand, the present inventors proposed a Sol-based substrate (61) having the configuration shown in FIG. 2 in order to reduce the stress generated in the silicon epitaxial layer. After forming a predetermined pattern of polycrystalline silicon 1- (or amorphous silicon layer) (5) that will become a stress buffer layer, and forming an Si02 insulating layer (2) on this polycrystalline silicon layer (5), A silicon semiconductor layer (3) is formed by selective epitaxial growth.
多結晶シリコン層（５）自身はシリコン基板＋１）と同
じ材料のため応力が少ないと共に、電気抵抗がシリコン
基板＜１１よりも大きい、従って、この構成では多結晶
シリコン層（５）の存在によってＳ ｉ（ｈ絶縁層（２
）の厚さを実質的に薄くしてＳ ｉ（ｈ絶縁層（２）の
応力を実効的に小さくし、これによってエピタキシャル
層（３）に発生する引張り応力を低減している。また、
第３図のＳｏｌ基板（４）と比較して、Ｓ ｉ０２絶縁
＋＝ （２＋が薄くなるも多結晶シリコンＪｔｊ ［５
）によってエピタキシャル層（３）とシリコン基板（１
）間の分離容量を小さくすることができる。この構成で
はエピタキシャルＩ＠ （３）に掛る応力を小さくする
ためにＳ ｉＯ２絶縁層（２）の厚さはあまり厚く°で
きす、１０００Å以上にしている。Since the polycrystalline silicon layer (5) itself is made of the same material as the silicon substrate +1), it has less stress and has a higher electrical resistance than the silicon substrate <11. Therefore, in this configuration, the presence of the polycrystalline silicon layer (5) causes S i (h insulating layer (2
) to effectively reduce the stress in the Si(h insulating layer (2)), thereby reducing the tensile stress generated in the epitaxial layer (3).
Compared to the Sol substrate (4) in Fig. 3, the polycrystalline silicon Jtj [5
) between the epitaxial layer (3) and the silicon substrate (1
) can be made smaller. In this configuration, in order to reduce the stress applied to the epitaxial I@(3), the thickness of the SiO2 insulating layer (2) cannot be too thick; it is set to 1000 Å or more.
しかるに、かかるＳｏｌ基扱（６）においても、Ｓｉｇ
ｈ絶縁層（２）上のエピタキシャル層（３）が薄い場合
にはエピタキシャル１ｍ （３１に発生する応力はまだ
大きいと思われる。However, even in such Sol-based treatment (6), Sig
When the epitaxial layer (3) on the h insulating layer (2) is thin, the stress generated in the epitaxial layer 1 m (31) is considered to be still large.
又、多結晶シリコン層（５）は、その電気抵抗がシリコ
ン基板（１）より大きいけれども５ｉ（ｈに比べて小さ
いので、絶縁物として代用しきれず、このため−Ｓ ｉ
０２絶縁層（２）を薄くした場合に分離容量も大きくな
る。Further, although the electrical resistance of the polycrystalline silicon layer (5) is larger than that of the silicon substrate (1), it is smaller than 5i(h), so it cannot be used as an insulator, and therefore -S i
When the 02 insulating layer (2) is made thinner, the isolation capacitance also increases.
本発明は、上述の点に鑑み、分離容）ｄの増加を防ぎ、
且つエピタキシャル層に発生する応力を低減できるよう
にした半導体基＆即ちＳＯＩ基扱を提供するものである
。In view of the above points, the present invention prevents an increase in separation volume) d,
Moreover, it provides semiconductor-based and SOI-based treatment that can reduce the stress generated in the epitaxial layer.
本発明は、基体上（１）に絶縁層を介して選択エピタキ
シャル成長による半導体層（１０）が形成されてなる半
導体基板において、絶縁層（８）を半導体層に接する絶
縁１９！（１２）と、この絶縁膜（１２）の応力を相殺
する膜（７）との積層膜で構成するようになす。The present invention provides a semiconductor substrate in which a semiconductor layer (10) is formed on a substrate (1) by selective epitaxial growth via an insulating layer, and an insulating layer (8) is in contact with the semiconductor layer (19!). (12) and a film (7) that cancels the stress of this insulating film (12).
絶縁層（８）が半導体ＪｔＷ（１０）に接する絶縁膜（
１２）と、この絶縁膜（１２）の応力を相殺する膜（７
）の積Ｉｊ膜で構成されるので、絶縁膜（１２）の応力
が可及的に小さくなる。これにより絶縁ＩＱ（１２）上
に形成される半導体層（１０）の応力が低減する。した
がって応力に起因する結晶欠陥も減り、結晶性のよい半
導体１！（１０）が形成される。An insulating film (where the insulating layer (8) is in contact with the semiconductor JtW (10)
12) and a film (7) that offsets the stress of this insulating film (12).
), the stress of the insulating film (12) is reduced as much as possible. This reduces stress in the semiconductor layer (10) formed on the insulating IQ (12). Therefore, crystal defects caused by stress are reduced, resulting in a semiconductor with good crystallinity! (10) is formed.
また、絶縁Ｊｍ （８１は積Ｉ一般で形成されるので厚
くすることができ、半導体Ｉｎ（１０）と基体（１）間
の分離容量が小さくできる。分離容量が小さいときはデ
バイスを作成したときのデバイスの商連動作に有利とな
る。In addition, since the insulation Jm (81) is generally formed by the product I, it can be made thicker, and the separation capacitance between the semiconductor In (10) and the substrate (1) can be reduced.When the separation capacitance is small, when the device is made This will be advantageous for the commercial operation of devices.
以下、第１図を参照して本発明によるＳＯ１法坂の実施
例をその製法と共に説明する。Hereinafter, an embodiment of the SO1 method slope according to the present invention will be described with reference to FIG. 1, together with its manufacturing method.
本例においては、先ず第１図Ａに示すようにシリコン基
板（１）上に応力ｒｉ街層となる厚さ３０００人程度０
例えば多結晶シリコン層！５）、）ｉ−さ１００〜５０
０炭種度のＳｉ３Ｎ２腺（７）及び厚さ１０００Å以上
の５ｉＯｚｌｌ！２！（１２）を順次被着形成する。こ
こで、Ｓ ｉ（ｈ股（１２）の応力と５ｉａＮ４ＩＱ（
７１の応力は互いに逆方向である。In this example, first, as shown in FIG.
For example, a polycrystalline silicon layer! 5),) i-sa 100-50
Si3N2 gland (7) with 0 coal grade degree and 5iOzll with thickness of 1000 Å or more! 2! (12) are sequentially deposited and formed. Here, S i (h crotch (12) stress and 5iaN4IQ (
The stresses at 71 are in opposite directions.
従って、ＳｉＯ２股（１２）の応力とＳｉ３Ｎ４股（７
）の応力が杓ち消し合う２Ｍ構造の絶縁層（８）が形成
される。Therefore, the stress of the SiO2 crotch (12) and the stress of the Si3N 4 crotch (7)
An insulating layer (8) having a 2M structure in which the stresses of ) are canceled out is formed.
次に、第１図Ｂに示すようにマスク（図示せず）を介し
てＳ ＋０２映（１２）、 ５ｉ−ＩＮ４ＩＩぐ（７３
及び多結晶シリコン層（５）をバターニングする。Next, as shown in FIG. 1B, S +02 (12) and 5i-IN4II (73
and patterning the polycrystalline silicon layer (5).
次に、第１図Ｃに示すようにＣＶＩ）法によるＳ ｉ（
ｈを被着して後エソナハソクして多結晶シリコン層（５
）の１ｕ１１面を覆うようなＳ ｉ０２側壁口１Ｓ（９
１を形成する。Next, as shown in Figure 1C, S i (
After depositing a polycrystalline silicon layer (5
) S i02 side wall opening 1S (9
form 1.
次に、第１図りに示すようにシリコン基板（１）が臨む
面からシリコンの選択エピタキシャル成長を行う。この
選択エピタキシャル成長は、３ｉ０２膜（１２）上まで
横力向に成長が進ような条件で行い、５ｉ（ｈ膜（１２
）上にシリコン半導体層（１０）を形成する。斯くして
目的のＳＯ１基板（１１）をｉｉ＃る。Next, as shown in the first diagram, selective epitaxial growth of silicon is performed from the surface facing the silicon substrate (1). This selective epitaxial growth was performed under conditions such that the growth progressed in the lateral direction up to the top of the 3i02 film (12), and the 5i(h film (12)
) A silicon semiconductor layer (10) is formed on the silicon semiconductor layer (10). In this way, the target SO1 substrate (11) is obtained.
かかる構成によれば、第２図のＳｏｌ基扱（６）と比較
してみると、５ｉＯｓＪ９ｊ （１２）の厚さを厚く形
成できると共に、５ｉＯＪ２ （１２） ０）応力とＳ
ｉ３Ｎ ４１１Ｒ＋７）の応力とか相殺されることに
よって５ｉＯＪ＊ （１２）の応力が小さくなる。従っ
て絶縁Ｗ （８）としてはＳｔ０？股（１２）とＳｉ〕
Ｎ４映（７）の合計膜厚となり、分離容量を小さくする
ことができると同時に、シリコン半導体ｊ＠即ちエピタ
キシャルＩｎ（１０）に発生する応力を１０’ ｄｙｎ
ｅ／ｃｄ程度に低減することができる。そして、応力が
低減されるので３心力に起因する結晶欠陥も低減できる
。構造的には第２図の構造とほぼ同じなので＠Ａ造工程
などの制限は特に変わらない。According to this configuration, when compared with Sol-based treatment (6) in FIG.
By canceling out the stress of i3N 411R+7), the stress of 5iOJ* (12) becomes smaller. Therefore, as the insulation W (8), St0? Crotch (12) and Si]
The total film thickness is N4 (7), which makes it possible to reduce the isolation capacitance and reduce the stress generated in the silicon semiconductor (i.e., epitaxial In (10)) by 10' dyn.
It can be reduced to about e/cd. Furthermore, since stress is reduced, crystal defects caused by three-core forces can also be reduced. Structurally, it is almost the same as the structure shown in Figure 2, so there are no particular changes in the restrictions such as the @A construction process.
一方、第３図の従来のＳｏｌ基板（４）と比較したとき
には絶縁１＠ （８）の下に応力緩衝層となる多結晶シ
リコン映（５）が介ｈｌｊされているごとにより、Ｓ
１（ｈｆｌ！（１２）を実質的に薄くすることができ、
実効的なＬｅａ力を小さくすることができる。On the other hand, when compared with the conventional Sol substrate (4) in Figure 3, S
1 (hfl!(12)) can be made substantially thinner,
The effective Lea force can be reduced.
尚、上側では応力緩衝層として多結晶シリコンＩｎ ＋
５１を用いたが、その他非晶實シリコン、酸素ドープ多
結晶シリコン、或はＳｉと膨張係数が同じなりＳＧ （
ボロンシリケートガラス） 、 Ｓｉｏ２より応力の
少ないＰＳＧ （リンシリケートガラス）等を用いるこ
ともできる。Note that polycrystalline silicon In + is used as a stress buffer layer on the upper side.
51 was used, but other materials such as amorphous silicon, oxygen-doped polycrystalline silicon, or SG (
It is also possible to use PSG (phosphorus silicate glass), which has less stress than Sio2 (boron silicate glass), or the like.
（発明の効果」
本発明によれは、基体上に絶縁層を介して半導体層が形
成されてなる半導体基板において、絶縁ｊ−を半導体１
ｉに接する絶縁層とこの絶縁段の応力を相殺する股との
積層膜で構成することにより、絶縁段の応力を小さくす
ることができ、この上に形成される半導体層の応力を低
減することができる。これによって結晶欠陥の少ない半
導体層がＲｊられる。同時に絶縁層を厚く形成できるの
で、半導体１−と基体間の分離容量も小さくすることが
できる。従って、ＶＬＳＩ等の作成に通した半導体＆扱
を提供することができる。(Effects of the Invention) According to the present invention, in a semiconductor substrate in which a semiconductor layer is formed on a base through an insulating layer, the insulating j- is
By constructing a laminated film of an insulating layer in contact with i and a crotch that offsets the stress of this insulating step, the stress of the insulating step can be reduced, and the stress of the semiconductor layer formed thereon can be reduced. Can be done. As a result, the semiconductor layer with few crystal defects is Rj. At the same time, since the insulating layer can be formed thickly, the separation capacitance between the semiconductor 1- and the substrate can also be reduced. Therefore, it is possible to provide semiconductor & handling through the creation of VLSI etc.
第１図Ａ−Ｄは本発明にょるＳＯＩ基扱の一例を示す製
造工程順の断面図、第２図は本発明の説明に供する比較
のための５Ｏ１ｉ坂の断面し１、第３図は従来のＳｏｌ
基扱の断面図である。
＋１）はシリコン基板、（２）は５ｉ（ｈ絶縁層、＋３
１ （１０）は選択エピタキシャル成にによるシリコン
半導体層、（５）は多結晶シリコン層、（７）はＳｉ３
Ｎ４股、（８）は絶縁ｒ−１（１２）はＳ ｉｔｈ絶縁
絶縁ある。1A to 1D are cross-sectional views in the order of manufacturing steps showing an example of SOI handling according to the present invention, FIG. 2 is a cross-sectional view of a 5O1i slope for comparison to explain the present invention, and FIG. Traditional Sol
It is a sectional view of the basic treatment. +1) is a silicon substrate, (2) is a 5i (h insulating layer, +3
1 (10) is a silicon semiconductor layer formed by selective epitaxial formation, (5) is a polycrystalline silicon layer, and (7) is a Si3
N4 crotch, (8) is insulated r-1 (12) is S ith insulated.
Claims (1)
導体基板において、 上記絶縁層が半導体層に接する絶縁膜と、該絶縁膜の応
力を相殺する膜との積層膜で構成されて成る半導体基板
。[Scope of Claims] A semiconductor substrate in which a semiconductor layer is formed on a base with an insulating layer interposed therebetween, a laminated film comprising an insulating film in which the insulating layer is in contact with the semiconductor layer, and a film that offsets the stress of the insulating film. A semiconductor substrate made up of
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3926788A JPH01214016A (en) | 1988-02-22 | 1988-02-22 | Semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3926788A JPH01214016A (en) | 1988-02-22 | 1988-02-22 | Semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01214016A true JPH01214016A (en) | 1989-08-28 |
Family
ID=12548367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3926788A Pending JPH01214016A (en) | 1988-02-22 | 1988-02-22 | Semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01214016A (en) |
-
1988
- 1988-02-22 JP JP3926788A patent/JPH01214016A/en active Pending
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