JPH01211000A - Voice reproducing device - Google Patents

Abstract

PURPOSE:To prevent the degradation of reproducing frequency characteristic by changing the cut-off frequency of a filter for reproduced voice in accordance with a frequency ratio of the sampling clock for recording to that for reproducing of digital voice data to a solid-state storage circuit. CONSTITUTION:Digital voice data recorded in a solid-state storage circuit 12 of an IC card by the sampling clock having a prescribed frequency is reproduced through a CPU 14 by the sampling clock for reproducing from a clock signal generating circuit 18 whose frequency is controlled by a variable resistor 6 for reproducing speed control. The digital voice reproduced at a desired repro ducing speed in accordance with the frequency ratio of the clock pulse for recording to that for reproducing is analyzed and synthesized by a voice signal synthesizing circuit 16 and a voice signal analyzing circuit 17 and outputted to an earphone 8 or the like as an analog voice sentence through a BPF circuit 20 which eliminates noise components. The cut-off frequency of this circuit 20 is changed and adjusted by a cut-off frequency varying means 24 interlocking with the resistor 6, and the reduction of the reproduced signal frequency is prevented though the reproducing speed is changed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an audio reproducing device for reproducing stored audio data, for example, for language practice.

(Prior Art) As an audio reproducing device, an audio reproducing device that utilizes a solid-state storage circuit such as an IC memory is provided. In this device, analog audio signals are digitized and stored in the solid-state storage circuit, and the audio data is sequentially read out and subjected to D/A conversion to synthesize and reproduce the analog audio signals.

In this type of device, when storing audio data in the solid-state memory circuit, for example, a foreign language is read aloud and converted into an audio analog signal using a microphone, etc., and this audio analog signal is converted into an audio analog signal as shown in Fig. 4. The audio data is quantized using a recording sampling clock of a predetermined frequency and stored in a solid-state storage circuit as audio data. When playing back this audio data, the audio data is converted to analog using a sampling clock for playback that has the same frequency as the sampling clock for recording, but at that time, the audio analog Since noise and distortion occur in the signal, this audio analog signal is passed through a filter circuit to remove the noise and distortion, and then the audio analog signal is amplified and output as reproduced sound.

Recently, however, in audio playback devices that use this type of solid-state memory circuit, it has been considered that the playback speed can be changed in order to increase the number of uses. By changing the frequency of the sampling clock to a ratio other than 1 to the recording sampling clock, the reproduction speed is made variable.

(Problem to be Solved by the Invention) However, when the playback speed is changed, that is, when the frequency of the sampling clock for playback is different from the frequency of the sampling clock for recording, the frequency of the audio analog signal changes. Noise or distortion in the signal may pass through the filter circuit as is, or originally necessary audio components may be removed, and as the playback speed is changed, the frequency characteristics deteriorate significantly.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to enable various usage forms by varying the speed of audio reproduction in devices that reproduce audio data from solid-state storage circuits such as IC memories. Moreover, it is an object of the present invention to provide an audio reproducing device that can prevent a decrease in frequency characteristics even when the reproduction speed is changed.

[Structure of the Invention] (Means for Solving the Problems) The audio reproduction device of the present invention extracts audio data from a solid-state storage circuit in which audio data obtained by digitizing audio analog signals based on a recording sampling clock of a predetermined frequency. A speech synthesis circuit that reads out audio data and converts it into an audio analog signal based on a reproduction sampling clock of a predetermined frequency, a filter circuit that removes noise components and distortion components contained in the audio analog signal, and this filter circuit. A playback circuit that outputs the audio analog signal that has passed through as playback sound, and a variable playback speed that changes the playback speed of the audio analog signal by setting the frequency ratio between the recording sampling clock and the playback sampling clock to a value other than 1. and a cutoff frequency variable means for changing the cutoff frequency of the filter circuit according to the frequency ratio of the recording sampling clock and the reproduction sampling clock. It is.

(Function) The audio signal synthesis circuit reads audio data from the solid-state storage circuit, converts it into an audio analog signal based on a predetermined reproduction sampling clock, passes this audio analog signal through a filter circuit, and outputs it as reproduced sound by the reproduction circuit. be done. At this time, if the reproduction speed variable means sets the frequency ratio between the recording sampling clock and the reproduction sampling clock to a value other than 1, the cutoff frequency variable means changes the cutoff frequency of the filter circuit according to the frequency ratio. Therefore, even if the frequency of the audio analog signal changes, it is possible to remove only noise and distortion without removing the audio component, and it is possible to eliminate deterioration in frequency characteristics.

(Example) Hereinafter, an example in which the present invention is applied to a language practice device will be described with reference to FIGS. 1 to 3.

In FIG. 2 showing the overall appearance, 1 is a flat box-shaped main body, on the front of which are provided a key control section 2 with a plurality of push buttons 2a, a liquid crystal display 3, and an embedded microphone 4. A variable resistor 5 for adjusting the volume, a variable resistor 6 for adjusting the playback speed, and an external audio signal input terminal 7 are provided on the left side in the figure, and an earphone jack 9 for the earphone 8 and a card are provided on the upper side in the figure. An insertion port 10 is provided.

Reference numeral 11 denotes an IC card as an external storage device configured to be insertable into and removed from the card insertion slot 10, and a solid-state storage circuit 12 including a FROM chip and a CPU chip, which are read-only storage elements, is embedded inside this card. It is. The solid-state storage circuit 12 stores in advance a plurality of groups of audio data obtained by digitizing audio analog signals based on a recording sampling clock having a predetermined frequency fr.

In this embodiment, the audio analog signal is obtained by recording and amplifying short sentences for conversation practice in a foreign language using a microphone. Further, the IC card 11 is provided with a plurality of contacts (not shown) for signal input/output, and when the IC card 11 is inserted into the card insertion slot 10, the contacts are provided inside the main body 1. It is configured to be in a connected state to a connector (denoted by reference numeral 13 in FIG. 1).

Now, Figure 1 shows the electrical configuration, where 14
15 is a RAM as a built-in solid-state storage circuit; 16 is an audio signal synthesis circuit; 17 is an audio signal analysis circuit; 18 is a variable oscillation frequency clock signal generation circuit; A switching circuit 20 is a band-pass filter type filter circuit including the volume adjusting variable resistor 5, and 21 is a reproducing circuit comprising an amplifier 22 and the earphone 8. The audio signal synthesis circuit 16 reads the audio data group specified by the central control circuit 14 from the solid-state storage circuit 12 of the IC card 11, and also reads out the audio data group specified by the central control circuit 14 from the solid-state storage circuit 12 of the IC card 11. The audio data is D/A converted and an audio analog signal is output to the filter circuit 20. The filter circuit 20 cuts low frequency ranges and high frequency ranges at a predetermined cutoff frequency. The audio analog signal that has passed through the filter circuit 20 is amplified by the amplifier 22 of the reproduction circuit 21 and output from the earphone 8. On the other hand, the audio signal analysis circuit 17
The audio analog signal given from the microphone 4 or the external audio signal input terminal 7 is sent to the clock signal generation circuit 1B.
The digital signal is quantized based on the recording sampling clock of frequency f outputted from the controller, A/D converted, and digitized. and stored in the RAM 15 as audio data.

Here, the playback speed adjusting variable resistor 6 and the clock signal generation circuit 18 are the playback speed variable means 23 according to the present invention.
The frequency fp of the sampling clock for reproduction outputted from the clock signal generation circuit 18 can be adjusted to include a value equal to the frequency f of the sampling clock for recording by operating the variable resistor 6 for adjusting the reproduction speed. The frequency f of the sampling clock for recording is constant.As a result, the frequencies fr and fp of the sampling clocks for recording and playback can be adjusted before and after.
The ratio can be adjusted to 1 and a value other than 1.

Further, 24 is a variable resistor for adjusting the cut-off frequency as cut-off frequency variable means, which is configured to be linked to the operation of the variable resistor 6 for adjusting the playback speed, and in this case, the above-mentioned frequency Depending on the ratio (fp/fr),
The lower cutoff frequency and the higher cutoff frequency are adjusted. That is, when fp/fr is 1 (at normal playback speed), the lower cutoff frequency is fcl, and the higher cutoff frequency is fc2.
Then, when fp/fr > 1 (the playback speed is fast), fp/f is adjusted to be higher as shown by fcl' and fc2' in FIG. 3(a), and fp/f
When r < 1 (playback speed is slow), Fig. 3 (b
) are adjusted so that they are respectively low as shown by f cl' and f c2'. However, the degree of adjustment is
It is continuous as is the playback speed.

The central control circuit 14 operates based on various commands inputted from the key input unit 2 and a pre-stored system program, as will be made clear from the explanation of the operation described later.
It is designed to exchange audio data between the solid-state storage circuit 12 or RAM 15 of the C card 11 and the audio signal synthesis circuit 16 or audio signal analysis circuit 17, or to control the display of the liquid crystal display 3.

Next, the operation of this embodiment will be explained.

(1) When playing back using the IC card 11 The solid-state storage circuit 12 of the IC card 11 stores in advance a group of audio data digitized using a recording sampling clock of a predetermined frequency f.This IC card 11 into the card insertion slot 10 of the main body 1, and input the text number and number of reproductions corresponding to the desired voice data group from the key input section 2.

Then, the central control circuit 14 displays the selected text number and the number of reproductions on the liquid crystal display 3, and instructs the audio signal synthesis circuit 16 to execute the conversion operation. Then, the audio signal synthesis circuit 16 transfers the audio data group corresponding to the selected sentence number to the solid state storage circuit 12 of the IC card 11.
At the same time, the audio data is converted into an audio analog signal based on the reproduction sampling clock of frequency fp given from the clock signal generation circuit 18 and output to the filter circuit 20. As a result, noise and distortion components contained in the audio analog signal are removed, and the signal is amplified by the amplifier 22 of the reproduction circuit 21 and outputted from the earphone 8 as audio.

Note that the playback volume on the earphone 8 can be adjusted by operating the volume adjustment variable resistor 5. When such audio reproduction is completed, an end signal is output from the audio signal synthesis circuit 16 to the central control circuit 14, and the central control circuit 14 repeats the above-described reproduction operation a preset number of times.

Now, when the variable resistor 6'G for adjusting the playback speed is adjusted, the frequency fp of the sampling clock for playback output from the clock signal generation circuit 18 becomes the sampling clock for recording in the audio data stored in advance in the IC card 1. The clock frequency f' is adjusted before and after the clock frequency f', including a value equal to the same value.Here, if the frequency fp of the sampling clock for playback is adjusted to be equal to the frequency f' of the recording sampling clock, the audio will be equal to the value at the time of recording. However, the frequency fp of the sampling clock for playback is the same as the frequency fp of the sampling clock for recording.
If the playback speed is adjusted higher than the standard speed, the playback speed becomes so-called fast playback, and conversely, if the playback speed is adjusted lower than the recording sampling clock frequency fr, the playback speed becomes the standard playback speed. Thus, according to this embodiment, by appropriately adjusting the playback speed using the playback speed variable means 22, it is possible to use the language practice in a manner that corresponds to the learning level.

On the other hand, as mentioned above, when the playback speed is changed, each frequency component of the audio analog signal also changes at the rate of change in the playback speed (f
p/f r ), but in this embodiment, the variable resistor 23 for adjusting the cutoff frequency operates in conjunction with the resistor 6 for adjusting the playback speed, and thereby the "C filter circuit 20" By changing the time constant and changing the cutoff frequency, the cutoff frequency is optimized, allowing the audio components in the audio analog signal to pass through and removing noise and distortion components, resulting in a change in sound quality. Excellent frequency characteristics can be obtained.

Incidentally, when the continuous reproduction mode is set by performing a predetermined operation on the key manual section 2, the audio data group stored in the solid state storage circuit 12 of the IC card 11 is automatically reproduced sequentially a set number of times.

(2) When performing recording/playback In this case, do not use the IC card 11 exclusively for playback.
Built-in RAM 15 is used. First, a recording mode is set by operating the key power section 2, and audio is recorded using the microphone 4 of the main body 1, or an audio analog signal from, for example, a radio receiver is input to the external audio signal input terminal 7. Then, the audio analog signal is given to the audio signal analysis circuit 17, which digitizes the audio analog signal based on a recording sampling clock of a predetermined frequency f" output from the clock signal generation circuit 18. are sequentially stored in the RAM 15 via the switching circuit 19 which is switched by a command from
The central control circuit 14 calculates the ratio between the total recordable time determined by the total storage capacity of the RAM 15 and the remaining recording time determined by the remaining storage capacity of the RAM 15, and displays this result on the liquid crystal display 3. To inform a user of the remaining recording time.

After recording is finished, if the playback mode is selected, the audio data digitized and stored in the RAM 15 is sequentially read out, and the I
The recorded voice is played back in the same way as when playing back using the C card 11.

Even in this case, by adjusting the variable resistor 6 for adjusting the reproduction speed, the reproduction speed can be adjusted as desired, and the variable resistor 24 for adjusting the cutoff frequency operates in conjunction with the resistor 6, so that the frequency characteristic does not decrease.

In the above embodiment, the reproduction speed can be continuously adjusted by operating the variable resistor 6, and the cutoff frequency by the variable resistor 24 can also be continuously varied accordingly. However, the present invention However, the present invention is not limited to this. For example, if the playback speed can be adjusted stepwise using a switch, the cutoff frequency may also be adjusted stepwise accordingly. Further, the cutoff frequency may be adjusted in conjunction with the frequency of the reproduction sampling clock. Further, in the above embodiment, the variable resistor 24 is used as an example to make the cutoff frequency variable, but a variable capacitor may be used as the cutoff frequency variable means.

In addition, the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the scope of the invention, for example, the recording function may not necessarily be provided.

[Effects of the Invention] As described above, since the present invention is provided with a reproduction speed variable means that makes the frequency ratio of the recording sampling clock and the reproduction sampling clock other than 1, the reproduction speed can be varied as desired, and the reproduction speed can be varied as desired. Furthermore, since a cutoff frequency variable means is provided to change the cutoff frequency of the filter circuit according to the frequency ratio, it is possible to eliminate a drop in frequency characteristics even when the playback speed is changed. Therefore, the excellent effect of eliminating the occurrence of sound quality deterioration is achieved.

[Brief explanation of the drawing]

1 to 3 show one embodiment of the present invention, FIG. 1 is an overall block diagram, FIG. 2 is an overall perspective view, and FIG. 3 is a diagram showing an example of change in cutoff frequency. , FIG. 4 is a waveform diagram when an audio analog signal is quantized. In the drawing, 5 is a variable resistor for volume adjustment, 6 is a variable resistor for playback speed adjustment (playback speed variable means), 11 is an IC card, 12 is a solid state storage circuit, 14 is a central control circuit, and 15 is R
AM (solid state memory circuit), 18 is a variable frequency clock signal generation circuit, 2° is a filter circuit, 21 is a regeneration circuit, and 24 is a variable resistor for adjusting the cutoff frequency (cutoff frequency variable means). Applicant: Toshiba Corporation Toshiba Audio/Video Figure 1 Figure 3

Claims (1)

[Claims] 1. Read the audio data from a solid-state memory circuit in which audio data is stored, which is digitized audio analog signal based on a recording sampling clock of a predetermined frequency, and convert it into an audio analog signal based on a reproduction sampling clock of a predetermined frequency. a filter circuit for removing noise components and distortion components contained in the analog audio signal, a reproducing circuit for outputting the analog audio signal that has passed through the filter circuit as reproduced sound, and a recording sampling clock. and a reproduction speed variable means for changing the reproduction speed of the audio analog signal by setting the frequency ratio between the recording sampling clock and the reproduction sampling clock to a value other than 1. 1. An audio reproducing device comprising cutoff frequency variable means for changing the cutoff frequency of the filter circuit according to a frequency ratio of the filter circuit.