JPS6232797B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a speech synthesis method, in particular, storing frequency control information of speech digital information to be synthesized.
The present invention relates to a speech synthesis method in which the frequency bandwidth of synthesized speech can be changed by selecting stored frequency control information.

An object of the present invention is to provide a system that can appropriately select and change the frequency band of a synthesized sound commensurate with the capability of a reproduction speaker.

In addition, only digital data in frequency bands that can be reproduced for other purposes is stored in memory,
By removing data in other bands, the efficiency of memory usage is increased, and at the same time, the storage capacity of the memory is compressed.

In recent years, the development of digital devices such as desktop calculators and translators that make full use of speech synthesis technology has been progressing.

Such technology usually involves converting analog information such as voice into digital information, then storing this in a memory such as RAM, and obtaining a synthesized sound to be played based on program instructions stored in ROM memory. .

The analog information of the original sound is quantized as faithfully as possible and converted into digital quantities.
Regenerative amplifiers and speakers each have their own limits to their reproducing capabilities, and the attenuation of their frequencies is particularly large at the upper and lower limits of the frequency band.As devices become smaller and thinner, their reproducing capabilities are significantly reduced. There were drawbacks such as:

The present invention has been made to overcome the above-mentioned drawbacks.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of the essential parts of an example of electronic equipment (such as a calculator, computer, educational equipment, etc.) adopting the method of the present invention.

In the figure, 1 is a microphone that converts an audio signal into an electrical signal, 2 is a microphone amplifier for amplifying the microphone signal, 3 is an amplifier for further amplifying the output of the microphone amplifier 2 to form a pulse waveform, Reference numeral 4 denotes a frequency counting memory (hereinafter referred to as a frequency memory counter) that counts and stores the frequency components of the pulse waveform, and terminals that output "1" when the frequency of the pulse waveform exceeds this are provided. In other words, terminal 0.1 outputs "1" when the frequency is 100Hz or higher, and similarly, 0.2 outputs "1" when the frequency is 200Hz or higher.
0.5 is configured to supply an output of "1" when the frequency is 500 Hz or higher, 3 is 3 KHz or higher, 5 is 5 KHz or higher, and 10 is 10 KHz or higher.

For example, if you measure the time interval from the rising edge to the falling edge of a pulse waveform input, and if the next rising pulse comes within 0.33 msec from the rising edge or falling edge, then
It has a frequency of 3KHz, and can be realized by outputting "1" from the "3" terminal.

_G1 to _G3 are AND gates that input the output from F, and the _G1 output appears in the frequency band of 500Hz to 3KHz, and similarly, the _G2 output appears in the frequency band of 200Hz to 3KHz.
5KHz, _G3 output appears in the frequency band of 100Hz to 10KHz. SW ₁ is AND gate G ₁ ~
This is a switch for selectively switching one of the frequency bands of _G2 , and this switch is constructed from a semiconductor element and can also be controlled based on instructions from the CPU. 5 is an A/D converter for converting analog information from the microphone amplifier output into digital information, 6 is an interface, and 7 is a CPU.
(arithmetic processing unit), which includes the acquisition unit ACC, etc. 8 is a memory that stores audio converted into digital data, such as random access memory.
Memory (RAM) 9 is a memory for storing execution procedures (algorithms) to be stored in RAM or algorithms for speech synthesis, such as read/write memory.
Only memory (ROM), 10 is a voice synthesizer that synthesizes digital data and also includes D/A conversion, 11 is an audio amplifier, and 12 is a speaker. Switch SW ₂ can play synthesized sounds or simply store digital data in memory RMA.
This is a switch that allows you to select whether to store or not.

FIG. 2 is a diagram showing an example of the frequency characteristics of a speaker employed as the speaker in the block diagram of FIG. 1.

In the figure, the reproduction capacity of speaker SP ₁ is 500Hz ~
3KHz is the lowest compared to other speakers, and the reproduction ability of speakers SP ₂ and SP ₃ is 200Hz and up, respectively.
5 KHz, 100 Hz to 10 KHz, and this frequency band is shown by the symbol with the frequency band of FC in the block diagram of FIG.

FIG. 3 is a time chart of waveforms of various parts of the block diagram of FIG. 1 when the speaker SP ₁ (500Hz to 3KHz) with the lowest reproduction capability shown in FIG. 2 is employed.

In the figure, a is the microphone amplifier output waveform diagram.
MAO, b is the output waveform diagram of pulse waveform amplifier A, AO, c, d are the output pulses Fc appearing at output terminals 0.5 and 3 of frequency memory counter FC.
(0.5), Fc(3), and e are the output waveform diagrams (G ₁₀ ) of the gate G ₁ .

Here, the waveform of Fc( ₃ ) is as follows: Frequency memory counter FC in Figure 1
This shows that the output of is High. Also, since the time from time t ₀ to t ₁ is within 166 usec, FC(3) is
It becomes High, and since it exceeds 166 usec between time t ₄ and t ₅ , it becomes Low level at time t ₅ .

Now, the sampling time of the A/D converter that converts analog data to digital data is 1/16th.
KHz, and further amplifies the output MAO of the microphone amplifier MA to obtain the pulse output AO (Figure b). However, when this pulse output AO is input to the frequency memory counter FC, the frequency component is initially 500Hz or higher, so the FC output Fc (0.5) becomes “1” (Figure C).
When the input pulse frequency becomes 3KHz or more at time _t1 , Fc(3) becomes "1", and therefore the output _G10 of the gate _G1 becomes as shown in Figure e.

In other words, since the frequency band that speaker SP ₁ can reproduce is 500Hz to 3KHz, the frequency band F when the gate G ₁₀ output is "1" is 500Hz<F<3KHz.
, and F when “0” is F<500Hz or F
>3KHz frequency.

Therefore, it is sufficient to sample digital data in the interval of G ₁₀ = 1 and store the data, and G ₁₀ =
The section of 0 is a section in which sampling is not performed because the speaker itself does not have a reproduction capability and cannot be reproduced even if it is stored as data.

For example, the output of Fc(3) will be "1" if the next rising edge arrives within 0.33 msec from the rising or falling edge of the previous input, and will be "0" if it does not arrive even after 0.33 msec has elapsed. be.

Based on the technical idea of storing the frequency control information of the digital audio information to be synthesized so that the frequency bandwidth of the synthesized sound can be changed,
It is possible to reproduce only audio digital information in a frequency band that matches the characteristics of the speaker as a synthesized sound.

Therefore, the frequency memory counter FC, gate circuit G, and switch SW ₁ shown in the embodiment can store frequency control information that can change the frequency bandwidth of the synthesized sound, and can selectively use the stored desired control information. Any circuit may be used as long as it is capable of outputting an output to the output signal and controlling the frequency of audio digital information to be synthesized using this output.

These circuits can be constructed using LSI or other semiconductor circuit elements.

Next, the speech synthesis method of the present invention will be explained according to the flowcharts of FIGS. 4 and 5.

First, FIG. 4 is a flowchart showing the execution procedure (algorithm) for inputting audio digital data to the memory RAM.

First, audio analog data inputted from a microphone 1 is converted into 7-bit digital data by an A/D converter VA via an amplifier 2. This 7-bit digital data is processed by the central processing unit _CPU
stored in the accumulator ACC (VA
→ACC), the gate output G from switch SW ₁ is G
= 1 (for example, frequency band is 500Hz<F<3KHz)
If G = 1, after resetting the flag GF provided in an area in the memory RAM, the contents of the accumulator ACC (7-bit digital data) are transferred to the memory RAM.
A/D is stored in a predetermined area (ACC → RAM), and the RAM address is counted up by 1 (RAMADRES + 1) in preparation for the next time. Perform time adjustment (TIMEADJUST) to import the microphone amplifier output MAO to the converter. Time adjustments are made at the VA.

If G ₁ , i.e. for example frequency f<500Hz, f
If <3KHz, this is outside the frequency band, and the flag in RAM8 determines whether GF=1, and if it is the first data, GF=0, indicating that the data is outside the frequency band. 8-bit accumulator in CPU to show that
80 to input “1” to the most significant bit of ACC
(Hexadecimal = H), that is, 10000000 as an accumulator
Input to ACC (80H→ACC) and set flag GF in RAM.

If it is the second time, the accumulator ACC is counted up (ACC+1) in order to count the duration of the state of _G1 . ACC count value is
If ACC<7FH, that is, 1111111, time adjustment is made and the process returns to VA1N. When the count value of accumulator ACC reaches 7HF, ACC cannot count any more, so resets the RAM flag GF, stores the contents of ACC in RAM, and
Count up the RAM address by 1.
In this way, G=1, that is, for example, 500Hz<f<
When 3KHz, 1 every sampling frequency 16KHz
It has a data storage capacity of bytes of RAM, but G
=0, that is, for example, when f<500Hz or f>3KHz, a maximum of 127 bytes can be stored in one byte, and therefore the data storage capacity of the RAM can be greatly compressed.

FIG. 5 shows a flowchart for outputting digital data stored in memory RAM by voice synthesis.

First, store the digital data stored in the memory RAM to the accumulator ACC,
(RAM→ACC), it is determined whether the 8th bit of the ACC accumulator is 1 or not. That is, if the 8th bit is 1, it means that G≠1 and it is outside the desired frequency band, and if the 8th bit is not 1, it means that G=1 and it is within the desired frequency band. .

Therefore, if HBIT ≠ 1, the accumulator ACC
Digital data of voice synthesizer VS
Input it to the (speech synthesizer) (ACC → VS), upload the RAM memory address by 1, and adjust the time for 16KHz sampling.

If the 8th bit of the accumulator ACC is 1
If so, it is determined that the digital data is outside the desired frequency band, and 0 is input to the voice synthesizer VS (0 → VS). (ACC-1) and adjust the time,
If ACC≠0, perform 0→VS again and ACC
When it becomes = 0, it goes straight to voice synthesizer VS.
It outputs the contents of ACC and executes processing to extract the next data.

As explained above, according to the speech synthesis method of the present invention, it is possible to appropriately select and change the frequency band of synthesized sound that matches the capability of the reproduction speaker.

Furthermore, by storing only digital data in a frequency band with playback capability in the memory and excluding data in other bands, it is possible to improve the efficiency of memory use and to compress the storage capacity of the memory.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the main parts of an example of an electronic device that adopts the speech synthesis method of the present invention, Figure 2 is a frequency characteristic diagram of an example of a speaker used in the same device, and Figure 3 is a waveform of each part of the same block diagram. 4 is a flowchart showing the procedure for inputting digital data into the RAM, and FIG. 5 is a flowchart showing the procedure for reproducing data stored in the RAM by voice synthesis. In the figure, 1: microphone, 2: microphone amplifier,
3: Pulse former, 4: Frequency memory counter, 5: A/D converter, 6: Interface,
7: Central processing unit (Cpu), 8: RAM memory,
9: ROM memory, 10: Voice synthesizer, 11: Amplifier, 12: Speaker.

Claims (1)

[Claims] 1. A speech synthesis device that digitizes analog information such as speech, samples this digital speech information, stores it in a memory, and reproduces the digital information in the memory as synthesized speech based on program instructions. , means for creating a plurality of sampling frequency band information of the audio digital information based on frequency components of the audio analog information, means for selecting the sampling frequency band information, and audio digital information in the selected sampling frequency band. a means for sampling only the synthesized sound and pasting it on the memory, and changing the frequency bandwidth of the synthesized sound by selecting the created sampling frequency band information.