JPH01209807A - Amplifier circuit - Google Patents
Amplifier circuitInfo
- Publication number
- JPH01209807A JPH01209807A JP63035687A JP3568788A JPH01209807A JP H01209807 A JPH01209807 A JP H01209807A JP 63035687 A JP63035687 A JP 63035687A JP 3568788 A JP3568788 A JP 3568788A JP H01209807 A JPH01209807 A JP H01209807A
- Authority
- JP
- Japan
- Prior art keywords
- collector
- input signal
- output
- power supply
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003321 amplification Effects 0.000 claims abstract description 13
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 13
- 239000003990 capacitor Substances 0.000 abstract description 9
- 230000008878 coupling Effects 0.000 abstract description 9
- 238000010168 coupling process Methods 0.000 abstract description 9
- 238000005859 coupling reaction Methods 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Abstract
Description
本発明は、入力信号の逆相の出力を得る増幅回路に関す
る。The present invention relates to an amplifier circuit that obtains an output with the opposite phase of an input signal.
逆相出力を取り出す簡易型増幅回路としては、トランジ
スター段によるエミッタ接地回路り、<ある。
第2図は、このようなエミッタ接地回路を利用したイコ
ライザ回路を示している。同図において増幅用トランジ
スタQ1には、コレクタ抵抗R3、エミッタ抵抗R4お
よびベース電位を設定する分圧抵抗rjl、rt2によ
り電流帰還バイアスが与えられろ。増幅用トランジスタ
Q1のコレクタからは入力端子!Nより結合コンデンサ
C1を介してベースに加えられた人力信号と逆相のエミ
ッタ接地出力が結合コンデンサC2を介して取り出され
、また、エミッタからは同相のエミッタ・ホロワ出力が
同じく結合コンデンサC3を介して取り出される。可変
抵抗器R5は、逆相と正相出力の合成比を?JN整し増
幅凹路全体のゲイン設定を行うために設けられ、その摺
動端子Tと接地ライン間に接続された共振器DRの共振
周波数を中心とした特定帯域成分の強調信号が出力端子
OU ’1’に得られる。A simple amplifier circuit that takes out a negative phase output is a common emitter circuit using a transistor stage. FIG. 2 shows an equalizer circuit using such a common emitter circuit. In the figure, a current feedback bias is applied to the amplifying transistor Q1 by a collector resistor R3, an emitter resistor R4, and voltage dividing resistors rjl and rt2 that set the base potential. The input terminal from the collector of the amplification transistor Q1! A human input signal applied to the base from N via coupling capacitor C1 and an emitter grounded output in reverse phase are taken out via coupling capacitor C2, and an in-phase emitter follower output is also output from the emitter via coupling capacitor C3. It is taken out. What is the composite ratio of the negative phase and positive phase outputs of variable resistor R5? An emphasized signal of a specific band component centered around the resonant frequency of the resonator DR, which is provided to set the gain of the entire JN adjustment amplification concave path and is connected between the sliding terminal T and the ground line, is output to the output terminal OU. Obtained at '1'.
増幅用トランジスタのコレクタがコレクタ抵抗を介して
電源+Vccと接続された従来の増幅回路では、電源電
圧が変動すると、変動成分が出力信号に重畳される。そ
こで、電源電圧の変動を抑えるために電源の安定化回路
を別途設ける必要がある。In a conventional amplification circuit in which the collector of an amplification transistor is connected to a power supply +Vcc via a collector resistor, when the power supply voltage fluctuates, a fluctuation component is superimposed on the output signal. Therefore, it is necessary to separately provide a power supply stabilizing circuit to suppress fluctuations in the power supply voltage.
本発明は上記の課題を解決するために、ベースに入力信
号が加えられる増幅用トランジスタのコレクタと電源と
の間に定電流源を設け、コレクタを抵抗(コレクタ抵抗
)を介して接地し、コレクタから入力信号と逆相の信号
を取り出すようにした。In order to solve the above problems, the present invention provides a constant current source between the collector of an amplifying transistor to which an input signal is applied to the base and the power supply, and connects the collector to ground via a resistor (collector resistor). A signal with the opposite phase to the input signal is extracted from the input signal.
この構成によれば、入力信号の無いときに定電流源から
の電流は増幅用トランジスタのコレクタ側と、コレクタ
抵抗側とに流れる。そして、入力信号が入力されると、
上記コレクタ側へ流れる電流mが例えば増加すると、コ
レクタ抵抗側に流れる電流量が減少する。したがって、
その出力端子からは入力信号に対して逆相の関係の出力
信号が出力される。そして、この場合の電流の変化は電
源の変動とは無関係である。・According to this configuration, when there is no input signal, the current from the constant current source flows to the collector side of the amplification transistor and the collector resistance side. Then, when the input signal is input,
For example, when the current m flowing to the collector side increases, the amount of current flowing to the collector resistance side decreases. therefore,
The output terminal outputs an output signal having a phase opposite to the input signal. And the change in current in this case is unrelated to fluctuations in the power supply.・
以下、本発明の実施例を図面を参照して詳細に説明する
。第1図はグラフィック・イコライザに用いられる、本
発明の実施例に係る増幅回路の回路図であり、第2図と
対応する部分には同一の符号を付している。第1図にお
いて、INは入力端。
子、Qlは増幅用トランジスタ、R1,R2,rt4は
抵抗、01〜C3は結合コンデンサ、+VCCは電源、
115は可変抵抗器、DRは直列共振器である。
本実施例において従来例と異なる構成は次の通りである
、。
ずなわら、本実施例の増幅回路は、第2図において増幅
用トランジスタQ1のコレクタと電源子Vccとの間に
接続されている抵抗R3に代えて、ダイオードDI、D
2.D3、抵抗R7,R8およびトランジスタQ2で構
成された定電流源1ccが接続され、増幅用トランジス
タQ1のコレクタと接地線との間にコレクタ抵抗R3が
接続されていることに特徴を有している。
その他の構成は従来例と同様であるからその説明は省略
4°る。
動作を説明する。まず、入力端子INに入力信号が与え
られていないときは、定電流源Iceからの電流■は増
幅用トランジスタQ1のコレクタ側への電流I+とコレ
クタ抵抗R6側への電流I。
とに分流される。次に、入力端子INに入力信号が与え
られると、その入力信号により増幅用トランジスタQl
のコレクタ側への電流■1がIt+iに変化すると、そ
のコレクタとコレクタ抵抗R6とが定電流源Iceで共
通に接続されているから、コレクタ抵抗R6側への電流
!、はR5−iとなる。
このことは、結合コンデンサC3側からの出力信号の位
相は入力信号のそれと同相であるのに対して、結合コン
デンサC2に接続された出力端子OUTから出力される
出力信号の位相は入力信号のそれに対して逆相となって
いる。
また、定電流源1ccの内部インピーダンスは増幅回路
の負荷インピーダンスより大きいので、本実施例の増幅
回路ではその増幅用トランジスタTrtのコレクタから
結合コンデンサC2を介して出力端子OUTから得られ
る出力信号は、電源の変動とは無関係に入力信号の逆相
の関係で出力されることになる。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram of an amplifier circuit according to an embodiment of the present invention used in a graphic equalizer, and parts corresponding to those in FIG. 2 are given the same reference numerals. In FIG. 1, IN is an input terminal. Ql is an amplification transistor, R1, R2, rt4 are resistors, 01 to C3 are coupling capacitors, +VCC is a power supply,
115 is a variable resistor, and DR is a series resonator. The configurations of this embodiment that differ from the conventional example are as follows. However, the amplifier circuit of this embodiment uses diodes DI and D instead of the resistor R3 connected between the collector of the amplifying transistor Q1 and the power supply Vcc in FIG.
2. D3, a constant current source 1cc composed of resistors R7 and R8, and a transistor Q2 are connected, and a collector resistor R3 is connected between the collector of the amplifying transistor Q1 and the ground line. . The rest of the configuration is the same as that of the conventional example, so a description thereof will be omitted. Explain the operation. First, when no input signal is applied to the input terminal IN, the current from the constant current source Ice is the current I+ to the collector side of the amplification transistor Q1 and the current I to the collector resistor R6 side. It is divided into two parts. Next, when an input signal is applied to the input terminal IN, the input signal causes the amplification transistor Ql to
When the current to the collector side of ■1 changes to It+i, since the collector and the collector resistor R6 are commonly connected by the constant current source Ice, the current to the collector resistor R6 side! , becomes R5-i. This means that the phase of the output signal from the coupling capacitor C3 side is the same as that of the input signal, whereas the phase of the output signal output from the output terminal OUT connected to the coupling capacitor C2 is the same as that of the input signal. On the other hand, it is in reverse phase. Furthermore, since the internal impedance of the constant current source 1cc is larger than the load impedance of the amplifier circuit, in the amplifier circuit of this embodiment, the output signal obtained from the output terminal OUT from the collector of the amplification transistor Trt via the coupling capacitor C2 is as follows. Regardless of power supply fluctuations, the input signal will be output in the opposite phase relationship.
以上説明したことから明らかなように本発明によれば、
定電流源により入力信号の逆相の関係となる出力信号を
出力端子から得られるように構成したから、定電圧源を
用いなくて済む結果、コストの低減された、かつ、出力
端子からは電源の変動成分が十分に除去された出力信号
が得られる増幅回路を提供することができる。As is clear from the above explanation, according to the present invention,
Since the configuration is configured such that an output signal having the opposite phase of the input signal can be obtained from the output terminal using a constant current source, there is no need to use a constant voltage source, resulting in cost reduction, and the power supply is not connected to the output terminal from the output terminal. It is possible to provide an amplifier circuit that can obtain an output signal from which fluctuation components of
第1図は本発明の実施例に係る増幅回路の回路図、第2
図は従来例に係る増幅回路の回路図である。
IN・・・入力端子、Ql・・・増幅用トランジスタ、
R6・・・抵抗、Cl−C5・・・結合コンデンサ、O
U1゛・・・出力端子、Ic’c・・・定電流源。FIG. 1 is a circuit diagram of an amplifier circuit according to an embodiment of the present invention, and FIG.
The figure is a circuit diagram of an amplifier circuit according to a conventional example. IN...input terminal, Ql...amplification transistor,
R6...Resistor, Cl-C5...Coupling capacitor, O
U1゛...output terminal, Ic'c...constant current source.
Claims (1)
タのコレクタと、電源との間に定電流源を設け、前記コ
レクタを抵抗を介して接地し、前記コレクタから入力信
号と逆相の信号を取り出す増幅回路。(1) A constant current source is provided between the collector of the amplification transistor to which the input signal is applied to the base and the power supply, the collector is grounded via a resistor, and a signal with the opposite phase to the input signal is extracted from the collector. Amplification circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63035687A JP2577946B2 (en) | 1988-02-17 | 1988-02-17 | Amplifier circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63035687A JP2577946B2 (en) | 1988-02-17 | 1988-02-17 | Amplifier circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01209807A true JPH01209807A (en) | 1989-08-23 |
JP2577946B2 JP2577946B2 (en) | 1997-02-05 |
Family
ID=12448807
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63035687A Expired - Fee Related JP2577946B2 (en) | 1988-02-17 | 1988-02-17 | Amplifier circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2577946B2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5354453A (en) * | 1976-10-28 | 1978-05-17 | Toshiba Corp | Amplifier circuit |
JPS57155809A (en) * | 1981-03-20 | 1982-09-27 | Nec Corp | Transistor amplifier |
-
1988
- 1988-02-17 JP JP63035687A patent/JP2577946B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5354453A (en) * | 1976-10-28 | 1978-05-17 | Toshiba Corp | Amplifier circuit |
JPS57155809A (en) * | 1981-03-20 | 1982-09-27 | Nec Corp | Transistor amplifier |
Also Published As
Publication number | Publication date |
---|---|
JP2577946B2 (en) | 1997-02-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |