JPH01206688A - Ic spacer - Google Patents

Ic spacer

Info

Publication number
JPH01206688A
JPH01206688A JP3240988A JP3240988A JPH01206688A JP H01206688 A JPH01206688 A JP H01206688A JP 3240988 A JP3240988 A JP 3240988A JP 3240988 A JP3240988 A JP 3240988A JP H01206688 A JPH01206688 A JP H01206688A
Authority
JP
Japan
Prior art keywords
spacer
high frequency
lead
hole
hysteresis loss
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3240988A
Other languages
Japanese (ja)
Inventor
Chitoshi Ueda
上田　千俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3240988A priority Critical patent/JPH01206688A/en
Publication of JPH01206688A publication Critical patent/JPH01206688A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/306—Lead-in-hole components, e.g. affixing or retention before soldering, spacing means

Landscapes

  • Coils Or Transformers For Communication (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To obtain an IC spacer able to restrain a high frequency electromagnetic wave without packaging a noise filter by a method wherein a magnetic bead large in a hysteresis loss is fitted to a hole which an IC lead is put through. CONSTITUTION:An IC spacer is structured in such a manner that a hole which an IC lead 1 is put through is bored in a spacer material 3 which is inserted between a packaging IC and a printed wiring board 4, and a ferrite bead 2, large in a hysteresis loss, which restrains a high frequency electromagnetic wave is fitted to the hole. The ferrite bead 2 is fitted onto the spacer material 3 concentrically with the hole bored in the spacer material 3 surrounding the IC lead 1. When digital signals pass through the IC spacer, magnetism is generated in the ferrite bead 2 around the lead 1 to induce a hysteresis loss. The hysteresis loss reflects on the digital signal as an energy loss toward a high frequency component, so that a high frequency noise is restrained. By these processes, the effect which restrains a high frequency electromagnetic wave can be obtained, so that a noise filter does not need to be packaged onto the printed wiring board.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、プリント基板に実装されるデジタル回路ＩＣ
のＩＣ用スペーサに関し、特に配線板から外部へ出力さ
れる高周波電磁波を抑制するＩＣ用スペーサに関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital circuit IC mounted on a printed circuit board.
The present invention relates to an IC spacer, and particularly relates to an IC spacer that suppresses high frequency electromagnetic waves output from a wiring board to the outside.

［従来の技術］ 従来、デジタル回路で発生する高周波電磁波に対し、印
刷配線板上の外部信号コネクタ部の直前にノイズフィル
タを配置し、これで高周波分の電磁波を抑制していた。[Prior Art] Conventionally, a noise filter has been placed immediately before an external signal connector on a printed wiring board to suppress high-frequency electromagnetic waves generated in a digital circuit.

［発明が解決しようとする課３９］ しかしながら、上述した従来の高周波電磁波の抑制方法
では、印刷配線板上にノイズフィルタを実装する必要が
有り、又、印刷配線板内部で終結する信号パターンから
発生する電磁波の抑制はノイズフィルタの追加等が必要
になり現実的には行うことが出来なかった。[Problem 39 to be solved by the invention] However, in the conventional method for suppressing high-frequency electromagnetic waves described above, it is necessary to mount a noise filter on the printed wiring board, and noise generated from signal patterns that terminate inside the printed wiring board is required. Suppression of such electromagnetic waves requires the addition of a noise filter, and cannot be done in practice.

［課題を解決するための手段］ 本発明は上記課題を解決し、ノイズフィルタを実装する
ことなく高周波電磁波を抑制することのできるＩＣ用ス
ペーサを提供することを目的とする。[Means for Solving the Problems] An object of the present invention is to solve the above problems and provide an IC spacer capable of suppressing high frequency electromagnetic waves without mounting a noise filter.

上記目的を達成するため本発明に係るＩＣ用スペーサは
、プリント基板と該プリント基板に実装するＩＣとの間
に挿入するＩＣ用スペーサにおいて、ＩＣのリードを通
す穴に高ヒステリシス損の磁性体ビーズを付けたもので
ある。　　″［実施例］ 次に、本発明の一実施例について図面を参照して説明す
る。In order to achieve the above object, the IC spacer according to the present invention is an IC spacer inserted between a printed circuit board and an IC mounted on the printed circuit board. This is the one with the . ``[Example] Next, an example of the present invention will be described with reference to the drawings.

、第１図　（ａ）　、　（ｂ）は本発明の一実施例によ
るＩＣ用スペーサの構成を示す断面図及び上面図である
。, FIGS. 1(a) and 1(b) are a sectional view and a top view showing the structure of an IC spacer according to an embodiment of the present invention.

同図において、本実施例によるＩＣ用スペーサは、印刷
配線板４と実装するＩＣ間に挿入されるスペーサ基材３
に、ＩＣのシード、１を通ずための穴を形成し、かつそ
の穴に高周波電磁波を抑制するための高ヒステリシス損
のフェライトビーズ２を付して構成される。In the same figure, the IC spacer according to this embodiment is a spacer base material 3 inserted between a printed wiring board 4 and an IC to be mounted.
A hole is formed through which the IC seed 1 passes, and a ferrite bead 2 with a high hysteresis loss is attached to the hole to suppress high frequency electromagnetic waves.

フェライトビーズ２は、図に示すようにスペーサ基材３
に形成された穴とほぼ同心円上にスペーサ基材３上に取
付けられ、ＩＣのリード１の周囲を取り巻いている。The ferrite beads 2 are attached to the spacer base material 3 as shown in the figure.
It is mounted on the spacer base material 3 almost concentrically with the hole formed in the hole, and surrounds the lead 1 of the IC.

次に、本実施例の動作について説明する。Next, the operation of this embodiment will be explained.

デジタル回路の信号は、通常ＤＣ〜数ＭＨ２で論理″０
゛、“１゛を切り替えている。この信号は、信号の変化
時、数１００ＭＨ２の高周波ノイズを発生している。Signals in digital circuits are usually DC to several MH2 and have a logic of ``0''.
This signal generates high frequency noise of several 100 MH2 when the signal changes.

本実施例の場合、デジタル信号は印刷配線板４上のＩＣ
リード１から本実施例のＩＣ用スペーサを通って、プリ
ント基板上の信号パターンへ伝わる。デジタル信号がＩ
Ｃ用スペーサを通った時、リード１の周りのフェライト
ビーズ２に磁気が生じ、ビステリシス損が生じる。この
ビステリシス損は、高周波分へのエネルギー損としてデ
ジタル信号に反映され、高周波ノイズが抑制される。つ
まりスペーサが、高周波へのノイズフィルタとして作用
する。In the case of this embodiment, the digital signal is transmitted to the IC on the printed wiring board 4.
The signal is transmitted from the lead 1 through the IC spacer of this embodiment to the signal pattern on the printed circuit board. The digital signal is I
When passing through the C spacer, magnetism is generated in the ferrite bead 2 around the lead 1, causing a bisteresis loss. This bisteresis loss is reflected in the digital signal as energy loss for high frequency components, and high frequency noise is suppressed. In other words, the spacer acts as a noise filter for high frequencies.

従って、本実施例ではノイズフィルタを用いることなく
ＩＣ用スペーサにより高周波電磁波の抑制を行うことが
できる。Therefore, in this embodiment, high frequency electromagnetic waves can be suppressed by the IC spacer without using a noise filter.

［発明の効果］ 以上説明したようにプリント基板と該プリント基板に実
装するＩＣとの間に挿入するＩＣ用スペーサにおいて、
ＩＣのリードを通す穴に高ヒステリシス損の磁性体ビー
ズを付けたことにより、高周波電磁波を抑制する効果が
あり、従来の縁に印刷配線板４上、ノイズフィルタを実
装する必要がなくなる。[Effects of the Invention] As explained above, in the IC spacer inserted between a printed circuit board and an IC mounted on the printed circuit board,
By attaching magnetic beads with high hysteresis loss to the holes through which the IC leads are passed, there is an effect of suppressing high frequency electromagnetic waves, and there is no need to mount a noise filter on the edge of the printed wiring board 4 as in the past.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）　、　（ｂ）は本発明の一実施例によるＩ
Ｃ用スペーサの構成を示す断面図及び上面図である。FIGS. 1(a) and 1(b) show I according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view and a top view showing the configuration of a C spacer.

Claims (1)

【特許請求の範囲】 プリント基板と該プリント基板に実装する ＩＣとの間に挿入するＩＣ用スペーサにおいて、ＩＣの
リードを通す穴に高ヒステリシス損の磁性体ビーズを付
けたことを特徴とするＩＣ用スペーサ。[Claims] An IC spacer inserted between a printed circuit board and an IC mounted on the printed circuit board, characterized in that magnetic beads with high hysteresis loss are attached to holes through which IC leads are passed. spacer.
JP3240988A 1988-02-15 1988-02-15 Ic spacer Pending JPH01206688A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3240988A JPH01206688A (en) 1988-02-15 1988-02-15 Ic spacer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3240988A JPH01206688A (en) 1988-02-15 1988-02-15 Ic spacer

Publications (1)

Publication Number Publication Date
JPH01206688A true JPH01206688A (en) 1989-08-18

Family

ID=12358154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3240988A Pending JPH01206688A (en) 1988-02-15 1988-02-15 Ic spacer

Country Status (1)

Country Link
JP (1) JPH01206688A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7495317B2 (en) 2005-08-01 2009-02-24 Samsung Electronics Co., Ltd. Semiconductor package with ferrite shielding structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7495317B2 (en) 2005-08-01 2009-02-24 Samsung Electronics Co., Ltd. Semiconductor package with ferrite shielding structure

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