JPH01205627A - Decoding circuit for digital transmission equipment - Google Patents

Abstract

PURPOSE:To reduce a circuit scale by constituting two BnZS(Bipolar with n Zeros Substitution Codes) each different in the number of replacing bits of one circuit. CONSTITUTION:In the reception of an output from a Bn1ZS code detecting circuit 3, a zero code replacing circuit 4 replaces the positive code and the negative code of a Bn1ZS code block comprising n1 bits latched by shift registers 1, 2 into consecutive n1-set of zeros. In the receipt of an output from a Bn2ZS code detecting circuit 5, the circuit 4 replaces the positive code and the negative code of a Bn2ZS code block comprising n2-bit latched by shift registers 1, 1', 2, 2' into consecutive n2-set of '0' codes. Then the positive code of the bipolar signal being the result of receiving an output code read sequentially synchronous ly with the clock from the output terminal of the shift register 1' is used as the negative code of the bipolar signal being the result of receiving the output code read sequentially synchronously with the clock from the output terminal of the shift register 2' to decode the original code string. Thus, the size of circuit is reduced.

Description

[Detailed description of the invention] [Required] Convert the BnZS code blocks in the received data to the original continuous n
Regarding the decoding circuit of a digital transmission device for replacing blocks of "0" codes, two BnZS decoding circuits with different numbers of replacement bits are configured in one circuit to reduce the circuit scale, and the BnZS code conversion rule is A digital transmission device equipped with two shift registers with an n1-bit configuration corresponding to the Bn,zs code conversion rule consisting of the number of replacement bits n, with the aim of automatically switching the circuit due to a change in the number of bits. In the decoding circuit, the number of replaced bits n2 of the 13n2ZS code conversion rule and the number of replaced bits n of the above Bn,zs code conversion rule.

By adding a shift register with the number of stages corresponding to the bit difference k from A Bn2zs code detection circuit is provided which monitors the code state of the received code launched into the register and detects a Bn2zs code block, and when the Bn2zS code detection circuit detects a Bn2ZS code block, a signal is sent to the two positive and negative shift registers. The positive side sign and negative side sign of the latched Bn2ZS code block are converted into n2 “0” by the above zero sign replacement circuit.
Configure to replace it with a sign.

[Industrial application field]

The present invention converts blocks of "0" codes into a specific code pattern based on the BnZS code conversion rule when a predetermined number n of consecutive "0'' codes occur in transmission data, and transmits it as a bipolar signal. The present invention relates to a decoding circuit of a digital transmission device for replacing a BnZS code block in received data with an original block of n continuous "0" codes in a digital transmission system.

[Conventional technology]

When transmitting a digital signal to a transmission path in a digital transmission device, it is necessary to convert the signal into a code format compatible with the transmission path and the receiving device before transmitting it.

For example, in regenerative relaying of digital transmission, etc., a self-timing method is adopted in which the synchronization pulse is regenerated from the bipolar signal itself sent out to the transmission path.
If "0" continues, it becomes difficult to extract and reproduce the synchronization pulse, and it becomes necessary to suppress the series of "0" codes in the transmission code.

Therefore, as one of the transmission code formats to solve the above problem, the code "0" is included in the bipolar signal sent to the transmission path.
” continues for n bits, the so-called BnZS code (Bip
polar with nZeros 5ubstit
tion Codes) are used.

[Problem to be solved by the invention]

The above BnZS code is B6ZS with n=5 bits.
B8ZS code or B8ZS code with n = 8 bits is in practical use, but on the receiving side, this received BnZS code
BnZ in bipolar signal replaced by sign conversion rule
It is necessary to decode the S code block into the original continuous "0" code string.

Conventionally, this type of decoding circuit has been configured as an independent decoding circuit according to the number n of replacement bits in the BnZS code conversion rule, and the system has been configured as two Bn decoding circuits with different numbers of replacement bits.
In order to be able to apply the ZS code conversion rule, for example, the two code conversion rules of B6ZS code and B8ZS code, two circuits, a B6ZS decoding circuit and a B8ZS decoding circuit, corresponding to the number of replacement bits must be set up independently at the time of system construction. Therefore, there is a problem that the circuit size of the receiving device becomes large, and switching of the circuit due to a change in the code conversion rule is troublesome and time-consuming.

The present invention aims to reduce the circuit scale by configuring two BnZS decoding circuits with different numbers of replacement bits into one circuit, and to automatically switch circuits in accordance with changes in the BnZS code conversion rule. purpose.

[Means to solve the problem]

As shown in FIG. 1, the principle of the present invention is shown in FIG.
n1 corresponding to the B n + Z S code conversion rule consisting of
It is equipped with two shift registers 1 and 2 with a bit configuration, one shift register sequentially inputs and latches the positive side sign of the received bipolar signal according to the B n rZS code conversion rule, and the other shift register receives The negative side sign of the bipolar signal is sequentially input and latched.
The code state of the received code latched in these two shift registers is monitored by the Bn+zs code detection circuit 3, and the Bn1ZSnl block in the received code is detected.
When an S code block is detected, the positive and negative codes of the Bn and zs code blocks latched in the two shift registers are replaced by n3 "0" codes by the zero code replacement circuit 4, and the above The original code string is decoded by using the output codes sequentially read from the positive side shift register as the positive side code of the bipolar signal, and the output codes sequentially read from the negative side shift register as the negative side code of the bipolar signal. In the decoding circuit of the digital transmission device, Bn, 2S
The number of stages of shift registers 1' and 2' corresponding to the bit difference k between the number of replacement bits n2 (n2>n, ) of the code conversion rule and the number of replacement bits ni of the above Bn, zs code conversion rule is transferred to the two shift registers 1' and 2'. 1.2 is added to the most significant bit side of each to configure two sets of positive and negative shift registers of n2-bit configuration, and the code state of the received code latched by the two sets of positive and negative shift registers of n2-bit configuration. A Bna zs code detection circuit 5 is provided to monitor the Bn2ZS code block in the received code and detect the Bn2ZS code block in the received code.
When the naZS code detection circuit detects a Bn2ZS code block in the received code, the positive side code and the negative side code of the Bn2Zs code block latched in the two sets of positive and negative shift registers are replaced by the zero sign substitution circuit 4. n2
It is now replaced with "0" codes.

[For production]

The positive side sign of the BnZS code-converted bipolar signal sent via the transmission line is transferred to shift registers 1 and 1'.
, the shift register 1°1' latches the code string while shifting it bit by bit in synchronization with the clock.

Further, when the negative sign of the bipolar signal is input to the shift register 2.2', the shift register 2.2' latches the code string while shifting it bit by bit in synchronization with the clock.

The Bn1ZS code detection circuit 3 is a shift register l.

The code state of the received codes latched to Bn2 is constantly monitored, and the code pattern of n1 consecutive received codes is Bn2.
B when it matches the code pattern according to the ZS code conversion rule
n, zs code block, and sends the detection output to the zero code replacement circuit 4.

On the other hand, the Bn223 code detection circuit 5 constantly monitors the sign state of the n2 bits of received codes latched in the positive side shift register 1.1' and the negative side shift register 2.2'. The code pattern of the received code is B
When it matches the code pattern according to the n2ZS code conversion rule, it is detected as a BnaZS code block, and the detection output is sent to the zero code replacement circuit 4.

When the zero sign replacement circuit 4 receives the detection output from the Bn1ZSnl detection circuit 3, the zero sign replacement circuit 4 receives a Bn consisting of nl bits which is latched in the shift register 1.2.

The positive side code and the negative side code of the ZS code block are replaced with n consecutive “0” codes, and the above Bn*ZS
When the detection output from the code detection circuit 5 is received, the positive side code and the negative side code of the Bn2ZS code block consisting of n2 bits latched in the shift registers 1.1' and 2.2' are successively n.

Replace with “0” codes.

Then, the output code sequentially read out in synchronization with the clock from the output end of the shift register 1' becomes the positive polarity sign of the received bipolar signal, and the output code read out sequentially in synchronization with the clock from the output end of the shift register 2'. is used as the negative side code of the received bipolar signal to decode the original code string.

〔Example〕

FIG. 2 shows one embodiment of the present invention, where the number of replaced bits n1=
It combines two decoding circuits into one circuit: a B6ZS decoding circuit with a 6-bit code and a B8ZS decoding circuit with a replacement bit number n2=8.
) is converted into a B6ZS code block consisting of a 6-bit zero code (
000000), and a B8ZS code block consisting of an 8-bit code pattern (00011011) is replaced with an 8-bit zero code (00000000).

The shift register 1 to which the positive polarity sign P of the received bipolar signal according to the BnZS code conversion rule is input has six flip-flops (hereinafter referred to as rFF) corresponding to the B6ZS code conversion rule.
J) consists of 111 to 116, and B8Z
Shift register 1 consisting of two (7) F F I It, 11a corresponding to the bit difference between the number of replacement bits n2=8 of the S code conversion rule and the number of replacement bits n,=8 of the B6ZS code conversion rule, which is -2. ' is added to the most significant side of shift register l, and these two shift registers I and 1' constitute an n2-bit shift register as a whole.

In addition, the shift register 2 to which the negative polarity sign N of the bipolar signal is input also has two 0F bits corresponding to the bit difference of ~2.
F21. A shift register 2' consisting of .about.21g is added, and these two shift registers 2, 2' constitute an n2-bit shift register as a whole.

The zero sign replacement circuit 41 is composed of FFs 42, 43 and NOR circuits 44.45, and the Q output of the FF 42 is transmitted to the FFs 111.113115.11. of the shift register 1.
and the reset terminal of FF212 and 214 of shift register 2, and the Q output of FF43 is connected to FF of shift register 2.
21. , 213.2 Is, 21g and FFII□ of shift register 1, 11. are connected to the reset terminals of Bn, zs code block and Bn2 ZS, respectively.
When detecting a code block, set the code string of the block to “0”
It is wired to replace the code.

The B6ZS code detection circuit that detects the presence of the B6ZS code block includes the positive side B6ZS code detection circuit 31 and the negative side B6
It is composed of two circuits, a ZS code detection circuit 32, and the positive side B6ZS code detection circuit 31 is an AND circuit 33,
According to 34.35, the negative polarity side B6ZS sign detection circuit 3
2 is constituted by AND circuits 36, 37, and 38, respectively.

The AND circuit 33 includes the FF11 of the shift register 1, -
116 latch code, the AND circuit 36 inputs the FF21 . ~216 latch codes are monitored, and the AND circuit 34 monitors the FF of the shift register 21.
21+ ~2 Is, the latch code of 2 Is is A
The ND circuit 37 connects the FF 11+ of the shift register 11 to
The latch codes of 11* and l Is are monitored, respectively.

Additionally, B8Z detects the presence of a B8ZS code block.
The S code detection circuit is composed of two circuits, a positive side B8ZS code detection circuit 51 and a negative side B8ZS code detection circuit 52, and the positive side B8ZS code detection circuit 51 is an AND circuit 53.
and AND circuits 53 and 54, and the negative side B8ZS sign detection circuit 52 is constituted by AND circuits 55 and 56, respectively.

The AND circuit 53 is the FF of shift registers l and 1'.
The latch codes of l 1+ to IIg and the AND circuit 55
are FF21° to 21. of shift registers 2 and 2'. The latch code of each is monitored.

First, the decoding operation for a bipolar signal based on the B6ZS code conversion rule will be explained with reference to the time chart of FIG. In addition, each waveform (a) to (1) in Fig. 3
'corresponds to each waveform at positions (a) to (i)' drawn in FIG.

Assuming that the received bipolar signal based on the B6ZS code conversion rule is an NRZ signal as shown in Figure 3 (5), this bipolar signal has a positive polarity code P as shown in Figures (C) and (d). After being converted into two unipolar signals of negative polarity sign N, they are input to the shift register 1.2, respectively.

When the positive side code P consisting of the code string shown in FIG. 3(C) is input to the input terminal 61 of the shift register 1, this positive side code P becomes F in synchronization with the clock CK shown in FIG. 3(a).
The data is sequentially latched while being shifted one bit at a time from FIII to F118.

On the other hand, the input terminal 62 of the shift register 20 is connected to the input terminal 62 of the shift register 20 as shown in FIG.
When the negative polarity side code N shown in is input, this negative polarity side code N is sequentially latched while being shifted one bit at a time to the FFs 211 to 218 in synchronization with the clock CK.

Now, as shown as block B1 in FIG. 3(6), a 6-bit code pattern (
011011), FF 11 of shift register l exists at time T1.
As shown in FIG. 3(e) to (J), the code (000101) is latched to 6 to 11+, and the code (000101) is latched to shift registers 2OFF21s to 211, as shown in FIG.
), the code (101000) is in a latched state.

Therefore, at the time T1, the AND circuit 36 in the negative side B6ZS code detection circuit 32 is connected to the FF of the shift register 2.
21s~21. The negative side code pattern (101000) peculiar to the B6ZS code latched in is detected, and the output becomes "1" as shown in Figure 3(C)'.
The circuit 37 is the FF I Is of the shift register l, 11
3-11. The positive side code pattern (0101) peculiar to the B6ZS code latched in is detected, and the output is "1" as shown in FIG. The circuit 38 outputs “1” as shown in FIG.
The output “1′” is sent to the R circuit 45.

The NOR circuit 45 in the zero sign replacement circuit 41 receives the output "l" from the AND circuit 38 and becomes the output "0" as shown in FIG. 45's output "0" is set to FF43, and FF43 outputs Q=" as shown in the same figure.
0”.

When the output of FF43 becomes Q="0" as described above, Q="0" of FF43 causes the output of FIG. 3(e) to (
As shown in J), (E) to (R)゛, the shift register 2
OFF 21+, 213.2 Is, 2 Is and FF 112.114 of shift register 1 are reset. As a result, a 6-bit B6ZS code block B1
FF11+ ~11 of shift register 1.2 corresponding to
6 and FF211 to 216 are all Q="0" (replaced.

The six consecutive “0” codes latched in the above two shift registers 1.2 correspond to the successively arriving clock CK.
The output terminals 65 and 66 of shift registers 1' and 2' are sequentially shifted one bit at a time in synchronization with FIG. 3 (1) (
As shown in t), the signals are read out as unipolar signals of both positive and negative polarities.

Then, the two unipolar signals of both positive and negative polarities read out from the shift registers 1' and 2' are sent to an OR circuit 63.
By combining the code pattern (011011) of the B6ZS code block B1 in the bipolar signal with the 6-bit zero code (000
000) is decoded.

Note that the decoding operation of block B1 described above is similar to that of block B1.
This is a case where the code "1" immediately before the start of 1 is on the negative side as shown by the code N1 in FIG. 3(d), but for example, as shown in the next block B2,
The code "1" immediately before the start of is the code Ps in the same figure (C).
When the block B1 is on the positive side as shown in , the presence of the block B1 is detected by the positive side B6ZS code detection circuit 31, contrary to the above operation, and the FF42 of the zero sign replacement circuit 41
Each FF of shift register 1.2 is reset by
Block B2 is replaced with a 6-bit zero code (000000).

Next, the decoding operation for bipolar signals according to the B8ZS code conversion rule will be explained with reference to the time chart of FIG. The waveforms (a) to (1)' in FIG. 4 correspond to the waveforms at positions (a) to (1)' shown in FIG.

In the case of B8ZS code decoding, B8ZS consisting of 8 bits
The code pattern (00011011) of the code block is 8
The original code string is decoded by replacing the bits with zero codes (00000000). B8ZS in this example
The code pattern (00011011) of the code constitutes the code pattern (00011011) for the B8zS code by adding a 2-bit code (00) to the code pattern (011011) of the B6ZS code described above.

B8ZS code block B1 in the time chart of Fig. 4
To explain the decoding operation of FIG.
As shown in e) to (1), the code (10001000) is latched, and the shift registers 2 and 2'
FF21s~21. As shown in (E) to (1) of the figure, the code (00000101) is latched.

Therefore, at the time T1, the AND circuit 53 in the positive side B8ZS code detection circuit 51 selects the shift register 1.1'.
FF11a-11. The positive side code pattern (10001000) peculiar to the B8ZS code latched in is detected, and the output becomes "l" as shown in FIG. 4(u), and the AND circuit 34 in the positive side B6ZS code detection circuit 31 FF215, 21 . of shift register 2. The negative side code pattern (01
01) is detected and the output becomes "1" as shown in the same figure (V), and upon receiving the output "1" of these two AND circuits, the AN
The D circuit 54 outputs "1" as shown in FIG.

The NOR circuit 44 in the zero sign replacement circuit 41 is given the output "1" from the AND circuit 54 and becomes the output "0" as shown in FIG.
As a result, the output "0"' of the NOR circuit 44 is set in the FF 42, and the output Q of the FF 42 becomes "0" as shown in (8)'.

When the output of FF42 becomes Q="0" as described above, the 41st m
As shown in (e) to (1) and (e) to (1), FF I L of shift register 1, 113. I Is, 1
ill and shift register 2 FF 212.214
is reset, and the OFF state of shift register 1°1' and shift registers 2 and 2' corresponding to B8ZS code block B1 is replaced with Q="0".

The 8-bit "0" code latched in each FF of the shift register is sequentially shifted one bit at a time in synchronization with the successively arriving clocks C and K, and the shift register 1'
, 2' are read out as unipolar signals having both positive and negative polarities as shown in FIG. 4(1)(t).

Then, the two unipolar signals of both positive and negative polarities read out from the shift registers 1' and 2' are sent to an OR circuit 63.
By combining the B8ZS 4 code blocks B in the bipolar signal as shown in (1)' in the same figure,
The original code string in which the 1 code pattern (00011011) is replaced with a 6-bit zero code (00000000') is decoded.

Note that the above embodiment uses B6ZS with a small number of replacement bits.
Replace the code pattern (011011) of the code with the code pattern (00011011) of the 8ZS code with a large number of bits.
), but B6
ZS code detection circuit 31, 32 and B8zS code detection circuit 5
By changing the circuit configuration of 1.52, a unique BnZS code pattern can be adopted for each code conversion rule.

〔Effect of the invention〕

According to the present invention, two BnZSs with different numbers of replacement bits
By configuring the decoding circuit with one circuit, the circuit scale can be reduced, and the circuit can be automatically switched in accordance with a change in the BnZS code conversion rule.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle of the present invention, Fig. 2 is a diagram showing an embodiment of the invention, Fig. 3 is a time chart during decoding of the B6ZS code of the above embodiment, and Fig. 4 is a diagram of the above embodiment. It is a time chart at the time of decoding of B8ZS code. 1.1', 2.2' are shift registers, 3 is Bnt
zs code detection circuit, 4 is zero code replacement circuit, 5 is Bn2
In the ZS code detection circuit, n, , n2 is the number of replacement bits of the BnZS code, and k is the bit difference between n and n2.

Claims (1)

[Claims] Two shift registers (1
, 2), and one shift register stores the received Bn
_1 The positive side sign of the bipolar signal according to the ZS code conversion rule is sequentially input and latched, and the negative side sign of the received bipolar signal is sequentially input and latched to the other shift register, and the latched signal is latched by these two shift registers. The code state of the received code is detected by the Bn_1ZS code detection circuit (
3) to detect the Bn_1ZS code block in the received code, and when the Bn_1ZS code block is detected, the Bn_1ZS code block latched in the above two shift registers is
The positive side code and the negative side code of the _1ZS code block are replaced with n_1 "0" codes by the zero code replacement circuit (4), and the output codes sequentially read from the positive side shift register are used as the positive side sign of the bipolar signal. Also, in a decoding circuit of a digital transmission device that decodes the original code string by using the output codes sequentially read from the negative side shift register as the negative side code of the bipolar signal, the Bn_2ZS code conversion rule is replaced. Number of bits n_2 (n_2
> n_1) and the number of replacement bits n_1 of the above Bn_1ZS code conversion rule.
) by adding n to the most significant bit side of each
Bn_2ZS constitutes two sets of positive and negative shift registers each having a _2-bit structure, and detects a Bn_2ZS code block in the received code by monitoring the code state of the received code latched by the two sets of positive and negative shift registers each having an n_2-bit structure.
A code detection circuit (5) is provided, and when this Bn_2ZS code detection circuit detects a Bn_2ZS code block in the received code, it detects the positive side code and the negative side of the Bn_2ZS code block latched in the two sets of positive and negative shift registers. The above zero sign replacement circuit (4) converts the code into n_2 “
1. A decoding circuit for a digital transmission device, characterized in that the decoding circuit replaces the code with a 0'' code.