JPH01204593A - Digital signal processing circuit for video camera - Google Patents

Abstract

PURPOSE:To decrease a circuit scale by using an address counter provided to a 1H delay line using a RAM in common with data setting of the RAM for a white balance circuit. CONSTITUTION:In case of setting initially data for table conversion to a RAM of a white balance circuit 5, an address data is supplied to an address of a data storage ROM whose area is designated by a CPU 11 storing the RAM address and the initial setting value of the white balance circuit 5 to apply the initial setting of the RAM of the white balance circuit 5 from the address counter of the 1H delay line. Thus, the address counter for initial setting of the RAM of the white balance circuit is not required. Thus, the scale of the system is easily reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital signal processing circuit for a video camera.

(Prior Art) FIG. 4 is a block diagram showing a color signal processing system in a digital signal processing circuit in a conventional video camera.

The analog imaging signal obtained from the CCDI is amplified by an amplifier 2, adjusted to the input level of an A/D converter 3 at the next stage, and converted into a digital signal by this A/D converter 3. This digital signal is sent to a luminance signal processing circuit (not shown), and is converted into an NTSC signal form through a color signal processing system shown in the drawing and output. Specifically, the digital signal is input to the white balance circuit 5 through the input terminal a of the switch 4, where level conversion and subtraction for white balance are performed by table conversion using a RAM, and the real-time image is Line-sequential color difference signals of R-Y and B-Y, which are data, are created. Then, this line sequential color difference signal is stored in the RAM 6a.
(See Fig. 5) is separated into RY and B-Y color difference continuous signals through one horizontal scanning period (IH) delay line 6, which is a delay circuit using a delay circuit (see Fig. 5). A predetermined waveform correction is performed in the data conversion ROM 7, and the signal is converted into an NTSC television signal by the encoder 8.

FIG. 5 shows a configuration example of the IH delay line 6, which is composed of the RAM 6a, the address counter 6b, and an interlocking double switch 6C.
The line-sequential color difference signal manually entered into the RAM 6a and the RAM 6a
By switching the signals outputted from the output lines 6d and 6e every IH period, continuous color difference signals of R-Y and B-Y are obtained on the output lines 6d and 6e.

On the other hand, the table conversion data is set in the RAM of the white balance circuit 5, and when this data is set, the switch 4 is switched to the input terminal side, and the data is set to the input side of the white balance circuit 5. is connected to the address counter 9. Then, the address data is supplied to the ROM10 and the white balance circuit 5, and the R
The data stored in OMl0 is transferred to the RAM of the white balance circuit 5. In addition, when data is set in the RAM of the white balance circuit 5, read/write switching control, switching control of the switch 4, and timing control of the IH delay line 6, encoder 8, and address counter 9 are performed according to commands from the CPU II. ing.

(Problems to be Solved by the Invention) However, in the above-described conventional digital signal processing circuit, it is desired to reduce the circuit scale.

In view of the above-mentioned circumstances, the present invention has conventionally provided a dedicated address counter 9 for setting data in the RAM of the white balance circuit 5.
Focusing on the fact that an address counter is always required for the H delay line, the circuit size is reduced by sharing this address counter.

Further, the ROM 10 and the data conversion ROM 7 are shared, and the circuit scale of the negative layer is reduced.

(Means for Solving the Problems) A digital signal processing circuit for a video camera according to the present invention includes means for converting an analog image signal obtained from an image sensor into a digital image signal, and a means for converting an analog image signal obtained from an image sensor into a digital image signal;
It creates a B-Y line sequential color difference signal, and includes a white balance circuit equipped with a RAM, a data storage ROM for initializing data in the RAM, and a line sequential color difference signal with white balance adjusted in one horizontal line. This device creates continuous color difference signals for R-Y and B-Y by delaying the scanning period, and includes a delay means equipped with an address counter. Address data is supplied to the address of the data storage ROM to initialize the RAM of the white balance circuit. Further, instead of the data storage ROM, a part of the data conversion ROM provided after the delay means is used as the data storage ROM area.

(Function) When initializing table conversion data in the RAM of the white balance circuit, the address counter of the IH delay line determines the area in which the RAM address of the white balance circuit and the value to be initialized are stored by the CPU. Address data is supplied to the specified address of the data storage ROM to initialize the RAM of the white balance circuit. For this reason, the RAM of the white balance circuit
does not require an address counter for initial setup.

In addition, the data conversion RO connected to the IH delay line
Data to be initialized in the RAM is stored in a partial area of M, and the data storage ROM is deleted to reduce the circuit scale.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of claim 1, in which an address counter 6b (fifth
(see figure) is inputted to the input terminal of the switch 4 and the ROM10.

The address counter 6b is stored in the RAM of the IH delay line 6.
The configuration is such that switching control between using it as an address counter for ROM 10 and using it as an address counter for ROM 10 is performed by a command from the CPU 1. In FIG. 1, blocks having the same configuration as the conventional one are given the same reference numerals as in FIG. 4.

Therefore, when initializing the RAM of the white balance circuit 5, the switch 4 is
is switched to the input terminal side, and the RAM address of the white balance circuit 5 is supplied from the address counter 6b of the IH delay line 16 through the input terminal of the switch 4, and at the same time, the address data for transfer and the data from the CPU 1l are supplied to the address of the ROM 10. Transfer area designation address data is supplied. The ROMIQ transfers data stored in advance for this address data to the RAM of the white balance circuit 5. When the initial setting of the RAM of the white balance circuit 5 is completed by the end of this transfer, the switch 4 is switched to the input terminal a by a command from the CPU II.
normal processing of the analog imaging signal obtained by the CCD 1 is performed.

2 and 3 are embodiments of claim 2,
In the IH delay line 26 shown in FIG. 2, the output of each output terminal of the dual selector switch 26C, the output of the address counter 26b, and the human power 26f from the CPU II are switched by the dual selector switch 17, and the output line 2
6d and 26e.

In FIG. 3, the storage area for the upper address of the data conversion ROM 7 is a table area that stores the data stored in the ROM 10. and,
In response to a command from the CPU II, the dual selector switch 17 in the IH delay line 26 switches between the address counter 26b and C.
The input from PUI 1 is switched to the input 26f side, the transfer area designation address data is output from the output line 26d, the transfer address data is output from the output line 26e, and the data is sent to the white balance circuit 5 via the terminal of the selector switch 4. is input. Further, this address specifies the address of the data conversion ROM 7, and the data in the table area is transferred to the white balance circuit 5. With the end of this transfer, the RA of the white balance circuit 5
The initial setting of M is completed. In this example, since the real-time video data and the RAM setting address are used on the same line, high-speed transfer is possible at the same speed as the real-time data.

(Effects of the Invention) As described above, according to the present invention, the address counter and the ROM for data transfer to the RAM of the white balance circuit can be reduced, and the scale of the system can be easily reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a digital signal processing circuit of a video camera according to claim 1, FIG. 2 is a block diagram showing an example of the configuration of an IH delay line, and FIG. 3 is a block diagram showing an example of the configuration of an IH delay line.
FIG. 4 is a block diagram showing a conventional example, and FIG. 5 is a block diagram showing an example of the configuration of a conventional IH delay line. 1...CCD 3...A/D converter 5...
・White balance circuit 16.26...IH delay line 7...Data conversion ROM 10...ROM (data storage ROM) Iku 2 L
JFigure 5

Claims (1)

[Scope of Claims] 1) means for converting an analog image signal obtained from an image sensor into a digital image signal, and creating line-sequential color difference signals of R-Y and B-Y from the digital image signal, A white balance circuit equipped with a RAM, a data storage ROM for initializing data in the RAM, and a white balance-adjusted line-sequential color difference signal that is delayed by one horizontal scanning period and processed for each of R-Y and B-Y. This device generates a continuous color difference signal, and is equipped with a delay means equipped with an address counter.
A digital signal processing circuit for a video camera, characterized in that address data is supplied to an address of an OM to initialize a RAM of a white balance circuit. 2) A digital signal processing circuit for a video camera, characterized in that, instead of the data storage ROM according to claim 1, a part of a data conversion ROM provided after the delay means is used as the area of the data storage ROM.