JPH01204183A - Converting circuit - Google Patents

Abstract

PURPOSE:To attain one light operation to the data of the same address for one read/write cycle in a maximum speed level by connecting a selector between the branched part of the output of a high speed memory and a light operation part, and feeding back the branching of the output of a light operation part to the input side of the selector. CONSTITUTION:The data outputted from a high speed memory 1 are inputted through a multiplexer 4 and a latch 5 to a light operation part 2. The output of the light operation part 2 is inputted through a latch 6 to a selector 3, the output of the light operation part 2 is returned through a feeding-back path F to the multiplexer 4 and the multiplexer 4 alternatively outputs data D1 or output D3 of the light operation part 2. A high speed repeating operation is executed in the loop of the feeding-back path F, a selector 4 and the light operation part 2. Thus, in the maximum speed level of the read/write cycle of the high speed memory 1, one light operation can be executed to the data of the same address for one read/write cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a conversion circuit, and more particularly to a conversion circuit that is effective for real-time video processing, display, real-time image analysis, etc. in a digital video processing system.

[Background of the invention and its problems]

Video processing 1! ! The concept is broad and includes techniques for chromakey, screen compositing, screen splitting, and other special effects that are used to make input images clearer, or to extract features and recognize images.

Video processing systems include analog processing systems, digital processing systems, and their combined systems, and digital processing systems are important in terms of the precision, reproducibility, and quantitative nature of processed results, and the diversity of processing. It is increasing. In this digital processing system, it is necessary to treat images as a collection of pixels, and in image processing for a practical number of pixels and floor FA, calculations on a pixel basis and correlations between pixels are important. 'ii The calculation becomes enormous.

For example, in order to measure the particle size distribution of 512 x 512 pixels with 8 bits each for RGB, it would take about 20 minutes per screen to measure the particle size distribution using a system equipped with a 16-bit general-purpose computer equipped with an arithmetic processor. There is an example. Even if this is calculated using a super-large computer with a processing speed of about 20 MIPS, the processing time is only a few seconds.
A small number of ICs, such as C, have been proposed to speed up video processing in the negative part. However, the functions of these dedicated ICs can only be applied to a narrow area of video processing technology, and when a video processing system is constructed using these ICs, the applications are extremely limited, and the cost is generally low. This results in poor performance. Also, these I
C has not been considered for use in combination with other ICs, and it is practically impossible to construct a multifunctional video processing system by combining these ICs.

In addition, specialized hardware is often configured for specific production lines. In this case, it goes without saying that the applications are limited, but in general, the conditions of use are also severely restricted, and the applicant of this invention has already filed a series of applications for image processing systems to address these problems. This application proposes a specific configuration for pipelining the conversion circuit in the video processing system.

Japanese Patent Application No. 62-004658 proposes a conversion circuit such as that shown in FIG.
The output of the light arithmetic unit 2 is connected to the data input Din of the high speed memory 1 via the selector 3.

With this conversion circuit, it is also possible to repeatedly perform the same arithmetic processing on a single piece of data, or to perform the same processing on a series of data groups and then sequentially store them in the high-speed memory 2.
Furthermore, extremely diverse processing such as data integration, data flk reduction, and data successive comparison becomes possible. Naturally, an address is given to the high-speed memory 1 by data D1, and No. 13 S of chip select (chip select) and WE (write enable) is input to that address, and known controls such as read and write switching of the high-speed memory 1 are performed. It is carried out. Controlling this signal S is extremely effective, for example, when writing only pixel data with a specific characteristic into the high-speed memory 2, and the number of pixels with other pixel values is accumulated while ignoring the pixel with the pixel value "o". This makes processing easier.

Roughly, data D3 is inputted to the light arithmetic section 2 as needed, and the content of the operation to be applied to the output of the high speed memory 2 in the light arithmetic section, for example, the numerical value to be added to the output when performing addition, is determined by this data D3. Given.

Note that if the number of inputs to the selector 3 is increased, the expandability of the conversion circuit will naturally increase.

It is necessary to convert this conversion circuit into a high-speed vibrator and write the result of a light operation to the data at a certain address in the high-speed memory in repeated light cycles. However, when the pipeline cycle is increased to the highest speed level of the read/write cycle of a high-speed memory, it may not be possible to secure enough calculation time in the light calculation section.

[Purpose of the invention]

This invention was devised based on this background, and at the highest speed level of read/write cycles of high-speed memory, one light operation is performed on data at the same address for each read/write cycle. The purpose of the present invention is to provide a conversion circuit that obtains the following results.

[Summary of the invention]

A conversion circuit according to the present invention includes a high-speed memory, a switching means connected to a data input of the high-speed memory, and a light arithmetic section connected to a branch of the output of the high-speed memory, the light arithmetic section of the light arithmetic section. In the conversion circuit whose output is input to the first switching stage, a selector is connected between the output branch of the high-speed memory and the light arithmetic section, and the output branch of the light arithmetic section is connected to the input side of this selector. The high-speed iterative operation is performed in the loop of the return s'I8, the selector, and the light operation section.

[Embodiments of the invention]

Next, one embodiment of the conversion circuit according to the present invention will be described based on the drawings.

In FIG. 2, the conversion circuit includes a high-speed memory such as a static RAM, a light arithmetic unit 2 connected to a branch of its data output, and a selector 3 connected to the data input of the high-speed memory 1. The output of the calculation section 2 is connected to the input side of the selector 3.

A multiplexer 4 and a latch 5 are sequentially connected between the output of the high-speed memory 1 and the light arithmetic unit 2, and the data output from the high-speed memory 1 is connected to the multiplexer and sent to the light arithmetic unit 2.
The output is input to the selector 3 via the latch 6. The output of the light arithmetic unit 2 is returned to the multiplexer 4 via the feedback path F, and the multiplexer 4 outputs the data D1 or the light arithmetic unit 2.
The output D3 is alternatively output. A latch 7 is roughly connected to the input side of the light arithmetic section 2, and data D4 to be applied to data in the memory, etc. in the light arithmetic section 2 is inputted to the light arithmetic section 2 through the latch 7.

A multiplexer 8 is connected to the address input of the high-speed memory 1, and an address (No. 3 AQ) is input directly and via a latch 9 to the multiplexer 8. An address signal AO input directly and an address signal passed through the latch are input to the multiplexer 8. A
1 is compared in comparison 610 and the comparison signal COMP+
is output.

FIG. 3 shows a time chart of the vibration line operation of the conversion circuit. The read/write enable (R/W in FIG. 3) of the high-speed memory 1 operates normally. The address signal AO is repeatedly input so as to designate one address for each cycle (one read, one write) of R/W No. 48, and the latch 9 delays 0 to the address signal by that one cycle. It is outputting No. 11 A1. The multiplexer 8 alternately outputs Ao and A every half cycle of the R/W signal (one read or write cycle), and inputs them to the address input of the high-speed memo January.

The data output Dout of the high speed memory 1 outputs data D1 corresponding to the address A2 during the read cycle.

When a different address is specified as address AO in each cycle (in FIG. 3, addresses A D + to AD7 are specified in sequence), data D is sent to the light arithmetic unit via multiplexer 4 and latch 5. 2, a predetermined calculation is performed, and the calculation result D3 is written to the same address via the latch 6 and selector 3. As is clear from Figure 3, a write cycle of A D +1 is specified,
After the read data is calculated, it is written to the same address at an appropriate timing.

If the same address is repeatedly specified as address AO, and the calculation is performed at the timing shown in Figure 3, when the second read address is specified, the data after the calculation has not yet been written to the memory, and the repeated calculation is performed. is performed only once every two cycles. Therefore, for repeated operations on the same address data, the return path F is used to immediately return the data after the light operation to the latch 5. Figure 4 shows a time chart for such an operation, in which the same address AD+ continues twice, another address AD2 is specified once, then address ADI is specified again, and then AD2 is repeatedly specified. has been done. The addresses Ao and A are compared in the comparator 10, and the comparison result COMPI becomes low level, for example, when the two match. COMP
1 is output from the multiplexer 4. The output data is immediately inputted to the light arithmetic unit 2 via the latch 5, and is computed in the next cycle. The result will be output.

The data at the first address AD is written to the address ADI after two repeated operations, and the data at the next AD2 is 1
After the calculation is performed, it is written to address AD2.

Next, when the address AD is designated, the data after two operations is stored at that address, and the data is newly read out and subjected to one operation. Next A
When D2 is repeatedly specified, the return path F is used again, and the read data (data after one operation) can be repeatedly operated.

By returning the output of the light arithmetic unit 2 to the input side of the light arithmetic unit 2 through the feedback path F in this way, the same data is subjected to repeated arithmetic operations in one R/W cycle.

FIG. 4 shows a second embodiment of the present invention, in which a memory in which read cycles and write cycles can coexist is used as a high-speed memory, such as a dual-port memory or a multi-port memory. . In this conversion circuit, the same or equivalent parts as in the first embodiment are indicated by the same reference numerals.

One of the differences from the first embodiment of the conversion circuit is that the multiplexer connected to the memory output is powered by three people, and the output of the latch 6 at the latter stage of the light operation 2 is also connected to the multiplexer 4 via the feedback path F°. This is the point that has been returned. Therefore, the multiplexer 4 can selectively select three data: the memory data output D1, the output of the light arithmetic unit 2, and the output of the latch 6.

The read address input RAin of memory 1 contains data A.
. is input directly, and the write address input W A i n
AO is input through latches 11 and 12, that is, address signal A2, which is AO delayed by two cycles, is input.If the signal delayed by one cycle in latch 11 is AI, then AO+At is In the comparator 13, A,
A2 is input as a roll signal to the comparator 14, and the multiplexer 4 outputs one of the three data based on these control signals. COMPl, COMP2
Assuming that is a signal that becomes low level when both addresses match, the relationship between these signals and the data selected by the multiplexer 4 is as shown in Table 1.

Table 1 Figure 6 shows the time chart of the same example.
The same address AD + 3 times, another address AD2 once, the first address AD + roughly 1 first AD
After the data D (ADI) of I is taken into the latch 5, the address ADI is designated again, so that COMPI becomes low level, and the output of the light arithmetic unit 2 can be returned from the feedback 18F. As a result, data D3 (ADI) obtained by performing calculations on D (ADI) three times is output from the other address AD2, then the same address AD.
Since I continues sequentially, COMPI goes to high level COMP
2 becomes low level. As a result, the data from the feedback path F' is selected, and the data D+(D(AD2)) is taken into the latch 5, and the data A which has been subjected to three calculations is
The data D3 (ADI) of D+ is taken into the latch 5 at the same time as the calculation in the light calculation section 2 of D (AD2) is completed. At the next timing, data D' (AD2) obtained by performing one operation on the data in AD2 is written to the memory address AD2, and Ds (AD, ) is again input to the light calculation unit 2 and calculated.

By providing the second feedback path F° in this manner, further calculations can be performed on the calculation results. Furthermore, since this is a memory in which read cycles and write cycles can coexist, the basic cycle of the conversion circuit can be set to 172 in the first embodiment, and since it is pipeline processing, calculations can be performed in synchronization with this extremely high-speed clock. It can be executed.

It goes without saying that the above vibe line configuration can be applied to any modification or application of the conversion circuit. Modifications and application examples of the conversion circuit will be described below as third to fifth embodiments and their modifications.

FIG. 7 shows a third embodiment of the conversion circuit, and is similar to the first embodiment.
In addition to the configuration shown in the figure, a selector 15 is also connected to the address input of the high-speed memory 1, and data D is connected to the address input of the high-speed memory 1.

is input to this selector 15. Data D4 is further input to the selector 15, allowing switching between data D1+D4. If the data to be input to the address input can be selected in this manner, it is necessary to switch the address control from the local bus to the main bus when inputting the data to the conversion main bus, and selection of the address input is essential. Furthermore, even when the high-speed memory 1 is used as a mere table, inputting data to the table and referencing data are generally separate control systems, and the selector 15 is required. Note that if the number of inputs to the selector 15 is increased roughly, the expandability of the negative layer increases to 4.

FIG. 8 shows a fourth embodiment of the conversion circuit.
In addition to the configuration of the embodiment, a selector 16 is also connected to the data input of the light calculation section 2, and data D3 is input to this selector 16. Rough data D is input to the selector 16, allowing switching between data D1 and D5. If the data to be sent to the light arithmetic unit 2 can be selected in this way, the expandability of the conversion circuit will increase. In other words, not only will you be able to select three types of data, but you will also be able to select the
In the figure, a conversion circuit IA similar to the conversion circuit in FIG.
The IB, IC, and ID C selectors 15 are omitted. ) are arranged, and the outputs of the high-speed memory 1 in each conversion circuit are all input to the selector 17. The output of the selector 17 is branched and input to the selector 16 of each conversion circuit 1, and the output of any one conversion circuit can be led to the light operation section of any other conversion circuit. It is possible to feed the output back to its own light arithmetic unit or via other conversion circuits. This allows extremely complicated conversion processing to be achieved.

10 to 13 show specific examples of the light arithmetic section, and only the specific configuration of FIG. 1 is illustrated.

In Fig. 10, a W adder 18 is adopted as a light arithmetic unit. For example, when calculating the area in a binary image or a labeled image, the pixel value is converted to A to D3 (in this case, to IJ). ) is returned to the selector 3 and stored again in the address D1 of the high-speed memory 1.As a result, the number of pixels of each pixel value in the image is counted, and the area of each label area is calculated. Desired.

Figure 11 shows the reduction as a light calculation section! ! In addition to the output of the high-speed memory 2, data D3 is input to the subtracter 19, and C3 (chip select 1, WE (write enable) No. 18 S is input to the high-speed memory 1. ,
This can also be achieved by using an adder by calculating the complement internally, and is often equivalent in concept to Figure 10. When filling the distribution after flattening with values,
The subtractor becomes important when there are many different values to be gradually reduced, such as when the number of each piece of data used for "filling" is gradually reduced.

FIG. 12 shows a maximum value extraction section 20 as a light calculation section. The maximum value extraction unit 20 compares the data stored in the high speed memory with the newly introduced data and returns the larger data to the high speed memory. Conversely, the minimum value extractor 21 returns smaller data to the high speed memory. These converting units can be used in various ways, but as shown in FIG. The fillet diameter can be easily determined by simply processing the following.

14I21 shows a conversion circuit for determining the center of gravity of a figure, which includes three sets of conversion circuits IA, similar to those in FIG.
IB and IC are connected in parallel, and each addition 1
! The x coordinate value Dx, the Y coordinate value Dy, and "1" are input to 18A, 18B, and 18C). The conversion unit nIC to which “1” is input is a circuit for quadrature to open/open by 10 degrees, and the conversion circuits IA and IB convert the integrated value of the Y coordinate when the pixel data is “1”. The value obtained by dividing by the area is the center of gravity Y
It is a coordinate. This calculation may be performed with MPtJ, or
Dedicated hardware may also be provided. Considering the versatility and compactness of the octopus system, it is preferable that such complex calculations be performed by an MPU.

Furthermore, in a labeled image, by specifying an address using the pixel value of the pixel data and adding the Dx and Dy at that time to the data stored at that address, the centroids of a plurality of labeling areas can be calculated simultaneously.

FIG. 15 shows a conversion circuit for determining chain coordinates and chain codes, which is a combination of conversion circuits LA and IB. In this embodiment, the light arithmetic unit 2 and selector 3 are omitted. The xiii standard value Dx is input to the data input of the conversion circuit IA, and the conversion circuit IB
The y-coordinate value oy is input to the data input of , and the pixel value of each pixel is registered to the address input of each conversion circuit IA, IB and the large input C3, WE. The arithmetic circuit 20 determines the starting point (for example, the point at which a raster scan scan line first enters the area) or end point (for example, the point at which a raster scan scan line leaves the area) of each labeling area from the pixel values. , that X
The coordinate value Dx is registered in the high speed memory 1 of the conversion circuit IA, and the y coordinate value Dy is registered in the high speed memory 1 of the conversion circuit IB. In this case, No. 3 S specifies writing of only the start point or end point. Then, the arithmetic circuit 20 receives neighborhood information P'l of each pixel based on the pixel value in the image memory 21.
, P'2, P'3. P'4. P'5. P'6, P'?
, P'8 are obtained and recorded in the image memory 22, and at the same time, the pixel value input from the image memory 21, that is, the labeling number, is input to the address input of each high-speed memory. As a result, the coordinates of the start and end points across Pisces a are registered in each high-speed memory at the address of the labeling number, and on the other hand, the image memory 22 can be accessed to quickly obtain the subsequent chain coordinates and chain code.

Fig. 17 shows a conversion circuit for determining area, perimeter, uniformity, and complexity, and the conversion circuits IA and IB are similar to those in Fig. 10 (selector 3 is omitted from illustration).
An arithmetic circuit 20 is connected to. The arithmetic circuit 20 outputs neighborhood information No. 18 based on the pixel value of each pixel. In the third example, the neighborhood information signal is 1-bit information indicating whether or not there is a pixel with a different pixel value from the target pixel in the four neighborhoods of the target pixel. The neighborhood information signal is input to the adder M18A of the conversion circuit IA, and its value is added to the output of the high speed memory 1. The pixel value of the target pixel is input as is to the address inputs of both high-speed memories 1, and an address is assigned to each labeled area. Add each time an address is specified by each pixel value! ! A neighborhood information signal is input to 18A, and the perimeter of the address prime number is determined. On the other hand, conversion circuit I
In B, each time a pixel value is given to the high-speed memory 1, the adder 18B can add "1" to the stored data of that pixel value. As a result, the number of pixels in each labeling area is integrated, and the area is determined. If the area and perimeter are roughly processed by an MPU, the degree of complexity can also be calculated.

The above-mentioned neighborhood information I%l signal is input to C3 of the conversion circuit IA and added to the input part of the addition N18A! Same as 18B, “1
”, the perimeter can be calculated in the same way.

FIG. 18 shows a conversion circuit for binarization, multi-value conversion, and pseudo color conversion (the light arithmetic unit and data input selector are omitted from illustration). An arithmetic circuit 20 is connected to the address input. An image memory 21 that records the pixel values of all pixels is connected to the arithmetic circuit 20, and another image memory 22 is connected to the output of the high-speed memory 1. A path 20 in the high speed memory 1 calculates a color code from the pixel values in the image memory 21 in advance. For example, in binarization processing, a pixel value is converted into a color code of "OJ" or "1" at a certain threshold level, and in multilevel processing, a multi-gradation color code is generated using a plurality of threshold levels. In order to perform pseudo-coloring, values for each of R, G, and B are generated in the high-speed memory 1 for one color code. Furthermore, the density values or RGB values output from the high-speed memory are stored in the image memory 22! FIG. 19, which is loaded and displayed, shows a conversion circuit for determining the zero-order moment about the X-axis in a binary image, and uses conversion circuits IA and IB similar to those in FIG. 10. However, in the converter '1slA, the selector 3 is omitted, and in the converter circuit IB, the selector 3 and the light arithmetic unit are omitted. The signals are stored in the high-speed memory of the conversion circuit IA as the CS and WE signals S. The coordinate value Dx is input as an address input to the high speed memory of the conversion circuit IA, and the y coordinate value Dy is input as an address input to the high speed memory of the conversion circuit IB. The high-speed memory of the conversion circuit IB stores the n-th power of a certain value as a table, and Dy
In response to the input, a value of Dy raised to the nth power is output. The output is input to the adder 18 of the conversion circuit IA, and the output is input to the adder 18 of the conversion circuit IA.
can be added to the data of the corresponding X coordinate value Dx stored in the high-speed memory 1 of . That is, in the conversion circuit IA, the value of Dy'' is accumulated and stored for each value of Dx.If the multiplied values are summed for all Dx, it becomes 0.
The next moment can be found.

Figure 20 shows a conversion circuit for determining Euler's number, and the same conversion circuits lA, IB, and IC as in Figure 10 are used.
, ID, and an arithmetic circuit 20 is connected to the address input of each high-speed memory 1. The III calculation r820 calculates the pixel value of each pixel and outputs the values of T, F, D, and E as continuous bit string information (T, F, D, E).

This information fill (T, F, D, E) is T extraction port 1111
23. F extraction circuit 24. D extraction circuit 25. E extraction circuit 2
Addition of each conversion unit r8LA, IAB, IC, ID through 6! It is input to U18. Each extraction circuit is T and F.

Extract the bit positions of D and E, and then extract the bit positions of T.

The values of F, D, and E are extracted, and the extracted values are integrated for each labeling area in each conversion step and stored in the high-speed memory 1. Euler number is G4 (near 4),
G8 (nearly 8), and when the area of each labeling region is V, it is given by G4=VE+F G8=VE-D+T-F.

In the above embodiments, addition/subtraction, maximum, and minimum value extraction were exemplified as the contents of the light operations of the conversion circuit, but in addition to these, logical operations such as R can be freely selected and adopted as long as high-speed operations are possible. I can do it.

Since the conversion unit is equipped with high-speed memory, it can be used as a general lookup table for data reference such as referring to RGB values from a so-called color code, or when labeling an image, it can store labeling information at high speed. It can be applied as a cache memory. In this case, the timing for outputting the label information is given from the neighborhood information (No. 3), a counter (address counter) is provided to specify the address of the high-speed memory of the conversion circuit, and this address counter is incremented by the neighborhood information signal. address can be specified.

Further, the selector includes any switching means such as a wired OR.

〔Effect of the invention〕

As mentioned above, the conversion circuit according to the present invention includes a light calculation section connected to the high-speed memory, and the output of the light calculation section is input to the switching means. A selector is connected between the light arithmetic unit and the output branch of the light arithmetic unit is fed back to the input side of the selector. High-speed repetitive calculations are performed in the loop between this feedback path, the selector, and the light arithmetic unit. At the highest speed level of high-speed memory read/write cycles, one read/write cycle
It has the excellent effect of performing one light operation on data at the same address in each write cycle.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conversion circuit already proposed by the applicant of the present invention, FIG. 2 is a block diagram showing a first embodiment of the conversion circuit according to the present invention, and FIG. 3 is a block diagram showing the first embodiment of the conversion circuit according to the present invention. Time chart, Fig. 4 (other time charts of the same embodiment, Fig. 5 is an abloc diagram showing the second embodiment, Fig. 6 is a time chart of the same embodiment, Fig. 7 and the following are Fig. 1) Modifications and application examples of the configuration are shown as the third to fifth embodiments and their modifications, and FIG. 7 is a schematic diagram showing the third embodiment, and FIG. 8 is a diagram showing the fourth embodiment. A block diagram showing an example, FIG. 9 is a block diagram showing the fifth embodiment, and FIGS. 10 to 13.
The figure is a block diagram showing an aspect of the light arithmetic unit in the configuration of the first leapfrog, FIG. 14 is a block diagram showing a modified example that combines the aspects of FIG. 10, and FIGS. 15 to 20 are other modified examples. FIG. ■A~ID...Conversion circuit, F--Return path, l High-speed memory, 2 Light arithmetic unit, 3 Selector, 4 Multiplexer, 5, 6.7...Latch, 8 Multiplexer, 9
Latch, 10/Comparator, 11.12 Latch, 13.1
4.Comparator, 15.16.17...Selector, 18.1
8A, 18 B, 18C adder, 19... subtractor, 20
・・Arithmetic circuit, 21. 22・Image memory, 23-・T extraction circuit, 24・F extraction circuit, 25・D extraction circuit, 26・
E extraction circuit.

Claims (3)

[Claims] (1) A high-speed memory, a first switching means connected to a data input of the high-speed memory, and a light arithmetic section connected to a branch of the output of the high-speed memory, wherein the output of the light arithmetic section is 1 In the conversion circuit input to the switching means,
A conversion circuit characterized in that a second switching means is connected between the output branch and the light calculation section, and the output branch of the light calculation section is fed back to the input side of the selector. (2) A high-speed memory, a first switching means connected to a data input of the high-speed memory, and a light arithmetic section connected to a branch of the output of the high-speed memory, wherein the output of the light arithmetic section is 1 In the conversion circuit input to the switching means,
A second switching means and a first latch are sequentially connected between the output branch and the light operation section, a second latch is connected between the light operation section and the data input, and the second latch and the second latch are connected between the light operation section and the data input. A return path returning to the input side of the second switching means is connected to the light arithmetic section, and a third switching means is connected to the address input of the high-speed memory, and the third switching means has an address input. A comparator for comparing these two address signals, which are input directly and via a third latch, is connected to the input side of the third switching means, and the output of this comparator is inputted to the second switching means as a control signal. A conversion circuit characterized by: (3) comprising a high-speed memory in which a read cycle and a write cycle can coexist, a first switching means connected to a data input of the high-speed memory, and a light calculation unit connected to a branch of the output of the high-speed memory; The output of this light calculation section is
In the conversion circuit input to the switching means, a second switching means and a first latch are sequentially connected between the output branch and the light calculation section, and a first latch is connected between the light calculation section and the data input. 2 latches are connected, a first return path returning to the input side of the second switching means is connected between the second latch and the light calculation section, and a first return path returning to the input side of the second switching means is connected between the second latch and the first switching means. is connected to a second return path returning to the input side of the second switching means, and a third latch and a fourth latch are connected in series to the write address input of the high speed memory, so that the address signal is transmitted to the third latch and the fourth latch. A common address signal is input to the third latch and the read address input of the high-speed memory, and the address signals of both are compared between the input side and output side of the third latch. A first comparator is connected between the output side of the fourth latch and the input side of the third latch, and a second comparator is connected between the output side of the fourth latch and the input side of the third latch. A conversion circuit characterized in that the output of is inputted to the second switching means as a control signal.