JPH0120362B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording apparatus, and particularly to a paper feeding mechanism thereof.

Analog signals to be recorded range from those with a fast waveform change rate (i.e. those with a high maximum frequency included in the signal) to those with a slow waveform change rate (i.e. those with a low maximum frequency included in the signal) Conventional recording devices select an appropriate paper feeding speed depending on the highest frequency included in the input signal. However, providing a paper feed speed selection mechanism has the drawback of making the device large and complicated, and reducing its reliability.

The purpose of this invention is to eliminate the above-mentioned drawbacks of conventional devices.In this invention, the paper feed speed selection mechanism is eliminated and paper feed is performed intermittently at a constant speed. That is,
In this invention, an input analog signal is converted into one word of a digital signal for each sampling period by selecting a sampling period suitable for the signal, and after writing this into a memory device, This is read out and recorded at a constant readout clock period that is not too large. The paper feeding speed during this recording is a constant speed corresponding to the reading speed. The number of unread words in the memory device gradually decreases due to the difference between the write speed and the read speed of the memory device, but when this reaches a predetermined lower limit, reading stops, paper feeding is stopped at the same time, and then the memory device Reading and paper feeding are restarted when the number of words that have not been read yet reaches a predetermined upper limit, and as a result, paper feeding is performed intermittently at a constant speed. Embodiments of the invention will be described below with reference to the drawings.

FIG. 1 is a system diagram showing the overall configuration of an embodiment of the present invention, in which 1 is an analog signal source that outputs an analog signal to be recorded, 2 is a recording control circuit, and 3 is a decoder as shown in the figure. In the example, 13a-13
A binary 8-bit digital signal is input through the output conductor of h, and the signal is output to the output line determined by the input signal among the 256 output lines numbered 0 to 255. 4 is the so-called stationary, recording head, array (stationary recording
The recording heads are arranged in a line perpendicular to the direction of paper feeding shown by the arrow 10, and the recording heads are arranged corresponding to each of the output lines of the decoder 3, and the recording heads selected by the output of the decoder 3 are Recording is then performed. 5 is a recording paper, 6 is a paper feed roller, 7 is a gear device, 8 is a paper feed motor, 9 is a motor drive circuit, 11 is an analog signal conductor, and 12 is a control signal line for the motor 8.

FIG. 2 is a block diagram showing an example of the recording control circuit 2 of FIG. 1, in which the same reference numerals as in FIG. AI indicates its analog signal input terminal, CLK indicates its clock signal input terminal, and in the example shown in the figure, the output is an 8-bit binary code representing the amplitude of the input, and the bits are output in parallel. 23 is the first memory, 24
is a second memory, which in the example shown in the figure is composed of eight parallel circuits each having 2 ⁿ bits of serial input and serial output shift registers, and CLK indicates its clock signal input terminal. The first memory 23 and the second memory 24 are collectively referred to as a memory device. 25, 26
are AND gate groups, 30 and 40 are oscillators, 31 is a binary five-stage frequency divider circuit, and 32 and 4 are respective AND gate groups.
2 are binary n-stage counters, 33 and 43 are flip-flops, 34, 44, 35,
45, 41, 47, and 48 are AND gates, 36 is a switch, 46 is an OR gate, and 50 is a pulse generation circuit.

3 is a waveform diagram showing an example of a waveform at a predetermined point in the circuit shown in FIG. Output waveform, d is output waveform of gate 48, e is gate 47
The output waveforms of each are shown.

The operation will be explained below. The oscillator 30 is a pulse oscillator, and if its pulse repetition period is T _S , the frequency dividing circuit 31 generates 2T _S , 4T _S , 8T _S ,
Pulses with periods of _16Ts and _32Ts are output, and pulses with periods of _Ts to _32Ts are selectively output by the switch 36. A pulse with an appropriate period is selected depending on the highest frequency included in the analog signal on the conductor 11, but let us assume that the period of the output pulse from the switch 36 is _TW .

The analog signal output from the preamplifier 21 has a period
With T _W as the sampling period, the signal is converted into a digital signal by the ADC 22 and input to the memory devices 23 and 24 . The oscillator 40 is also a pulse oscillator, and if its pulse repetition period is T _R , it is designed to be T _R T _S . That is, no matter what value T _W is selected, the relationship T _R T _W is always maintained.

In FIG. 3, if the power is turned on at point _tp , the counters 32, 42 and flip-flop 43 are reset by the output pulse of the pulse generating circuit 50, and from that point on, ²ⁿ pulses are input to the counter 32. After (i.e. after 2 ⁿ T _W ) the counter 32 outputs an output pulse to the flip-flop 33.
is inverted and flip-flop 43 is set. (Fig. 3 t ₁ time point). The state of the flip-flop 33 at time t _p can be either, but if it were in the state shown in FIG. The signals are sequentially shifted and input by pulses of T _W period from the gate 35 . During t _p -t ₁ , gates 41, 47, 48 are all closed, input to counter 42 is blocked, and outputs of memory devices 23, 24 are sent to gate groups 25, 26.
will be blocked. At time t ₁ , the analog signal between t _p and _{t 1} is converted into 2 ⁿ words of digital signal, and the second memory 24 is fully written, and the gate 3
5 is closed to finish writing to the second memory 24, and gate 34 is opened to start writing to the first memory 23.

Also, at the time t ₁ , the flip-flop 43 is set and the gate 41 outputs a pulse with the period _TR , and at the time t ₁
Since the gate 45 is open after that point, the second memory 24 is shifted using the pulse of the T _R period as a clock, and the gate group 26 is written in the order written earlier.
It is output after passing through. (After time _t1 , a logic "1" signal is output from the gate 47 to open the gate group 26).

At time t ₂ , 2 ⁿ T _R hours after time t ₁ , the counter is 4.
2 outputs a pulse to reset the flip-flop 43, closes the gates 41, 47, and 48 again, and stops reading. Since the motor 8 is controlled by the output of the gate 41 (for example, the motor 8 may be considered to be a stepping motor) t ₁ -
During _t2 , paper is fed at a constant speed corresponding to the period T _R , and paper feeding is stopped at point _t2 . Therefore, the signal output from the ADC 22 between _tp and _t1 is recorded on the recording paper 5 by the recording head and array 4 between _t1 and _t2 , and paper feeding and recording are temporarily stopped at time _t2 .

At time t _3, 2 ⁿ T _W hours after time t ₁ , the counter 32
outputs a pulse to invert flip-flop 33 and set flip-flop 43. From time t ₃
Reading from the first memory 23 is performed until time t ₄ after 2 ⁿ T _R hours, and writing to the second memory 24 is performed from time t ₃ until time t ₅ after 2 ⁿ T _W hours. It will be done. In this way, repeat the cycle from t ₁ − _{t 5}
The output of ADC 22 is continuously output to memory devices 23, 2.
4, and the written signals are read out at a constant speed in the order of writing and recorded in response to paper feeding at a constant speed. Reading and paper feeding may be temporarily stopped depending on the difference between the writing speed and reading speed, but even if the writing clock cycle T _W is changed, it is not necessary to change the paper feeding speed accordingly. do not have.

Furthermore, although the circuit shown in FIG. 2 shows a design example in which writing to the memory devices 23 and 24 is started immediately after the power is turned on, and the data is read and recorded, the flip-flop is 43 in a reset state so that recording is started after the recording start signal is given.

Furthermore, in conventional recording devices, when the waveform change speed of an input analog signal is fast, it is sometimes necessary to convert this into a digital signal, temporarily store it in a memory device, and then read it out from the memory device at an appropriate speed and record it. However, it is easy to add the above-described functions of memory devices in conventional recording devices to the memory devices 23 and 24 of the present invention.
For example, if a read clock period with the relationship 2T _S < T _R < 4T _S is used, when T _W ≥4T _S , the operation is the same as that described above with respect to FIGS. 2 and 3, and T _W = When T _S or T _W = 2T _S , the
A circuit for blocking the clock signal input to the ADC 22 after the time corresponding to _t3 may be added.

Note that in the embodiment shown in FIG. 2, the memory device 2
Although a shift register is used as 3 and 24, the memory device of the present invention is not limited to a shift register, and any memory device that reads in the order of writing may be used.RAM (random access memory) may be used for this purpose. It is easy to use FIFO (first
-in-first-out) memories are also suitable for such applications. Furthermore, the memory devices 23 and 24 shown in FIG. 2 have a storage capacity of 2×2 ⁿ words as a whole, and start reading when the number of unread words reaches 2 ⁿ words, and when the reading of these 2 ⁿ words is finished. The control was such that reading was stopped and then reading was restarted when the number of unread words reached 2 ⁿ words again, but depending on the configuration of the memory device, writing and reading can be performed at the same time. Specifically, it can be designed to appropriately control the start and stop of reading depending on the relationship between the number of words that have been read and the number of words that have not yet been read. For example, the first and second numerical values are determined in advance, and when the number of unread words in the memory device becomes less than or equal to the first numerical value while the memory reading device is operating, the operation of the memory reading device is stopped and the operation is stopped. If the number of unread words becomes equal to or greater than a second value while the reading is stopped, the reading may be restarted.

As described above, according to the present invention, the sampling period of the input analog signal is set to an appropriate value for the analog signal, while the paper feeding speed is kept constant regardless of the sampling period, and the paper feeding selection mechanism By omitting this, the device can be made smaller and lighter, and its reliability can be improved.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the recording control circuit of FIG. 1, and FIG. 3 is a waveform at a predetermined point of the circuit of FIG. 2. FIG. 1...analog signal source, 2...recording control circuit,
3... Decoder, 4... Recording head array, 5... Recording paper, 8... Paper feed motor, 22
...ADC, 23, 24...Memory device (23...
...first memory, 24...second memory).

Claims (1)

[Claims] 1. A plurality of recording heads are arranged on a recording paper of a recording device in a direction perpendicular to the traveling direction of the recording paper, and a recording head is selected from among the plurality of recording heads according to the amplitude of an input signal. In a recording device having a stationary, a recording head, and an array configured to record on the recording paper using a recording head, an analog signal to be recorded is input, and this analog signal is arbitrarily selected at each variable sampling period. An analog-to-digital converter that converts the digital signal into a one-word digital signal and outputs it; a memory device in which the digital signal is continuously written and temporarily held using the variable sampling period as a write clock period; a memory reading device for reading each word of a digital signal stored in the memory device in the order in which it was written at a constant read clock period not greater than the writing clock period; When the number of unread words exceeds a predetermined second value while the operation of the memory reading device is stopped, the operation of the memory reading device is started. A readout control device, a paper feed control device that feeds the recording paper at a speed determined by the readout clock cycle and starts and stops the paper feed in synchronization with the start and stop of the memory readout device. A recording device characterized by: 2. The memory device includes a first memory and a second memory, and when writing to the first memory is completed, writing to the second memory is started, and writing to the second memory is started.
When writing to the first memory is completed, writing to the first memory is started, and when writing to either memory is completed, the read control device activates a memory reading device to start reading from the one memory, The present invention is characterized by comprising means for stopping the memory reading device when reading from that memory is finished, and restarting the memory reading device when writing to the other memory is finished to start reading from the other memory. A recording device according to claim 1.