JPH01202023A - Logical level control circuit - Google Patents

Abstract

PURPOSE:To remove the dispersion of a level shift quantity especially on the low level side and to obtain an optionally level-shifted low level output by connecting resistor elements between an output part of a logical gate and a power supply and extracting a level shifted output from a node between the resistor elements. CONSTITUTION:Serial resistors R1, R2 are connected in parallel with an FET Q1 having constant current characteristics as a load element and an output voltage VOUT is extracted from a node between the resistors R1, R2. Thereby, the low level output can be optionally controlled by controlling the resistance values of the resistors R1, R2. When a depression type FET shorted between the drain and gate is used as the resistor element, the resistor element stabilized against the dispersion of the threshold voltage or the like of the FET can be obtained and the resistor element excellent in uniformity and controllability can be obtained.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a logic level control circuit used for logic level conversion from a DCFL (directly coupled FET logic) circuit to an ECL circuit, for example, to eliminate variations in level shift amount, especially on the low level side. At the same time, the resistor element is connected between the output part of the logic gate and the power supply, and the level-shifted output is taken out from the middle of the connection for the purpose of measuring the low-level output that has been arbitrarily level-shifted.

[Industrial application field]

The present invention relates to logic level control circuits, particularly GaAs/M
Compound semiconductor FETs such as ES-F8T and HEMT
The present invention relates to a logic level control circuit used for logic level conversion from a DCFL circuit using, for example, an ECL circuit.

[Conventional technology]

In general, it is necessary to adjust the logic level within a logic circuit or in the human output section to ensure consistency with other circuits, and a level shift circuit is essential for this purpose. That is, when converting the logic level of a DCFL circuit used in a compound semiconductor FET such as GaAs/MBS-FET or HEMT to the logic level of an ECL circuit, when the power supply voltage is -2V, the logic level of the DCFL circuit is For example, -1,2V (high level side) and -1,9V (low level side), while ECL
The logic levels of the circuit are, for example, 1-r-o, sv (high level side) and -1.8V (low level side), and therefore a conversion circuit (level control circuit) for such logic level voltages is required.

FIG. 5 shows an example of a level control circuit as a conventional technology, in which Q6 is an enhancement type FET as a switching element. FET, Di is a diode for level shifting, Ql is the depletion type FET, and a current driving type FET whose gate is connected to the connection point between Ql and the level shifting diode D1 (that is, the output side of the level control circuit) This is an enhancement type FET.

In this way, in conventional circuits, a rectifying element such as a diode or FET is used as a level shifting element, and a constant current circuit is combined with this to perform level shifting. The amount of shift is determined by the characteristics of the current circuit, and the amount of shift fluctuates due to variations in those characteristics, making it difficult to finely adjust the amount of shift. That is, in the circuit using the above-mentioned MES-FBT or HEMT, level shifting is performed using a Schottky diode, but if the diode is about the same size as the FET, the amount of shift is 0.6 to 0.8 V, Adjustment of smaller shift amounts is difficult.

In particular, in a DCFL using a rectifying element for level shifting as shown in FIG. When a substantially positive power supply voltage (ground potential in this case) is applied to the gate of the enhancement type FET Ql, the amount of shift in the output voltage V Although it can be determined relatively easily by the resistance and the output current flowing there, the amount of voltage shift on the low level side (i.e., the input voltage V
1, the FET Q5 as a switching element is turned on, and the gate of the enhancement type FBT Ql has a level slightly shifted from the negative side power supply voltage VEE (for example, level shifted by about 0.3 to 0.4 V). A voltage is applied to the enhancement type FIET Ql
Low-level output voltage V obtained by passing a small amount of current through. It is difficult to set the LIT shift amount to a predetermined value, and it is an important issue to be able to accurately adjust such a voltage shift on the low level side.

[Problem to be solved by the invention]

The present invention was made to solve such problems,
By using a voltage dividing resistor as a load element instead of the level shift element described above, it is possible to eliminate variations in the amount of level shift, especially on the low level side, and to change the level-shifted low level output arbitrarily. .

[Means to solve the problem]

In order to solve this problem, the present invention provides a logic level control circuit in which a resistance element is connected between the output part of a logic gate and a power supply, and a level-shifted output is taken out from the middle of the resistance element.

As the resistance element, it is preferable to use a plurality of depletion type FETs whose drains and gates are short-circuited and connected in series depending on the power supply voltage.

[For production]

According to the above configuration, it is possible to arbitrarily adjust (that is, arbitrarily level shift) the output level from the middle of the resistance element, and in particular, it is possible to arbitrarily control the output on the low level side.

As mentioned above, by using a depletion type FET with the drain and gate shorted as the resistance element, it is possible to provide a stable resistance element even with variations in the threshold voltage of the FET, etc. A resistance element with excellent uniformity and controllability can be obtained.

〔Example〕

FIG. 1 shows a level control circuit as an embodiment of the present invention, in which an FE having constant current characteristics is used as the load element.
Series resistors R1 and R2 are connected in parallel with TQl, and the output voltage VOUT is taken out from a connection point in the middle. Therefore, by adjusting the resistance values of the resistors R1 and R2, the low level output can be arbitrarily controlled. Note that in this case, the high level output is approximately at ground potential.

FIG. 2 shows a level control circuit as another embodiment of the present invention, in which the resistors R1 and R2 are replaced by drain
Depletion type FETs O2 to O5 whose gates are short-circuited are used.

FIG. 6 shows the current-voltage characteristics of a depletion type FET with its drain and gate shorted.As shown in FIG. 6, this FET operates in a linear region (characteristics close to resistance). In this case, the current value is stable and hardly fluctuates with respect to fluctuations in the threshold voltage Vth.

(In addition, in Fig. 6, the Vth ranges from -300 mV to -80 mV.
The characteristic change when the voltage is changed to 0 mV is shown. )
.

In this respect, for example, in order to realize a level shift amount of about 0.1V, the resistance element needs to have high uniformity and controllability, but if the linear region of the FET as described above is used as the operating region, Since stable current characteristics can be obtained even with variations in the threshold voltage of the FET, the FET with its drain and gate short-circuited can be used as a stable resistor.

Furthermore, as mentioned above, GaA is used in the FET as a load element.
When using an s-MES-FET or HEMT, a Schottky junction is used for the gate, so if the voltage between the gate and source exceeds, for example, 0.8V, the gate-source current (Schottky The current flowing through the Schottky gate becomes excessive, so in the circuit shown in FIG. To prevent this, the four FIETs O2 to O5 are connected in series so that the voltage applied across each FET (resistance element) is, for example, about 0.6V.

That is, in the present invention, among the current-voltage characteristics shown in FIG. 6, Vns (the drain-source voltage of each resistance element)
A region where the voltage is approximately 0.8V or less will be used.

In this way, in the embodiment shown in FIG. 2, the output voltage V on the low level side. U is the resistance value of '6W++W2 to Q4, W2 is the resistance value of the FBT O5, and the resistance value is adjusted by the FET0 size and the like.

FIG. 3 shows a level control circuit as still another embodiment of the present invention. In the embodiment shown in FIG. Depletion type FETs O2 to O5 (with their drains and gates short-circuited) are connected in parallel with the depletion type FLL:T Ql as the resistance elements, as in the embodiment shown in FIG. Alternatively, only the FETs O2 to O5 may be used as resistance elements without using the FET Ql as a load element of the logic gate, that is, the FBT O5. In addition, as in the embodiment shown in FIG.
By providing the FET Ql having the above-mentioned constant current characteristics (saturation characteristics), it is possible to improve current cutoff and to more sharply switch logic levels.

FIG. 4 shows an example in which the circuit shown in FIG. 2 is used as a control circuit for controlling the ECL level (i.e., an output circuit for an IC to output an ECL level output from a DCFL circuit). Enhancement type FET Q for current drive is connected to the output terminal (connection point between FET Q4 and Q5).
The gate of No. 7 is connected, and the termination resistor R0 and the ECL circuit are connected to the output side (source side). In this case, the voltage applied to the gate of the enhancement type FBT lower (the voltage taken out from the connection point of the FBT Q4 and Q5) is on the high level side (FBT O,
6 is off state) is almost the ground voltage, and the low level side (FET Q6 is on state) is -1.6V (
(level shift by 0.4V from VEE).

As a result, the conduction state of the enhancement type FET Q7 is controlled, and a high-level voltage V is supplied to the ECL circuit by a current flowing from the output side (source side) of the FET Q7 through the termination resistor R1. 1
．． is approximately -0.8V, the voltage V on the low level side. U7 is about -
The voltage is set to L 8 V, and a predetermined level conversion is performed.

Figure 7 shows the transfer characteristics (
V to VIn. Figure 8 shows the level control circuit according to the present invention shown in Figure 4 above.
3 shows the transfer characteristics of a level conversion circuit (from a DCFL circuit to an ECL circuit). As shown in FIG. 7, in the conventional inverter circuit shown in FIG. For example -30
On the other hand, in the circuit of the present invention as shown in FIG. 4, as shown in FIG. The value of Vln (at the time of switching from level to low level) is approximately constant regardless of fluctuations in Vth, and stable operation can be performed.

〔Effect of the invention〕

According to the present invention, it is possible to eliminate variations in the amount of level shift, especially on the low level side, and it is possible to obtain a stable low level output that has been level shifted by a predetermined amount.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a level control circuit as one embodiment of the invention, FIG. 2 is a diagram showing a level control circuit as another embodiment of the invention, and FIG. 3 is a diagram showing a level control circuit as another embodiment of the invention. Figure 4 is a diagram showing a level control circuit as another embodiment; Figure 4 is a diagram showing an example in which the circuit in Figure 2 is used as a control circuit for controlling the ECL level; Figure 5 is a level control circuit as a prior art. FIG. 6 is a diagram showing the current-voltage characteristics of a depletion type FET as a load element used in the circuits of FIGS. 2 to 4, and FIG. FIG. 8 is a diagram showing a state in which the transfer characteristic depends on the threshold voltage of the load element. FIG. 8 is a diagram showing a state in which the transfer characteristic of the circuit of FIG. 4 depends on the threshold voltage of the load element. (Explanation of symbols) Q1 to Q5... Depletion type FET. Q6-Q7...Enhancement type FET.

Claims (1)

[Claims] 1. A resistive element is connected between the output part of the logic gate and the power supply,
A logic level control circuit characterized in that a level-shifted output is taken out from the middle of the output. 2. As the resistance element, a plurality of depletion type FETs whose drains and gates are short-circuited are connected in series according to the power supply voltage, and a level-shifted output is taken out from a predetermined connection point. Logic level control circuit according to item 1. 3. The logic level control circuit according to claim 1, wherein a depletion type FET whose gate and source are short-circuited is connected in parallel with the resistive element. 4. Depletion type FEs connected in series
3. The logic level control circuit according to claim 2, wherein a depletion type FET whose gate and source are short-circuited is connected in parallel with T.