JPH01200749A - Synchronizing step-out detecting system - Google Patents

Abstract

PURPOSE:To attain the detection of a stable synchronizing step-out and to execute a precise switching control by finding the mean voltage value of synchronous condition detecting information obtained at a carrier reproducing circuit and comparing it with a reference voltage. CONSTITUTION:A multilevel orthogonal amplitude modulation signal outputted from an intermediate frequency amplifier is branched with a distributor 12, and is introduced through synchronous wave detectors 11a and 11b, LPFs 13a and 13b, and operational amplifiers 14a and 14b to identifying devices 15a and 15b. Then, a fixed logic process is executed with a receiving logic circuit 17, and demodulation digital data D1-D4 are obtained. On the other hand, from a synchronous condition detecting signal BS of a logic circuit 18 for a carrier reproducing control, the mean voltage value DS of the signal BS is compared with a reference voltage by a synchronizing step-out detecting circuit 30, and a synchronizing step-out signal ES is obtained. By the signal ES, a receiving system switching circuit is controlled and is switched from an existing system to a standby system. Thus, a precise switching control is realized.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a multi-level quadrature amplitude modulated wave signal (multi-level QAM signal).
The present invention relates to a method for detecting synchronization loss in a digital wireless communication device that receives and demodulates a signal.

(Prior Art) In recent years, a multi-value quadrature amplitude modulation (multi-value QAM) method has been adopted as one of the transmission methods for digital microwave communication. This transmission method transmits digital data by changing both the amplitude and phase of the carrier wave, and can achieve more efficient transmission. FIG. 5 is a basic block diagram showing the configuration of a receiving system of a digital wireless communication device to which this type of modulation method is applied. After being converted into an intermediate frequency band signal by the generated local oscillation signal, the signal is guided to a demodulator 5 via an intermediate frequency amplifier 4 having an automatic interest rate control function, where the original signal is demodulated.

By the way, in digital wireless systems, the effects of fading etc. cause a drop in received power and waveform distortion.
This may cause a deterioration in the code error rate. Therefore,
Conventional communication devices employ, for example, a space diversity reception method, and also provide an automatic equalization circuit in the intermediate frequency band to compensate for waveform distortion. When the error rate deteriorates, quality deterioration is prevented by switching the reception system from the working device to the standby device. However, conventional devices detect out-of-synchronization, which is necessary for switching the receiving system and switching the control logic of the automatic equalization circuit, by comparing, for example, the spectrum of the demodulated signal when synchronization is established and the spectrum when synchronization is lost. This is done by detecting minute power differences.

For this reason, it is difficult to perform stable detection, and stable detection requires complex and extremely high-precision adjustment.

As mentioned above, the conventional out-of-sync detection method has the problem that it is difficult to stably detect out-of-sync, and stable detection requires complicated and highly accurate adjustment. The invention focuses on this point, and provides a 1+1 method for detecting out-of-sync for a digital wireless communication device, which enables out-of-sync detection to be detected stably without any adjustment, and which is easy to configure and handle, and allows accurate switching control at all times. This is what we are trying to provide.

[Structure of the Invention] Problem (Means for Solving Isatsuki) The present invention solves the problem by converting a multi-value demodulated signal obtained by synchronously detecting a multi-value (22n-value) orthogonal amplitude modulated wave into an in-phase component and a quadrature denominator. a demodulation circuit that obtains demodulated data by performing logical processing on the identification output of the discriminator; and a demodulation circuit that obtains demodulated data by performing logical processing on the identification output of the discriminator; A digital wireless communication device comprising: a carrier regeneration circuit that obtains synchronization state detection information, supplies the carrier phase error information to a voltage 111Q controlled oscillator in accordance with the synchronization state detection information, and generates a recovered carrier wave from the voltage controlled oscillator. In this case, calculate the average voltage value of the synchronization state detection information obtained by the carrier wave regeneration circuit, compare this average voltage value with the reference voltage range at the time of synchronization establishment, and if the above average voltage value falls outside this reference voltage range. The system outputs an out-of-synchronization detection signal.

(Function) As a result, out-of-synchronization is detected using a signal obtained by logically processing the synchronization state detection information obtained by the carrier wave regeneration circuit, that is, the identification signal consisting of a binary digital signal output from the A/D converter. This is done by finding the average voltage value of It becomes possible to detect easily and stably. Therefore, by using this detection result, it is possible to always perform stable and accurate switching control of the receiving system, etc., depending on the state of line quality. In addition, since the detection is performed by using the synchronization state detection information obtained by the existing carrier wave regeneration circuit, it can be realized extremely easily by just adding a few circuits such as a circuit to calculate the average voltage value and a circuit to perform comparison. There are some advantages.

(Example) Next, an example of the present invention will be described using the 1.6QAM method as an example. FIG. 1 is a circuit block diagram showing the configuration of a demodulation section of an IGQAM digital wireless communication device. This demodulator includes two synchronous detectors 11a for in-phase and quadrature phase.
, 11b, the 16Q AM signal output from an intermediate frequency amplifier (not shown) is branched into two by a divider 12, and each of the above-mentioned synchronous detectors], l a, j 1. introduced into b,
Here, each signal is synchronously detected. Then, the four-level baseband signals of in-phase and quadrature components obtained by these synchronous detectors 11a and llb are passed through a low-pass filter 13a.
, ], 3b to remove harmonic components, and perform level control using operational amplifiers 14a and 14b, the discriminator 15a
, 1.5b, respectively.

Each of these discriminators 15a and 1.5b is composed of a 4-bit A/D converter, and is synchronized with the clock regenerated from the 4-value baseband signal by the clock regeneration circuit 16. Each value baseband signal is identified by A/D conversion, and the top two of these identification outputs SII to S4I, S] and Q-34Q are
Bits S], I, S21 and SIQ, S2Q are subjected to predetermined logic processing by a reception logic circuit]7 to obtain demodulated digital data D1 to D4.

In addition, in this device, the discrimination outputs S] to S4I, S] and Q-84Q of the discriminators 15a, ], and 5b are respectively introduced into the logic circuit for carrier wave regeneration control]8. This logic circuit] 8 includes an exclusive OR circuit 8 for obtaining a carrier wave phase error signal, a synchronous state detection circuit 82, and a synchronous state detection circuit 82, which detects the carrier wave phase error signal according to the detection signal output from the synchronous state detection circuit 82. It is composed of a flip-flop circuit 83 for sending out data. Of these, the synchronization state detection circuit 82 includes a first circuit 84 that detects a state when synchronization is stable, a second circuit 85 that detects a state when synchronization is pulled in, and these first and second circuits 84.85. A third circuit 86 performs an AND operation with the clock CLK in an AND circuit 86b to obtain a synchronization state detection signal. The first circuit 84 includes each of the identification outputs SI
I~S41, lower 2 bits of 5IQ-94Q S3I
, S4I, S3Q, and S4Q are processed by exclusive OR circuits 84a and 84b, respectively, and their respective outputs are subjected to AND processing by an AND circuit 84c, thereby obtaining a synchronization state detection signal when synchronization is stable. Further, the second circuit 85 outputs each of the identification outputs S 11-84 I, S 1 . Q
- Upper 2 bits of 34Q SII, S21 and SI
Q and S2Q are processed by the exclusive OR circuits 85a and 85b, and their respective outputs are processed by the exclusive inverting OR circuit 85c, so that the signal point is aligned with the synchronization axis I at the time of synchronization pull-in.
The synchronization state detection signal is obtained by selecting only the positions having the same distance from the orthogonal axis Q.

Then, the carrier phase error signal outputted from the flip-flop circuit 83 of the carrier wave regeneration control logic circuit 18 is introduced into the voltage controlled oscillator (VCO) 20 after passing through one DC amplifier with a built-in loop filter. Ru. This VCO 20 generates a regenerated carrier wave with a frequency corresponding to the DC voltage value of the carrier phase error signal, and this regenerated carrier wave is shifted by 90 degrees with the in-phase regenerated carrier wave by the 90' phase divider 2]. After being split into a regenerated carrier wave,
The signals are supplied to the synchronous detectors 11-a and 11-llb, respectively.

By the way, this device is a logic circuit for controlling carrier wave regeneration mentioned above]
The out-of-synchronization detection circuit 30 is provided, which utilizes the synchronization state detection signal that is impaired by 8. This out-of-sync detection circuit 30 is
It is composed of a direct current amplifier 3] and a unit circuit 32,
The synchronization state detection signal is introduced into the DC amplifier 3 to find its average voltage value, and this average voltage value is converted to the minimum base voltage value Vr when synchronization is established in the Schmitt circuit 32.
When compared with el', a detection signal indicating an out-of-synchronization is output when this minimum reference voltage V ref is not present.

With such a configuration, first of all, in a state where synchronization is achieved without the influence of fading etc., the signal position of the 16QAM signal and the identification outputs of the discriminators 15a and 15b SII~
The relationship with S4 I,'S IQ-84Q is that when the synchronization is stable, the signal point (black circle) always exists within the diagonal line as shown in Figure 2 (a), so the carrier wave regeneration control logic circuit]8 Regardless of the output of the second circuit 85, the output AS of the first circuit 84 is always 1'' as shown in FIG. CLK is output as is as a synchronization state detection signal. Therefore, the average voltage value of the synchronization state detection signal BS output from the DC amplifier 3 of the out-of-synchronization detection circuit 30 is equal to the mark rate of this synchronization state detection signal BS. Since the voltage is 1/2, the voltage exceeds the minimum reference voltage value V rcf as shown in FIG.

-1,0- On the other hand, the received power decreases due to the effects of fading, etc.
Assuming that this causes the current system to go out of sync, 16
As shown in FIG. 2(b), the positions of the signal points of the QAM signal are random on a circumference whose radius is centered on the intersection of the phase axes and extends to the stationary position. Therefore, the first and second circuits 84 of the carrier wave regeneration control logic circuit 18
．． The output of 85 becomes <"o" as shown in FIG. 4AS, or changes randomly between "0" and "1".

For this reason, the synchronization state detection signal BS output from the third circuit 86 becomes a signal with a low mark rate that contains many "0" levels as shown in FIG. The average voltage value DS of the synchronization state detection signal BS output from the amplifier 31 is the minimum reference voltage value V.
It becomes less than ref. Therefore, the Schmitt circuit 32 outputs the out-of-synchronization detection signal ES (level "1"), and the out-of-synchronization detection signal ES causes the reception system switching circuit 4
0 switches from the working system to the protection system, and from then on, reception and demodulation operations are performed using this protection system.

In this way, in this embodiment, the discriminator] 5a.

Using the synchronization state detection signal BS obtained by logically processing each identification output of 15b, the average voltage value DS of this synchronization state detection signal BS is obtained, and this average voltage value DS and the minimum base 4 voltage value V ref' Since the out-of-synchronization detection signal ES is generated by comparing the values with Out-of-synchronization can be detected with great accuracy and without the need for adjustment. Furthermore, since out-of-synchronization is detected by using the synchronization state detection signal BS generated by the existing carrier wave regeneration control logic circuit 18, the DC amplifier 31 calculates the average voltage value DS of the synchronization state detection signal BS.
By newly providing a Schmitt circuit 32 for comparing the voltage values and generating the out-of-sync signal ES, the out-of-sync detection signal can be generated, and this can be realized with a very simple configuration. can.

It should be noted that the present invention is not limited to the above embodiments = 12
- No. For example, the circuit for calculating the average voltage value of the synchronization state detection signal and the circuit for generating the out-of-sync detection signal by comparing the voltage values may be configured using circuits other than DC amplifiers and Schmitt circuits. Modulation method is IGQ
32QAM in addition to AM.

It can be implemented in the same way even in the case of IGQAM or higher, such as G4QAM. In addition, the method of using the out-of-synchronization detection signal, the configuration of the demodulator and the carrier wave regeneration circuit, etc. can be modified in various ways without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, the average voltage value of the synchronization state detection information gathered by the carrier wave regeneration circuit is obtained, and this average voltage value is compared with the reference voltage range at the time of synchronization establishment. By outputting an out-of-synchronization detection signal when the above average voltage value falls outside this reference voltage range,
Out-of-synchronization can always be detected stably without any adjustment, thereby providing an out-of-synchronization detection method that is easy to configure and handle and can always perform accurate switching control.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing the configuration of a demodulation section of a digital wireless communication device to which an out-of-sync detection method is applied in an embodiment of the present invention, and FIG. 2 shows the relationship between the signal position of an 18QAM signal and the identification output. 3 and 4 are signal waveform diagrams used to explain the operation of the circuit shown in FIG. 1, respectively, and FIG. 5 is a block diagram showing the basic configuration of the receiving system of the digital wireless communication device. 1.1a, llb...Synchronous detector, 12...Distributor,
1.3a, 13b・Low pass filter, 14a. 14b... operational amplifier, 15a, 15b... discriminator, 16... clock regeneration circuit, 17... receiving logic circuit,
18... Logic circuit for carrier wave regeneration control, 19... DC amplifier with loop filter, 20... Voltage controlled oscillator (VCO), 21... 90° signal divider, 30...
- Out-of-synchronization detection circuit, 31... DC amplifier, 32...
・Schmidt circuit. Applicant's agent, patent attorney Takehiko Suzue, and C5J(v') size ^ /"1 /"1 n ()

Claims (1)

[Claims] The multi-value demodulated signal obtained by synchronously detecting a multi-value (2^2^n-value) orthogonal amplitude modulated wave is discriminated by a discriminator for each in-phase component and quadrature component, and the discrimination output of this discriminator is subjected to logical processing. A demodulation circuit obtains demodulated data by performing a logical process on predetermined bits of the identification output of each of the discriminators to obtain carrier phase error information and synchronization state detection information, and according to this synchronization state detection information, In a digital wireless communication device comprising a carrier wave regeneration circuit that supplies the carrier wave phase error information to a voltage controlled oscillator and generates a recovered carrier wave from the voltage controlled oscillator, an average voltage value of synchronization state detection information obtained by the carrier wave regeneration circuit. is determined, and this average voltage value is compared with a reference voltage range at the time of synchronization establishment, and when the average voltage value falls outside the reference voltage range, an out-of-synchronization detection signal is output. Out-of-sync detection method.