JPS63217754A - Digital phase demodulation circuit - Google Patents

Abstract

PURPOSE:To stabilize decision by providing a gate circuit making a binarized threshold value asymmetrical in the phase plane so as to reduce malfunction of carrier synchronization establishment decision. CONSTITUTION:In a carrier recovery PLL and a feedback selection circuit 13, the PLL is controlled to be a closed loop in a prescribed timing, a reference signal from a tan<-1>theta circuit 8 is received to lead a control signal for a VCO 16. The synchronizing establishment decision information is given from a carrier synchronization establishment detection circuit 30. In this case, the MSB and its low-order 2-bit in a demodulation output D of a 128-phase decode circuit 12 are inputted to a binarized gate circuit 40, which has an asymmetrical threshold level on the phase plane and its output is inputted to the detection circuit 30.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a digital phase demodulation circuit that detects a specific sequence (synchronization word) in a received signal and determines synchronization establishment based on its presence or absence. .

(Prior Art) As a development of digital transmission methods such as the QPSK modulation method, a method is being considered in which, for example, a QPSK signal and an N-phase PSK signal are time-division multiplexed and transmitted. This method allows for flexible transmission/reception system configuration because it is possible to simultaneously secure channels with different transmission qualities as necessary.

As an example, there is a signal format published in Japanese Patent Application Laid-Open No. 60-500192 entitled "Signal Encoding/Decoding Apparatus". This example uses a QPSK signal and a 128-phase P
This is a method in which the SK signal is time-division multiplexed, transmitted, and demodulated. To demodulate such a phase modulated wave, a circuit as shown in FIG. 6 is required.

In FIG. 6, a time division multiplexed signal (input signal A) of a QPSK signal and a 128-phase PSK signal supplied to input terminal O
) is supplied to the synchronous detection circuit 2.3.

The output of the local oscillator 16 is directly supplied to the synchronous detection circuit 2 as a regenerated carrier, and the output of the local oscillator 16 is supplied to the synchronous detection circuit 3 as a regenerated carrier after passing through the 90° phase shift circuit 1. The output of the synchronous detection circuit 2.3 is
An analog-to-digital (hereinafter referred to as A/D) converter 6. provides synchronous detection outputs B and C through a low-pass filter 4.5.
7, respectively.

Now, if the phase of the input signal A is θ, and the oscillation phase of the local oscillator 16 matches the absolute phase of the input, the outputs B and C have voltage values of COS θ and sin θ, respectively.

Using these values, the arctangent (θ-jan
4(sin θ/cos θ), the phase θ of the input signal A can be obtained.

Signals B and C are therefore digitized in an A/D converter 6.7 using the lower bits excluding their MSB to
Calculation of data at ~90°, that is, the above jan ” (s
inθ/cosθ) is calculated. This calculation result is output from the tan' circuit 8, and this tan'
The circuit 8 is constituted by a read only memory (ROM).

Furthermore, the MSB of the output of the A/D converter 6.7 is 2 bits, and this content can be used as the demodulation output of the QPSK signal, and also as phase quadrant information when demodulating the 128-phase phase modulation signal. Can be used.

In a digital phase demodulation circuit, even when the recovered carrier used for synchronous detection is not synchronized with the input modulated wave, it is necessary to recover the clock that operates the digital circuit.

In this circuit, the clock can be regenerated stably by squaring the detection output B (in-phase) and the detection output C (quadrature) and adding them together. This utilizes the relationship (sin θ) 2+ (cos θ) 2 = 1. That is, as shown in the figure, the synchronous detection output BS
C is supplied to two east circuits 23 and 22, respectively, and the squared outputs are added by an adder 21. The added output is then supplied as a control voltage to a voltage controlled oscillator of a clock regeneration phase-locked loop circuit (hereinafter referred to as a clock regeneration PLL circuit) 19. As a result, from this clock regeneration PLL circuit 19,
A clock for maintaining the synchronous detection output B%C in an orthogonal relationship can be obtained.

Next, a description will be given of means for reproducing a reproduced carrier for performing synchronous detection.

From the tan-1θ circuit 8, as mentioned above, 0° to 90
6 phase demodulated signals are output. Now, considering the time when a QPSK modulated wave whose phase state is limited to, for example, 45°, 135°, 225°, or 315' is being received, the demodulated output of the tan'θ circuit 8 is The data can be seen as 45° - 5 =. On the other hand, considering the time when the 128-phase PSK modulated wave is received, it is rare that the demodulated output data of the tan-1θ circuit 8 is 45° at this time.
It is uniformly distributed at 90 degrees and cannot be considered as white noise. Therefore, it is necessary to provide a PLL feedback selection circuit 13 for carrier regeneration and to close the PLL loop only at the time when the QPSK modulated wave is being received to regenerate the carrier.

For this purpose, it is necessary to identify whether it is the QPSK modulated wave reception time or the 128-phase PSK modulated wave reception time when the input signal A arrives in the carrier asynchronous state. The circuits that perform this identification are the digital delay detection circuit 25 and the reference pattern detection circuit 27, and the PLL operation mode of the carrier recovery PLL feedback selection circuit 13 is controlled by the identification signal thereof.

The digital delay detection circuit 25 outputs the digitized detection outputs B and C, and the detection output B' detected one clock ago,
By finally performing a difference calculation with C', the phase difference between the detection outputs caused by the carrier asynchronous state is reduced, and the detection probability of the reference pattern, which will be described later, is increased. In other words, if it is in the QPSK modulated wave receiving state, 4
Since the 5° data is input continuously, the difference output should be zero.

The reference pattern detection circuit 27 is a digital delay detection circuit 2
5, it is determined whether or not a predetermined pattern has been detected. Then, based on the detection timing of the reference pattern, the reception time of the QPsK modulated wave is determined and an identification signal is generated. Since it is necessary to increase the probability of detection even in a carrier asynchronous state and a low C/N state, this reference pattern usually employs a PN signal limited to two-phase modulation.

Next, a method and means for detecting phase correction of QPSK demodulated output and establishment of synchronization will be explained. If the oscillation phase of the local oscillator 16 matches the absolute phase of the input signal, the MSB output of the A/D converter 6.7 will be as shown in the following table.

The decoding circuit 9 linearly converts these MSBs into so-called Gray code/straight binary.
This is a code conversion circuit. Here, the control of the oscillation phase of the local oscillator 16 takes four undefined states for each 906 because quadrants are not distinguished.

In order to eliminate the influence of this unstable state, the phase state of the local oscillator 16 is detected by the non-modulation period included in the input signal A, and the phase state of the local oscillator 16 is detected, and the phase state of the A/D converter 6 converted into a straight binary code is detected. The correction value may be added to the MSB output, that is, the output of the decoding circuit 9. These effects are
It is obtained by the phase error detection circuit 28 and the 2-bit adder 11.

Thereby, the QPSK signal can be demodulated without switching the oscillation phase of the local oscillator 16 itself. The phase error detection circuit 28 is a circuit that detects a reproduced carrier (0°, 90°, 180°, 2706) from a reference phase included in an input signal using a frame synchronization detection output of a predetermined sequence. Depending on the output, the 2-bit adder 11
Determine the addition value of

Next, a method for detecting establishment of carrier synchronization will be explained.

This detection uses the QPSK demodulation output and the 128-phase P
This can be achieved by detecting the presence or absence of the reference pattern using the SK demodulation output. Now, suppose the modulation phase is 45° and 225°.
If a reference pattern limited to is sent, that pattern corresponds to the positions of the black star and white star shown on the phase plane shown in FIG. In FIG. 7, the numerical value on the circumference is the value (binary number) D of the 128-phase PSK demodulated output.

The above reference sequence (pattern) can be detected in the low C/N and carrier pull-in process by setting a threshold between α and β in Figure 7, binarizing the signal, and then comparing the patterns. good.

In FIG. 6, necessary bits of the output of the 128-phase decode circuit 12 are led to the binarization gate circuit 29,
Further, by inputting this output to the carrier synchronization establishment detection circuit 30, the establishment of synchronization is determined. The 128-phase decode circuit 12 has a 0° to 90° angle from the tan jθ circuit 8.
A 128-phase demodulated signal is obtained using data within the range of and quadrant information that can be determined from the QPSK demodulated output. The synchronization establishment output obtained by detecting the reference pattern in the carrier synchronization establishment detection circuit 30 is used as a carrier regeneration PL.
The signal is supplied to the L feedback selection circuit 13 and used to switch the loop band and gain of the PLL, thereby making the operation of the carrier regeneration PLL more stable. Furthermore, the synchronization establishment output is also supplied to the signal processing circuit 31 shown in FIG.
The signal processing circuit 31 is used to determine that the =10-128 phase demodulated signal is reliable.

(Problems to be Solved by the Invention) In the above-described device, if the phase error detection circuit 28 malfunctions during the carrier pull-in process, it may be mistakenly regarded as a carrier synchronization established state. This is because the 128-phase decode circuit 12 uses the output of the 2-bit adder 11 as quadrant information. In particular, if a signal format in which every other reference pattern is alternated is input, it becomes impossible to recover from the above malfunctioning state.

In a low C/N state or in a carrier attraction process, malfunctions of the phase error detection circuit 28 are likely to occur. For example, if the state shown in FIG. 8 occurs, that is, the I-axis (in-phase)
, if the demodulation axis of the Q axis (orthogonal) is completely shifted by 90'', then the reference pattern should not be detected, but another signal is detected as the reference pattern,
It is determined that carrier synchronization is established. In addition, if a signal format (often adopted for transmission of video signals, etc.) in which frame synchronization is achieved by inverting every other reference signal and transmitting it is input, the detuning frequency will change to the reference signal during the carrier pull-in process. If the insertion interval matches the insertion interval, the previous reference signal will be stably detected, and the malfunction state will not be able to be extracted, resulting in a serious system defect.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a digital phase demodulation circuit that can reduce malfunctions in carrier synchronization establishment determination and obtain stable determination.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a binary gate circuit that constitutes a means for detecting a reference pattern using a part of a polyphase PSK demodulated output. A new gate circuit is added to make the threshold value asymmetrical in the phase plane.

(Function) When using the above means to identify a reference pattern for determining synchronization establishment in this system, the binarization threshold level of a part of the 128-phase PSK demodulation output is set as shown in FIG. 2, for example. Since it is asymmetric, it is possible to prevent error detection in the reference sequence in the carrier acquisition process, and it is possible to make a stable and accurate determination of carrier synchronization establishment.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which a QPSK signal and a
This is a device that demodulates a phase modulated wave that is time-division multiplexed and transmitted with a 28-phase PSK signal. The circuit of the present invention differs from the circuit shown in FIG. 6 in the binarization gate circuit 40, and the other parts are the same as the circuit shown in FIG. Therefore, the same parts will be given the same reference numerals as in FIG. 6, and instead of the explanation of FIG. 1, the explanation will focus on the different parts.

As explained above, the carrier regeneration PLL and feedback selection circuit 13 selects the PLL at a predetermined timing.
A voltage-controlled local oscillator 1 is controlled so that L is in a closed loop, and receives a reference signal from a tan 'θ circuit 8.
It operates to obtain a control signal for controlling 6. Therefore, the carrier regeneration PLL and feedback selection circuit 13 require a signal that provides closed loop formation timing. Furthermore, in a low C/N reception state or in a carrier pull-in process, information for controlling the loop gain and loop band for the carrier PLL is required.

In order to control the loop gain and loop bandwidth, it is necessary to determine whether the system has established synchronization, widen the pull range until synchronization is established, and narrow the pull range once synchronization is established. Provides system stability.

Furthermore, if the loop gain is increased when synchronization has not been established, phenomena such as oscillation will occur, so it is better to suppress the gain during synchronization pull-in and increase the gain to improve responsiveness once synchronization is established. To get this kind of behavior,
A synchronization establishment determination signal is required, and this information is provided from the carrier synchronization establishment detection circuit 30.

The present invention is characterized by the configuration of the path for obtaining the carrier synchronization establishment determination signal. That is, of the demodulated output of the 128-phase decode circuit 12, the MSB and its lower two bits are supplied to the binarization gate circuit 40.

The binarization gate circuit 40 includes, for example, an AND circuit 41 that receives the lower two bits as an input, and an output of this AND circuit 41 and an MS.
An exclusive OR circuit 42 that takes B as an input, and an AND circuit 43 that takes the output of the AND circuit 41 and the MSB as inputs.
and an OR circuit 44 which receives the output of the AND circuit 43 and the output of the exclusive OR circuit 42, and supplies the output of the OR circuit 44 to the carrier synchronization establishment detection circuit 30.

The above binarization gate circuit has α'-
It has a threshold level at β′, and on the phase plane,
This results in an asymmetrical threshold level. When the signal of phase region E1 is input, it outputs high level "H", and when the signal of phase region E2 is input, it outputs low level "H".
Output L''.

By providing the binarization gate circuit 40 having asymmetric threshold levels on the phase plane in this way,
Problems like those of the past no longer occur.

That is, as shown in Figure 3, even if the demodulation axes I and Q are shifted by 90 degrees, even if an alternating signal at the position of the black triangle is input, this signal will not be binarized as in the conventional method. .

This invention is not limited to the above embodiments, but the fourth embodiment
It may be configured as shown in FIG. 5(a) and FIG. 5(a).

Note that this figure shows another embodiment of only the essential parts of the present invention.

The embodiment shown in FIG. 4 includes a binarization gate circuit 40, an AND circuit 41, an exclusive OR circuit 42, and an inverter 5.
0, AND circuits 51.53, and OR circuits 52.54. The threshold level of this circuit, when shown on a phase plane, is at the position indicated by the α'-β' line shown in FIG. 3(b).

The embodiment shown in FIG. 5(a) is an example in which a read-only memory 60 is used from the beginning without using a logic circuit. The threshold level of this memory, when shown on a phase plane, is, for example, the position shown by the α'-β line shown in FIG. This is convenient if you want to easily store multiple items and use them selectively.

In the above explanation, the binary gate circuit is used to obtain information to notify the PLL feedback selection circuit for carrier regeneration of the establishment of synchronization, but the purpose of use is not limited to this purpose. The resulting circuit can be used in various locations.

[Effects of the Invention] As described above, the present invention can reduce malfunctions in carrier synchronization establishment determination, and can provide a digital phase demodulation circuit that obtains stable determination.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of this invention, FIGS. 2 and 3 are phase plane diagrams shown to explain an example of the operation of the circuit of this invention, and FIG. 4 is a circuit diagram showing another embodiment of this invention. FIG. 5 is a circuit diagram showing another embodiment of the present invention and a phase diagram showing its operating characteristics. FIG. 6 is a diagram showing a conventional digital phase demodulation. FIG. 7 is a diagram showing the circuit. FIG. 8 is a phase plane diagram shown to explain the operation of the circuit of FIG. 6. 1...90° phase shift circuit, 2.3...synchronous detection circuit,
4.5...Low pass filter, 6.7...A/D converter, 8...tan 4θ circuit, 9...decoding circuit,
11... 2-bit adder, 12... 128-phase decoding circuit, 13... PLL feedback selection circuit for carrier regeneration, 14... D/A converter, 15... low-pass filter, 16... Local oscillator, 25... Digital delay cold wave circuit, 27... Reference pattern detection circuit, 28
... Phase error detection circuit, 30 ... Carrier synchronization establishment detection circuit, 31 ... Signal processing circuit, 40 ... Binarization gate circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] (1) Synchronization in which an input signal in which M (M is an integer) PSK wave having an absolute phase and a synchronization word limited to two-phase modulation are time-division multiplexed is synchronously detected using regenerated carriers of detection axes with mutually orthogonal phases. A detection means, an analog-to-digital conversion means for converting each synchronous detection output with different detection axes into a digital signal, and each lower bit output except for the most significant bit of each analog-to-digital conversion output is used to convert the phase of the input signal to 0. means for obtaining a demodulated output expressed in the range from 90° to 90°; second demodulating means for obtaining quadrant information output of the first demodulated output using each of the most significant bit outputs;
, or a binarization gate unit that binarizes the output decoded using the demodulation output of the second demodulation unit or both demodulation outputs, and detects the synchronization word using the binarized demodulation signal. and a means for indicating a carrier establishment state by detecting or continuously detecting the synchronization word, and the binarization gate means makes the threshold of the signal input thereto asymmetric in the phase plane. A digital phase demodulation circuit characterized in that a means is provided.