JPH01200645A - Element isolation of molecular device - Google Patents

Element isolation of molecular device

Info

Publication number
JPH01200645A
JPH01200645A JP63025243A JP2524388A JPH01200645A JP H01200645 A JPH01200645 A JP H01200645A JP 63025243 A JP63025243 A JP 63025243A JP 2524388 A JP2524388 A JP 2524388A JP H01200645 A JPH01200645 A JP H01200645A
Authority
JP
Japan
Prior art keywords
film
element isolation
polymer
insulating film
si3n4
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63025243A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP63025243A priority Critical patent/JPH01200645A/en
Publication of JPH01200645A publication Critical patent/JPH01200645A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce a wiring capacitance value and to realize a high speed by using a high-polymer insulating film such as a polyimide film or the like for element isolation of an electronic circuit device containing a molecular element formed on an insulating substrate or the like. CONSTITUTION:P-type and n-type polydiacetylene films 2, a gate insulating film 3 composed of Si3N4 or the like and a gate electrode 4 composed of a conductive film are formed on the surface of an insulating substrate 1; a field- effect transistor is formed. In order to isolate this transistor from adjacent elements, an element isolation insulating film 5 by a high-polymer film such as polyimide or the like or by a two-layer structure of an Si3N4 film or the like and the high-polymer film is formed; an extraction electrode 6 is formed on this element isolation insulating film 5 via a contact hole, and is connected to the adjacent elements.

Description

【発明の詳細な説明】 C産業上の利用分野〕 本発明は高分子素子を用いた集積回路装置の素子分離法
に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a device isolation method for integrated circuit devices using polymer devices.

〔従来の技術〕[Conventional technology]

従来、高分子素子は単体素子の提案はあったが集積回路
装置の提案はなく、その為に、高分子素子の素子分離に
関する具体的な提案はなかった。
Conventionally, there have been proposals for single elements for polymer elements, but no proposals for integrated circuit devices, and for this reason, there have been no concrete proposals regarding element separation of polymer elements.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、上記従来技術によると、高分子素子による集積
回路が構成し難いと云う問題点があった。
However, the above-mentioned conventional technology has a problem in that it is difficult to construct an integrated circuit using polymer elements.

本発明は、かかる従来技術の問題点をなくし、高分子素
子による集積回路の構成を可能とする素子分離法を提供
する事を目的とする。
It is an object of the present invention to provide an element isolation method that eliminates the problems of the prior art and makes it possible to construct an integrated circuit using polymer elements.

〔課題を解決するための手段〕[Means to solve the problem]

上記問題点を解決するために、本発明は、高分子素子に
よる集積回路装置の素子分離に高分子絶縁膜を用いる手
段をとる事を基本とする。
In order to solve the above problems, the present invention is based on the use of a polymer insulating film for element isolation of an integrated circuit device using polymer elements.

〔実 施 例〕〔Example〕

以下、実施例により本発明を詳述する。 Hereinafter, the present invention will be explained in detail with reference to Examples.

第1図は本発明の一実施例を示す分子素子の素子分lf
f1i造である。すなわち、絶縁基板1の表面には、P
型及びrI型のポリジアセチレン膜2及び5isN+等
から成るゲート絶縁膜3、導電膜から成る′ゲート電極
4が形成され、電界効果トランジスタが形成され、該ト
ランジスタの隣接素子との分離のために、ポリイミド等
の高分子膜かあるいはSi3N4膜等と高分子膜の2層
構造による素子分雛絶縁膜5か形成され、該素子分離絶
縁膜5上に引出し電極6がコンタクト穴を介して形成さ
れ、隣接素子との接続が行なわれる。
FIG. 1 shows an element component lf of a molecular device showing an embodiment of the present invention.
It is made by f1i. That is, on the surface of the insulating substrate 1, P
A gate insulating film 3 made of type and rI type polydiacetylene films 2 and 5isN+, and a gate electrode 4 made of a conductive film are formed to form a field effect transistor, and in order to separate the transistor from adjacent elements, An element isolation insulating film 5 having a two-layer structure of a polymer film such as polyimide or a Si3N4 film and a polymer film is formed, and an extraction electrode 6 is formed on the element isolation insulating film 5 through a contact hole. Connections with adjacent elements are made.

尚、絶縁基板1は、ポリジアセチレン2等の素子構成高
分子基板であっても良く、更に、三次元集積回路の場き
には素子分離絶縁膜5は平面方向の素子分離のみならず
、立木方向の素子分離に用いられても良い事は云うまで
もない。
The insulating substrate 1 may be an element-constituting polymer substrate such as polydiacetylene 2. Furthermore, in the case of a three-dimensional integrated circuit, the element isolation insulating film 5 is used not only for element isolation in the planar direction but also for Needless to say, it may also be used for directional element separation.

〔発明の効果〕〔Effect of the invention〕

本発明により高分子素子による集積回路装置の形成が可
能となる効果がある。更に、高分子材による素子分離は
、高分子材の低誘電率(ε舛3)から配線容量の低減に
よる高速化を計ることができる効果もある。
The present invention has the effect of making it possible to form an integrated circuit device using polymer elements. Furthermore, element isolation using a polymer material has the effect of increasing speed by reducing wiring capacitance due to the low dielectric constant (ε 3) of the polymer material.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す高分子素子の素子分離
構造図である。 1・・・絶縁基板 2・・・ポリジアセチレン 3・・・ゲート絶縁膜 4・ ・ ・ゲート電極 5・・・素子分離絶縁膜 6・・・引出し電極 以  上 出願人 セイコーエプソン株式会社
FIG. 1 is a diagram of an element isolation structure of a polymer element showing an embodiment of the present invention. 1... Insulating substrate 2... Polydiacetylene 3... Gate insulating film 4... Gate electrode 5... Element isolation insulating film 6... Leading electrode and above Applicant Seiko Epson Corporation

Claims (1)

【特許請求の範囲】[Claims]  絶縁基板上等に形成された分子素子を含む電子回路装
置の素子分離にはポリイミド膜等の高分子絶縁膜を用い
る事を特徴とする分子装置の素子分離法。
A device isolation method for molecular devices characterized in that a polymer insulating film such as a polyimide film is used for device isolation of electronic circuit devices including molecular devices formed on an insulating substrate or the like.
JP63025243A 1988-02-05 1988-02-05 Element isolation of molecular device Pending JPH01200645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63025243A JPH01200645A (en) 1988-02-05 1988-02-05 Element isolation of molecular device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63025243A JPH01200645A (en) 1988-02-05 1988-02-05 Element isolation of molecular device

Publications (1)

Publication Number Publication Date
JPH01200645A true JPH01200645A (en) 1989-08-11

Family

ID=12160543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63025243A Pending JPH01200645A (en) 1988-02-05 1988-02-05 Element isolation of molecular device

Country Status (1)

Country Link
JP (1) JPH01200645A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010009074A (en) * 2002-03-14 2010-01-14 Semiconductor Energy Lab Co Ltd Electrophoretic display device and method of fabricating electrophoretic display device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010009074A (en) * 2002-03-14 2010-01-14 Semiconductor Energy Lab Co Ltd Electrophoretic display device and method of fabricating electrophoretic display device
US8599469B2 (en) 2002-03-14 2013-12-03 Semiconductor Energy Laboratory Co., Ltd. Display device and method of fabricating the same
US9122119B2 (en) 2002-03-14 2015-09-01 Semiconductor Energy Laboratory Co., Ltd. Display device and method of fabricating the same
US9513528B2 (en) 2002-03-14 2016-12-06 Semiconductor Energy Laboratory Co., Ltd. Display device and method of fabricating the same
US10088732B2 (en) 2002-03-14 2018-10-02 Semiconductor Energy Laboratory Co., Ltd. Display device and method of fabricating the same
US10663834B2 (en) 2002-03-14 2020-05-26 Semiconductor Energy Laboratory Co., Ltd. Display device and method of fabricating the same

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