KR910017656A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR910017656A
KR910017656A KR1019910001172A KR910001172A KR910017656A KR 910017656 A KR910017656 A KR 910017656A KR 1019910001172 A KR1019910001172 A KR 1019910001172A KR 910001172 A KR910001172 A KR 910001172A KR 910017656 A KR910017656 A KR 910017656A
Authority
KR
South Korea
Prior art keywords
conductive layer
regions
insulating film
semiconductor device
conductive
Prior art date
Application number
KR1019910001172A
Other languages
Korean (ko)
Other versions
KR940003606B1 (en
Inventor
요시노리 오꾸무라
아쓰시 하찌스가
Original Assignee
시기 모리야
미쓰비시뎅끼가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 시기 모리야, 미쓰비시뎅끼가부시끼가이샤 filed Critical 시기 모리야
Publication of KR910017656A publication Critical patent/KR910017656A/en
Application granted granted Critical
Publication of KR940003606B1 publication Critical patent/KR940003606B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

내용 없음No content

Description

반도체장치Semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1도는 본 발명의 1실시예를 표시한 반도체장치의 컨택트 구조를 설명하는 단면도.1 is a cross-sectional view illustrating a contact structure of a semiconductor device according to one embodiment of the present invention.

Claims (1)

제 1도전형의 반도체기판상의 소자분리영역간에 소정의 간격을 두고 적어도 2개의 제 2 도전형의 불순물영역이 형성된 반도체장치에 있어서, 상기 소자분리영역상에 형성되는 동시에 상기 반도체기판상의 상기 분순물영역간에 제 1의 절연막을 끼워 형성된 복수의 게이트전극과, 상기 적어도 2개의 제 2 도전형의 불순물영역중의 한쪽의 불순물영역에 접속되고, 상기 게이트전극의 측벽부 및 상부에 제 2의 절연막을 끼워 형성된 제 1의 전도층과, 상기 적어도 2개의 제 2도전형의 불순물 영역중의 다른쪽의 불순물영역에 접속되고, 적어도 그 단부가 상기 제 1의 도전층상에 제 3의 절연막을 끼워 형성된 제 2의 도전층과 상기 제 1의 도전층에 접속된 제 1의 배선층과, 상기 제 2의 도전층에 접속된 제 2의 배선층을 포함하는 반도체장치.A semiconductor device in which at least two second conductivity type impurity regions are formed at predetermined intervals between device isolation regions on a first conductive semiconductor substrate, wherein the impurities formed on the device isolation region are simultaneously formed on the device isolation region. A plurality of gate electrodes formed by sandwiching a first insulating film between the regions, and an impurity region of one of the at least two second conductivity type impurity regions, and a second insulating film formed on the sidewall portion and the upper portion of the gate electrode. A first conductive layer sandwiched between the first conductive layer and the other impurity region of the at least two second conductive type impurity regions, the at least one end of which is formed by sandwiching a third insulating film on the first conductive layer; A semiconductor device comprising a second conductive layer, a first wiring layer connected to the first conductive layer, and a second wiring layer connected to the second conductive layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910001172A 1990-03-13 1991-01-24 Semiconductor device KR940003606B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2-63671 1990-03-13
JP2063671A JP2623019B2 (en) 1990-03-13 1990-03-13 Semiconductor device

Publications (2)

Publication Number Publication Date
KR910017656A true KR910017656A (en) 1991-11-05
KR940003606B1 KR940003606B1 (en) 1994-04-25

Family

ID=13236052

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910001172A KR940003606B1 (en) 1990-03-13 1991-01-24 Semiconductor device

Country Status (3)

Country Link
JP (1) JP2623019B2 (en)
KR (1) KR940003606B1 (en)
DE (1) DE4107883A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4113733C2 (en) * 1990-04-27 1996-01-25 Mitsubishi Electric Corp Field effect transistor, method of manufacturing the same, and DRAM using the same
US5276344A (en) * 1990-04-27 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Field effect transistor having impurity regions of different depths and manufacturing method thereof
DE4143389C2 (en) * 1990-04-27 1994-11-24 Mitsubishi Electric Corp Field-effect transistor for dynamic memory
JP2934325B2 (en) * 1990-05-02 1999-08-16 三菱電機株式会社 Semiconductor device and manufacturing method thereof
USRE40790E1 (en) 1992-06-23 2009-06-23 Micron Technology, Inc. Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device
US5229326A (en) * 1992-06-23 1993-07-20 Micron Technology, Inc. Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5559773A (en) * 1978-10-27 1980-05-06 Hitachi Ltd Method of fabricating mis semiconductor device
JPS58142579A (en) * 1982-02-18 1983-08-24 Mitsubishi Electric Corp Mos transistor
JPS6110271A (en) * 1985-05-02 1986-01-17 Hitachi Ltd Semiconductor device
JPS61292951A (en) * 1985-06-21 1986-12-23 Hitachi Ltd Semiconductor integrated circuit device
JP2548957B2 (en) * 1987-11-05 1996-10-30 富士通株式会社 Method for manufacturing semiconductor memory device
JPH0221652A (en) * 1988-07-08 1990-01-24 Mitsubishi Electric Corp Semiconductor storage device
KR940005729B1 (en) * 1989-06-13 1994-06-23 삼성전자 주식회사 Method of making dram cell

Also Published As

Publication number Publication date
KR940003606B1 (en) 1994-04-25
DE4107883A1 (en) 1991-09-19
JP2623019B2 (en) 1997-06-25
JPH03263330A (en) 1991-11-22

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