JPH01196177A - Field-effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To enhance a pinch-off characteristic by installing a gate structure where the thickness of a uniformly doped active layer is changed from a source to a drain in the active layer between the source and the drain. CONSTITUTION:A uniformly doped active layer 2 is formed on a semiinsulating substrate 1 of, e.g., GaAs by an MBE method or the like; the film thickness of the active layer 2 from the side of a source to the side of a drain is increased gradually from ds to da. A gate (G) is formed on the face of the active layer 2 which is inclined between a source (S) and a drain (D) due to the difference in the film thickness; a drain voltage Vds is impressed between the source (S) and the drain (D); a gate voltage Vg is impressed between the source (S) and the gate (G). Because, by this constitution, the shape of a depletion layer 3 is parallel to the interface between the active layer and the high-resistance substrate, the depletion layer 3 during a pinch-off comes into face contact with the interface. Accordingly, the pinch-off becomes sure and can suppress a leakage current.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides a method for pinch-off of the drain current by changing the thickness of the active layer in the gate portion of a field effect transistor from the source to the drain direction. The present invention relates to a field effect transistor configured such that the end of the under-gate depletion layer is parallel to the interface between an active layer and a high-resistance substrate, and a method for manufacturing the same.

[Prior art and problems] Figure 2 shows a conventional field effect transistor (referred to as FET).
The structure of is shown schematically.

An active layer 12 is formed on a high-resistance substrate 11 by, for example, molecular beam epitaxy (hereinafter referred to as MBE method), source S and drain D electrodes are provided at both ends of the active layer 12, and a p-type electrode is provided between these. A gate G is provided.

The figure shows an n-channel type.

As shown in the figure, a drain voltage Vds is applied between the source S and the drain D, and a gate voltage Vg is applied between the source S and the gate G.

In such a configuration, the active layer 12 and the high resistance substrate 11
Under normal operating conditions, during pinch-off, the interface between There is no contact, and the leakage current at the interface increases,
Good pinch-off is difficult. In particular, with the recent trend toward shorter gates, suppression of leakage current is desired.

[Structure of the Invention] The present invention was made for the purpose of improving the pinch-off performance in the above-mentioned FET, and the thickness of the uniformly doped active layer changes from the source to the drain in the active layer between the source and drain. FE with gate structure like
T and its manufacturing method.

FIG. 1 shows an embodiment of the invention. As shown, GaA
A uniformly doped active layer 2 is formed on a semi-insulating substrate 1 such as s by, for example, MBE, but the thickness of the active layer 2 varies from ds to da from the source side to the drain side. This diagram schematically shows a case in which the thickness is increased. Note that ion implantation can also be used instead of MBE.

As shown in the figure, a gate electrode (G) is provided on the surface of the active layer 2 which is inclined due to the difference in film thickness between the source S and the drain D, and a drain voltage V is applied between the source S and the drain D. , and a gate voltage Vg is applied between the source S and the gate G.

According to such a configuration, the shape of the depletion layer 3 is parallel to the interface between the active layer and the high-resistance substrate, so that the depletion layer 13 and the interface come into surface contact at the time of pinch-off.

Therefore, pinch-off becomes reliable, and leakage current can be suppressed.

Here, we will explain why leakage current can be suppressed by gradually increasing the thickness of the active layer from the source side to the drain side as described above.

The thickness W of the depletion layer formed under the gate is, however, g: gate voltage φB: Njotsky barrier height Eo: energy at the bottom of the conduction band E,: Fermi energy q: violet charge weight no: carrier concentration, where vg is the gate voltage Below, if W is constant in the gate length direction (X direction), W does not depend on X as long as φ□+n0 is constant.

However, in addition to the gate voltage Vg, the drain voltage Va
The FET is operated with t normally applied. In that case, v8 actually changes in the X direction, with vg(x=O)=vgs being low on the source side and Vg(x=1)=Vgd being high on the drain side.

Assuming linear approximation, Vg (X) = vgs + v'd□/1・×・・・・・・
・(2) Vt (x=,,l') =Vgd=Vgs+
V'as > Vgs where V'ds: Expressed as the potential difference between both ends of the gate. Due to this distribution, the depletion layer width W also has a distribution in the X direction.

However, ε3: dielectric constant of the semiconductor Therefore, the thickness W of the depletion layer under the gate changes from W6 to Wd.

Therefore, in the present invention, the active layer thickness under the gate is set to w6 and W6.
The interface between the active layer and the high-resistance substrate is made parallel to the edge of the depletion layer.

[Example] Si was deposited on a 2″φ semi-insulating GaAs substrate by the MBE method.
Doped uniform active layer, thickness 0.2j1m −, no
=1.0×1017 was grown.

The source and drain ohmic electrodes are AuGeN1 alloy electrodes, and the Schottky gate is Au/P with a length of 1 μm.
It is made of t/Ti.

When FET operation is performed with this, Vgs=t, o(
V).

V gd = 1.5 (V ), and the depletion layer thickness is W
8 → 1570 people IIdsaki 1790 people It is calculated.

On the other hand, the active layer formed in the same manner as above was subjected to focused ion etching that reached the O level (the surface of the active layer) linearly from a depth calculated to be about 200 people from the source side to the drain side. After that, a gate electrode was formed and an FET was manufactured.

The actual value of this FET is Vth" 1.54V.

On the other hand, for a FET with a conventional structure, vth=-1, 60V tear, ■d++=toμA or less,
The way in which ds decreases is small, and it is thought that the depletion layer contacts at a point during pinch-off, causing leakage.

[Effects of the Invention] In the present invention, the thickness of the active layer is changed to reflect the potential distribution of the gate in the source-drain direction, so that the active layer-high resistance interface and the edge of the depletion layer are parallel to each other. As a result, during pinch-off, the depletion layer can be brought into contact with the high-resistance substrate side at all points along its length, directly under the gate.
Since the pinch-off characteristics of the FET are improved, the frequency characteristics are improved, and higher frequency operation can be performed with the same material.

[Brief explanation of the drawing]

FIG. 1 schematically shows an embodiment of the present invention. FIG. 2 schematically shows a conventional FET. DESCRIPTION OF SYMBOLS 1... Semi-insulating substrate, 2... Active layer, 8... Depletion layer. Dice! Agony 2

Claims (2)

[Claims] (1) A field effect transistor characterized in that the active layer between the source and the drain has a gate structure in which the thickness of the uniformly doped active layer changes from the source to the drain. (2) A method for manufacturing a field effect transistor, characterized in that the thickness of the uniformly doped active layer in the gate portion is varied from the source to the drain direction by focused ion etching.