JPH01196171A - Bipolar transistor - Google Patents

Abstract

PURPOSE:To make operating speed of a transistor high by a method wherein a base-emitter junction is formed to be flat and a base-collector junction is formed in such a way that the base width is expanded toward an outer base region in order to quickly charge and discharge an excess charge used to form a base pushing region. CONSTITUTION:For example, an Si substrate 11, an N<+> type collector buried layer 12, an n-type collector 13, a P-type base 14 and an N-type emitter 15 are laminated in this order. A P<+> type outer base region 16 is formed at the side part of the collector 13 and the base 14 so as to surround a collector-base junction part. A base-emitter junction is made flat; a base-collector junction is formed in such a way that it is flat directly under the base-emitter junction and that it is inclined with reference to the base-emitter junction so that the base width can be expanded toward the outer base region 16 at the peripheral part. By this setup, the charging and discharging time, especially the discharging time, of an excess charge in a base pushing region is shortened; a switching characteristic of a transistor can be improved sharply.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to bipolar transistors constituting integrated circuits, and particularly to bipolar transistors with high speed and low power consumption performance.

(Prior Art) In recent years, various structures and manufacturing methods for bipolar transistors constituting integrated circuits have been proposed, and among these, technologies considered to be relevant to the present application will be described below.

First of all, in the Japanese Patent Publication No. 1O-81862, Figure 7 (
As shown in a), the emitter region 71. A planar self-aligned bipolar transistor structure is described in which the base region 72 and collector region 73 are self-aligned. The characteristics of this structure are: 1. The emitter-base junction is very small in size and essentially flat.

■ The base-collector junction is basically planar and has approximately the same area as the emitter-base junction.

■ A highly conductive polysilicon region 74 surrounds the vertical emitter, base and collector regions. A first and a second insulating material 75,76 respectively emitter region 7
1 and collector region 73 from a polysilicon region 74, which serves as a lateral contact to the active base and a metal base contact.

Announced at the Solid State Devices Conference in 1980, 19
In 1981 (Japl, orAppl, Phys, vol.
, 20,5uppl.

20-1. 'F published in pp. 149-153)
lat Emitter Transistor wit
In the paper entitled "Self-Aligned Ba5e" by Fujita et al., as shown in FIG. 7(b), (2) the emitter-base junction is basically flat.

(2) The impurity concentration that gives the conductivity type of the external base is high up to a position extremely close to the emitter region 7], and the base resistance is small.

It is stated that.

Also, in 1981 (International 5
olid-3tate Circuits Conrer
“Selr-AIigned” announced at
Transistor wNh 5idevall
In the article by Nakamura et al. entitled "Ba5e Electrode", as shown in FIG.

(2) having a polycrystalline silicon region 74 overlying the insulator 76 and providing electrical contact to the base region 72;

(2) Between the polycrystalline silicon region 74 and the base region 72, there is an external base region that partially soaks into the collector region 73.

(2) The external base region and the emitter region 71 are in contact with each other at the sides.

It is stated that.

Here, the basic idea of bipolar transistor structure with high speed and low power consumption performance is to realize a shallow vertical junction structure and a small horizontal geometry. It goes without saying that the three types of transistor structures described above were proposed based on this idea. Conventionally, the operating speed of bipolar transistors has been based on a model that is governed by the one-dimensional charge transit time in the vertical direction, and the three types of transistor structures mentioned above are exactly what realize this one-dimensional structure. I can say that there is.

However, in recent years, computer simulations have shown that the operating speed of bipolar transistors with large amplitude signals is not limited to the vertical direction of the base extrusion region formed in the collector region, but also the two-dimensional direction including the horizontal direction. The inventors revealed that charging and discharging are dominant (IEICE Technical Report, SDM
87-99. pII).

81-88>. For this reason, even in the conventional structure described above, it cannot be said that sufficient speed-up has been achieved.

(Problems to be Solved by the Invention) As described above, in conventional bipolar transistors, the charging and discharging speed of the base extrusion region is not sufficient during large amplitude signal operation, and it is difficult to sufficiently increase the transistor operating speed. It was difficult.

The present invention has been made in consideration of the above circumstances, and its purpose is to speed up the charging and discharging of excess charges forming the base extrusion region during large amplitude signal operation, thereby increasing the transistor operating speed. The object of the present invention is to provide a bipolar transistor that can be used in a wide range of applications.

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to improve the emitter-base junction as well as the base-collector junction, thereby improving the base extrusion area.
The goal is to sufficiently increase the dimensional charging and discharging speed.

That is, in the present invention, a collector region of a first conductivity type, a base region of a second conductivity type, and an emitter region of a first conductivity type are laminated in the above order on a semiconductor substrate, and a part of the base region and collector region is stacked on the side. In a bipolar transistor having an external base region of a second conductivity type surrounding the base region and providing an ohmic junction in the base region and a pn junction in the collector region, the base-emitter junction is formed flat and the base-collector junction is formed flat. is formed to be inclined with respect to the base-emitter junction so that the base width increases toward the external base region.

(Function) According to the present invention, since the electrical resistance decreases from the internal base region to the external base region, the excess charge in the base extrusion region can be reduced even though the base width is widened in the region around the intrinsic transistor. Charging and discharging become faster, making it possible to significantly improve switching speed. In addition, since the emitter-base junction is flat, the emitter region does not directly contact the external base region with a high impurity concentration, increasing the withstand voltage and further preventing the base extrusion region from expanding in the horizontal direction. . Moreover, since the resistance of the internal/external base coupling portion, which is important for high-speed operation, is low, high-speed performance can be achieved even if the impurity concentration of the internal base region is low. Therefore, charging and discharging of excess charge in the base extrusion region, which greatly affects the operating speed of the bipolar transistor, becomes faster, and the switching speed can be significantly improved.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a sectional view showing a schematic configuration of a bipolar transistor according to an embodiment of the present invention. In the figure, 11 is an 81 substrate, 12 is an N+ type collector buried layer, 13 is an n-type collector, 14 is a P-type base, and 15 is an N-type emitter, which are stacked in the above order. A P+ type external base region 16 is provided on the side of the collector 13 and the base 4 so as to surround the collector-base junction.

A first insulator 17 is embedded under the external base region 16 so as to surround the side portions of the collector 13 . A second insulator 18 is formed over the external base 16 and surrounding the base-emitter junction.

Note that the base-collector junction is flat just below the base-emitter junction, and at the periphery, the base width or external base region 1
It is formed to widen toward 6. Also, 21,
Reference numerals 22 and 23 indicate electrodes, 21 is an emitter electrode, 22 is a base electrode, and 23 is a collector electrode.

FIG. 2 is a diagram schematically showing the impurity distribution on the right side of the central portion (A-A') of the transistor, including the external base region and the insulating region.

Further, FIG. 3 schematically depicts the impurity distribution in the depth direction of the external base region 16 and the charge distribution in the depth direction at the center of the transistor in the desired base extrusion state. - The dotted line shows the distribution of the base P-type impurity concentration along the line A-A' in FIG. The solid line shows the distribution of the P-type impurity concentration in the external base region 16 along the line BB' in FIG.

As can be seen from Figure 3, in order to speed up the charging and discharging of excess charge in the base extrusion region, which is very important in ultra-high-speed bipolar transistors, unlike conventional methods, the external base region is extended to a deep region located next to the base extrusion region. 16 impurity concentration is increased.

Moreover, by widening the width of the internal base region toward the external base region, the resistance of the internal/external base coupling portion is lowered. In addition, in order to maintain the pressure resistance between the emitter and the base and to prevent the base extrusion region from expanding in the horizontal direction, the base-emitter junction is made flat as shown in FIG. The change is made steep, and the external base region 16 is placed as close to the center as possible in terms of pressure resistance. Furthermore, in order to reduce the capacitance of the external base-collector junction, an insulator 17 is provided which is in contact with a portion of the external base region 16 directly below and surrounds a portion of the side of the collector.

Next, a method of manufacturing the bipolar transistor having the structure of the above embodiment will be described.

First, as shown in FIG. 4(a), N-type impurities are introduced at a high concentration into a limited region of a P-type wheel crystal silicon wafer 11 to form an N+-type collector buried layer 12. As impurities, arsenic, antimony, etc. can be used.

Next, as shown in FIG. 4(b), the collector buried layer 1 is
An N-type epitaxial layer 13 having a thickness of approximately 1 μm is formed on the substrate 2.

Subsequently, the surface of the N-type epitaxial layer 13 is oxidized to form 5
00 silicon oxide film 31 is formed.

Furthermore, silicon nitride film 32. A silicon oxide film 33 and a silicon nitride film 34 are deposited by chemical vapor deposition (CVD). Thereafter, as shown in FIG. 4(C), using the resist as a mask, anisotropic reactive ion etching (
6 films 34, 33 and 32, 31 are etched by RIE), and then the N type epitaxial layer 13 and the N+
A part of the collector buried layer is etched to form a mesa region 35.
form.

Next, as shown in FIG. 4(d), the surfaces of the mesa region 35 and the N+ type collector buried layer 12 exposed by RIE were oxidized to form a silicon oxide film of 100%.
A silicon oxide film 36 of 4,000 layers is formed using the CVD method. Subsequently, a flattening resist 37 is applied.

Next, as shown in FIG. 4(e), a part of the resist 37 and a region located on the mesa region 35 of the silicon oxide film 36 are etched by RIE to form a silicon nitride film 34.
expose the surface of Thereafter, as shown in FIG. 4(1), the silicon oxide film 36 located between the mesa region 35 and the resist 37 is etched by RLE, and the resist 37 is etched.
7 is removed, leaving a part of the silicon oxide film 36.

Next, as shown in FIG. 4(g), the surface of the exposed mesa region is thinly oxidized to form a silicon oxide film 38.

Subsequently, a silicon nitride film 39 is deposited using the CVD method. Next, as shown in FIG. 4(h), anisotropic RI
Etching 39 is performed using E to leave sidewalls 40 of silicon nitride film on the sides of mesa region 35. Thereafter, as shown in FIG. 4(i), a silicon oxide film 41 is grown by selective oxidation using the sidewalls of the silicon nitride film 40 as a mask so that the lower side of the mesa shape is thinner than the upper side.

Next, as shown in FIG. 4(j), after removing the silicon nitride film sidewall 40 and the silicon oxide film sidewall 38, a P-type polycrystalline silicon film 42 containing boron is deposited. Subsequently, as shown in FIG. 4(k), the silicon oxide film 31. Mesa type region 3 leaving silicon nitride film 32
The polycrystalline silicon film 42 of No. 5 is removed and planarized. Thereafter, as shown in FIG. 4(1), using the silicon nitride film 32 as a mask, the exposed surface of the polycrystalline silicon film 42 is oxidized to form a silicon oxide film 43. At this time, boron is diffused from the polycrystalline silicon film 42 to the sidewalls of the mesa region 35, forming an external base region 16.

Next, as shown in FIG. 4(m), a silicon nitride film 32 is formed.
．． After partially etching the surfaces of silicon oxide film 31 and silicon oxide film 43, amorphous silicon containing arsenic is deposited, and boron is implanted by ion implantation to form base region 14.

Subsequently, boron is electrically activated by annealing to obtain a P-type electrical connection with the external base region 16, and at the same time, the amorphous silicon is made into a single crystal to form the emitter 15. At this time, the periphery of the emitter-base junction is surrounded by a silicon oxide film 43. Subsequently, the monocrystalline silicon is removed except for the emitter 15 portion. After this, after opening the base and collector electrode forming regions,
By forming each electrode with A and Q, the first
A bipolar transistor having the structure shown in the figure is completed.

Next, it will be explained using the results of a two-dimensional device simulation that the switching characteristics of the transistor are improved by using the structure of the above embodiment.

Figure 5(a) shows a conventional transistor structure (internal base impurity peak concentration 2x10I8c10l8), Figure 5(b) shows a conventional transistor structure with flattened emitter-base junction and base-collector junction, and Figure 5(C) shows a conventional transistor structure with flattened emitter-base junction and base-collector junction. A transistor structure according to the invention in which the emitter-base junction is flat and the slope of the base-collector junction begins in the intrinsic region (
Internal base impurity peak concentration 2 x 10 “cm”
) is shown. In high-speed bipolar transistor circuits,
The simulation was performed using values close to the voltage range used.

The collector electrode potential was fixed at 0 [V], the emitter electrode potential was fixed at -1.9 [V], and the base electrode potential was changed from -1.0 [V] to -1.4 [V] by 4 [ps] in the OFF characteristic. ]
to change linearly. Figure 6 shows the change in collector current over time. 1 from the steady state 90% value of 0 [ps]
Comparing the OFF characteristics in terms of the time it takes to decrease to 0%,
In conventional structure A, 26[ps], emitter-base junction,
In structure B, where both the base and collector junctions are flat, 2
6 [ps], and the OFF characteristics are rather deteriorated.

On the other hand, in Invention C, a significant improvement was achieved at 17 [ps] despite the low peak concentration of internal base impurities.

As described above, according to this embodiment, the external base is brought as close as possible to the intrinsic L transistor region, and the impurity concentration is increased even to the region located next to the base extrusion region. It becomes possible to charge/discharge and share excess charge by shortening the discharge time.
It becomes possible to significantly improve transistor switching characteristics. Furthermore, by sloping the base-collector junction, the resistance of the joint between the internal base and the external base is lowered, so high speed performance can be achieved even if the impurity concentration in the internal base region is low.

In addition, the base-emitter junction is flattened, the concentration change in the horizontal direction of the external base region is made steep, and the external base region is moved as close to the center as possible, so that the withstand voltage between the emitter and the base is maintained, and the base extrusion Horizontal expansion of the area can be prevented. Furthermore, since an insulator is provided that surrounds a portion of the side of the collector, it is possible to reduce the external base-collector junction capacitance.

Note that the present invention is not limited to the embodiments described above. For example, although polycrystalline silicon is used for the external base lead-out region, epitaxially grown SOI
(Silicon On In5ulator) is expected to further improve the characteristics due to the reduction in base resistance and base current. In addition, in the embodiment, NPN
Although the description has been made regarding a transistor, it goes without saying that a PNP l-transistor can also be implemented in the same manner. Further, the insulating film provided under the external base region is provided to reduce the external base-collector junction capacitance, and may be removed if this junction capacitance does not pose a problem.

In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, the base-emitter junction is formed flat, and the base-collector junction is formed so that the base width □ widens toward the external base region. Therefore, charging and discharging of excess charge forming the base extrusion region can be sufficiently accelerated, and the transistor operating speed can be significantly increased.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a schematic structure of a bipolar transistor according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line A-A in FIG.
'Schematic diagram showing the distribution of impurity concentration on the right side of the line, 3rd
The figure is a schematic diagram showing the impurity concentration in the depth direction of the external base region and the charge distribution in the depth direction at the center of the transistor in the desired base extrusion state, and FIG. 4 is a cross-sectional view showing the manufacturing process of the example transistor. Fig. 5 is for explaining two-dimensional simulation of conventional transistors and example transistors, and is a diagram schematically showing the cross-sectional structure of each transistor, Fig. 6 is a characteristic diagram showing the OFF characteristics of the collector current, and Fig. 7 1 is a cross-sectional view showing the main part configuration of a conventional bipolar transistor. 11... Si substrate, 12... N+ type collector buried layer, 13... N type collector, 14... P type base,
15... N type emitter, 16... P+ type external base region, 17... first insulating film, 18... second insulating film, 21.22.23... electrode, 31, 33, 36° 38. 41. 43... Silicon oxide film, 32, 34° 39... Silicon nitride film, 35... Mesa type region, 3
7...Resist, 42...Polycrystalline silicon film. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) A collector region of a first conductivity type, a base region of a second conductivity type, and an emitter region of a first conductivity type are laminated in the above order on a semiconductor substrate, and a part of the base region and collector region is stacked on a side part. In a bipolar transistor with an external base region of the second conductivity type, which is surrounded by A bipolar transistor characterized by a slope relative to the base-emitter junction so as to widen toward the external base region. (2) a portion of the base-collector junction is flat;
The point at which the base-collector junction begins to slope is the point at which the base-collector junction begins to slope.
Claim 1 characterized in that it is inside the emitter junction end.
Bipolar transistor as described.