WO2023273320A1

WO2023273320A1 - Zener diode and manufacturing method therefor

Info

Publication number: WO2023273320A1
Application number: PCT/CN2022/073069
Authority: WO
Inventors: 金华俊; 宋亮; 史一凡
Original assignee: 无锡华润上华科技有限公司
Priority date: 2021-06-30
Filing date: 2022-01-21
Publication date: 2023-01-05
Also published as: CN115548129A

Abstract

A zener diode and manufacturing method therefor. The method comprises: forming an electric field barrier layer (102) on a substrate (101); forming a pattern mask on the substrate (101), the pattern mask having a first window (106) that exposes part of the electric field barrier layer; removing the electric field barrier layer (102) in the first window (106); forming a first conductive-type doped region (107) and a second conductive-type doped region (108) in the substrate (101); forming a sidewall structure (110) on a sidewall of the first window (106) to limit the first window (106) to a second window (111); and performing first conductive-type ion implantation on the basis of the second window (111) to form, in a self-aligned manner, a first conductive-type connection region (112) between the first conductive-type doped region (107) and the second conductive-type doped region (108), wherein the doping concentration of the first conductive-type connection region (112) is greater than that of the first conductive-type doped region (107).

Description

Zener diode and method of making the same

Cross References to Related Applications

This application claims the priority of the Chinese patent application with the application number 2021107375198 and the title of the invention "Zener diode and its manufacturing method" filed with the China Patent Office on June 30, 2021, the entire contents of which are incorporated by reference in this application .

technical field

The invention belongs to the field of semiconductor device design and manufacture, and in particular relates to a Zener diode and a manufacturing method thereof.

Background technique

The statements herein merely provide background information related to the present application and do not necessarily constitute prior art.

Under normal circumstances, there is only a small current in the reverse biased PN junction. This leakage current remains constant until the reverse voltage exceeds a certain value. After this value, the PN junction suddenly starts to conduct large currents. This sudden and significant reverse conduction is reverse breakdown and can cause damage to the device if no external measures are taken to limit the current. Reverse breakdown usually sets the maximum operating voltage of a solid-state device.

One mechanism leading to reverse breakdown is the avalanche multiple phenomenon. On reverse biasing the PN junction, the depletion region widens with increasing bias, but not enough to prevent electric field strengthening. A strong electric field accelerates some carriers through the depletion region at very high speed. When these carriers collide with atoms in the crystal, they knock loose valence electrons and create additional carriers. Because the carriers can generate thousands of extra external carriers by impact, just like snowballs create an avalanche, this process is called avalanche multiple phenomenon.

Another mechanism for reverse breakdown is tunneling. Tunneling is a quantum-mechanical process based on the principle that particles can move a small distance in any obstacle. If the depletion region is thin enough, carriers can jump through it by tunneling. The tunneling current is mainly determined by the width of the depletion region and the voltage difference across the PN junction. Reverse breakdown caused by tunneling is called Zener breakdown.

The reverse breakdown voltage of the PN junction mainly depends on the width of the depletion region. The wider the depletion region, the higher the required breakdown voltage. As mentioned earlier, the lighter the doping, the wider the depletion region and the higher the breakdown voltage. When the breakdown voltage is less than 5 volts, the depletion region is too thin, mainly Zener breakdown. When the breakdown voltage is higher than 5 volts, it is mainly avalanche breakdown. PN diodes designed for the reverse conducting state are called Zener diodes or avalanche diodes depending on the dominant operating mechanism. Zener diodes have a breakdown voltage of less than 5 volts, while avalanche diodes have a breakdown voltage of greater than 5 volts.

In fact, the breakdown voltage of the PN junction is not only related to its doping characteristics, but also related to its geometry. As an example, for diodes with N+ doped regions/P-type doped regions, in order to reduce the breakdown voltage, the implantation dose of the P-type doped regions is usually increased overall, which will lead to an increase in the concentration of the arcuate junction of the PN junction , its electric field increases sharply, which leads to increased leakage and cannot effectively reduce its breakdown voltage.

Contents of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a Zener diode and its manufacturing method, which is used to solve the problem that the breakdown voltage of the Zener diode structure in the prior art is relatively high. If the concentration is reduced by increasing the The breakdown voltage of the diode will cause the electric field of the arc surface junction to increase, which will lead to the problem of increased leakage and cannot effectively reduce its breakdown voltage.

In order to achieve the above object and other related objects, the present invention provides a method for manufacturing a zener diode. The method includes the steps of: providing a substrate, forming an electric field blocking layer on the substrate; forming a graphic mask, the graphic mask has a first window exposing part of the electric field blocking layer; etching and removing the electric field blocking layer in the first window to expose the substrate; passing through the first window Forming a doped region of the first conductivity type and a doped region of the second conductivity type located in the doped region of the first conductivity type in the substrate; forming a sidewall structure on the sidewall of the first window, so as to Confining the first window to a second window; implanting ions of the first conductivity type into the substrate based on the second window, so that the doped region of the first conductivity type is doped with the second conductivity type The impurity regions are self-aligned to form a connection region of the first conductivity type, wherein the doping concentration of the connection region of the first conductivity type is greater than the doping concentration of the doped region of the first conductivity type.

The present invention also provides a Zener diode, comprising: a substrate; a doped region of the first conductivity type located in the substrate; a doped region of the second conductivity type located in the doped region of the first conductivity type; The first conductivity type connection region is located in the first conductivity type doped region, below the second conductivity type doped region, and directly contacts the bottom of the second conductivity type doped region, the first conductivity type doped region The doping concentration of the conductive type connection region is greater than that of the first conductive type doped region; and the electric field blocking layer is located on the substrate and covers both sides of the first conductive type doped region.

The present invention also provides another Zener diode, which includes: a substrate; an electric field blocking layer located on the substrate; a graphic mask located on the substrate and the electric field blocking layer, The pattern mask and the electric field blocking layer have a first window exposing the substrate; the doped region of the first conductivity type is located in the substrate exposed by the first window and extends to the electric field blocking layer the doped region of the second conductivity type, located in the doped region of the first conductivity type; a sidewall structure, located on the sidewall of the pattern mask, to limit the first window to a second window; The connection region of the first conductivity type is located in the substrate where the second window is exposed, and is located between the doped region of the first conductivity type and the doped region of the second conductivity type, wherein the first conductivity type The doping concentration of the type connection region is greater than the doping concentration of the first conductivity type doping region.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present application will be apparent from the description, drawings and claims.

Description of drawings

FIGS. 1 to 8 show the structural schematic diagrams of each step of the method for manufacturing a Zener diode according to an embodiment of the present invention, wherein FIG. 8 shows a schematic structural diagram of the Zener diode according to an embodiment of the present invention.

Component designation description

101 Substrate

102 Electric field blocking layer

103 Silica layer

104 Silicon nitride layer

105 photoresist layer

106 first window

107 The first conductivity type doped region

108 Second conductivity type doped region

109 dielectric layer

110 side wall structure

111 Second window

112 The first conductivity type connection area

detailed description

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

For example, when describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual production.

For the convenience of description, spatial relation terms such as "below", "below", "below", "below", "above", "on" etc. may be used herein to describe an element or element shown in the drawings. The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, structures described as having a first feature "on top of" a second feature may include embodiments where the first and second features are formed in direct contact, as well as additional features formed between the first and second features. Embodiments between the second feature such that the first and second features may not be in direct contact.

It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

The present application provides a Zener diode, comprising:

Substrate;

a doped region of the first conductivity type located in the substrate;

a second conductivity type doped region located in the first conductivity type doped region;

The first conductivity type connection region is located in the first conductivity type doped region, below the second conductivity type doped region, and directly contacts the bottom of the second conductivity type doped region, the first conductivity type doped region The doping concentration of the connection region of conductivity type is greater than the doping concentration of the doping region of the first conductivity type; and

The electric field blocking layer is located on the substrate and covers both sides of the doped region of the first conductivity type.

In the aforementioned Zener diode, the connection region of the first conductivity type is added at the PN junction interface formed by the doped region of the first conductivity type and the doped region of the second conductivity type, and the doping concentration of the connection region of the first conductivity type is greater than the The doping concentration of the doping region of the first conductivity type can effectively avoid the sharp increase of the arc junction electric field of the PN junction, so that by locally increasing the concentration of the planar junction region of the PN junction, the breakdown voltage can be effectively reduced and a better performance can be obtained. breakdown characteristics.

In one of the embodiments, the lateral width of the connection region of the first conductivity type is smaller than the lateral width of the doped region of the second conductivity type.

In one embodiment, the lateral width of the connection region of the first conductivity type is between 0.5 and 0.8 times the width of the doped region of the second conductivity type.

Further, as shown in FIGS. 1 to 8 , this embodiment provides a method for manufacturing a Zener diode.

As shown in FIG. 1 , firstly, step 1) is performed, a substrate 101 is provided, and an electric field blocking layer 102 is formed on the substrate 101 .

As an example, the substrate 101 may be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (silicon on insulator) or GOI (germanium on insulator) and the like. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other Epitaxial structure, such as SGOI (silicon germanium on insulator), etc. In this embodiment, the substrate 101 is a Si substrate.

The electric field blocking layer 102 is used to reduce the surface electric field of the substrate 101, prevent the subsequent breakdown of the second conductivity type doped region 108 from occurring on the surface of the substrate 101, and ensure that the device has low leakage. In this embodiment, the electric field blocking layer 102 may include a polysilicon layer and an insulating layer, the insulating layer is located between the polysilicon layer and the surface of the substrate 101, and may be formed by a vapor phase epitaxy process and a photolithography-etching process. The shape of the electric field blocking layer 102 may be circular, rectangular or the like.

As shown in FIGS. 2-3 , step 2) is then performed to form a pattern mask on the substrate 101 , and the pattern mask has a first window 106 exposing part of the electric field blocking layer 102 .

In this embodiment, forming a pattern mask on the substrate 101 includes:

As shown in FIG. 2 , step 2-1) is performed first, and a silicon dioxide layer 103 and a silicon nitride layer 104 are sequentially deposited on the substrate 101 .

For example, a silicon dioxide layer 103 and a silicon nitride layer 104 may be sequentially deposited on the substrate 101 by using plasma enhanced chemical vapor deposition (PECVD).

As shown in FIG. 2 , step 2-2) is then performed to form a photoresist layer 105 on the substrate 101 , and form a photoetching window in the photoresist by a photolithography process.

For example, a photoresist layer 105 may be formed on the substrate 101 by a spin coating process, then the photoresist layer 105 is baked, and a photoresist window is formed in the photoresist by a photolithography process. .

As shown in Figure 2, then carry out step 2-3), etch the silicon nitride layer 104 and the silicon dioxide layer 103 through the photolithography window, so that the silicon nitride layer 104 and the silicon dioxide layer In step 103, a first window 106 exposing part of the electric field blocking layer 102 is formed.

For example, the silicon nitride layer 104 and the silicon dioxide layer 103 may be sequentially etched by a plasma etching process to form the exposed portion of the electric field blocking layer in the silicon nitride layer 104 and the silicon dioxide layer 103. 102 of the first window 106 .

As shown in FIG. 3 , step 2-4) is finally performed to remove the photoresist layer 105 to form the pattern mask.

For example, the photoresist layer 105 may be removed by an ashing process or/and a wet cleaning process to form the pattern mask.

As shown in FIG. 4 , step 3) is then performed to etch and remove the electric field blocking layer 102 in the first window 106 to expose the substrate 101 .

For example, the electric field blocking layer 102 in the first window 106 may be etched and removed by using a plasma etching process, and the etching process stops at the surface of the substrate 101 .

As shown in FIG. 5 , proceed to step 4) to form a first conductivity type doped region 107 and a first conductivity type doped region 107 in the substrate 101 through the first window 106. Two conductivity type doped regions 108 .

Specifically, forming the first conductivity type doped region 107 in the substrate 101 through the first window 106 and the second conductivity type doped region 108 located in the first conductivity type doped region 107 includes the following step:

Step 4-1), implanting ions of the first conductivity type into the substrate 101 through the first window 106 and performing a first annealing, so that the P-type ions diffuse a first width in the lateral direction and diffuse in the vertical direction In the first depth, the P-type ions may be, for example, boron or the like.

Step 4-2), performing N-type ion implantation in the substrate 101 through the first window 106 and performing a second annealing, so that the N-type ions diffuse a second width in the lateral direction and a second width in the vertical direction. Depth, the N-type ions can be phosphorus and the like.

In the above step 4-1) and step 4-2), the first width is greater than the second width by controlling parameters such as implantation doses of the P-type ions and N-type ions, annealing temperature and annealing time , the first depth is greater than the second depth.

As an example, the doping concentration of the doped region 107 of the first conductivity type is 1E15 cm ⁻³ to 1E17 cm ⁻³ , and the doping concentration of the doped region 108 of the second conductivity type is 1E19 cm ⁻³ to 1E20 cm ⁻³ . In this embodiment, the doping concentration of the doped region 107 of the first conductivity type is 1E16 cm ⁻³ , and the doping concentration of the doped region 108 of the second conductivity type is ^5E19 cm ₋₃ .

As shown in FIGS. 6-7 , step 5) is then performed to form a sidewall structure 110 on the sidewall of the first window 106 to limit the first window 106 to a second window 111 .

Specifically, forming the side wall structure 110 on the side wall of the first window 106 includes the steps of:

As shown in FIG. 6 , step 5-1) is performed first, and a dielectric layer 109 is formed on the surface of the pattern mask and the bottom and sidewall of the first window 106 through a deposition process.

For example, the dielectric layer 109 can be formed by using plasma enhanced chemical vapor deposition (PECVD) equal to the surface of the pattern mask and the bottom and sidewalls of the first window 106. In this embodiment, the dielectric layer 109 The material is silicon dioxide.

As shown in Figure 7, then carry out step 5-2), remove the dielectric layer 109 on the surface of the pattern mask and the bottom of the first window 106 by an etch-back process, due to the etching rates of the dielectric layer 109 at different positions There is a difference, when the surface of the graphic mask and the dielectric layer 109 at the bottom of the first window 106 are all removed, the dielectric layer 109 on the sidewall of the first window 106 will be partially retained to form the sidewall structure 110. In this step, the fabrication of the sidewall structure 110 can be completed without additional fabrication of a mask, which can effectively reduce the process cost.

In this embodiment, the width of the side wall structure 110 can be set to be between 0.1 and 0.25 times the width of the first window 106 , so that the width of the second window 111 is equal to the width of the first window 106 Between 0.5 and 0.8 times the width.

As shown in FIG. 8 , step 6) is finally carried out, performing ion implantation of the first conductivity type into the substrate 101 based on the second window 111, so that the first conductivity type doped region 107 and the second The first conductivity type connection region 112 is self-aligned between the conductivity type doped regions 108, and the first conductivity type connection region 112 is connected to the first conductivity type doping region 107 and the second conductivity type doping region 108 are closely adjacent to each other, wherein the doping concentration of the first conductivity type connection region 112 is greater than the doping concentration of the first conductivity type doping region 107, and the first conductivity type connection region 112 can effectively improve The arc junction electric field of the PN junction formed by the doped region 107 of the first conductivity type and the doped region 108 of the second conductivity type.

As an example, the doping concentration of the connection region 112 of the first conductivity type is 1E18cm ⁻³ to 1E19cm ⁻³ , for example, the doping concentration of the connection region 112 of the first conductivity type is 5E18cm ⁻³ .

In this embodiment, since the width of the second window 111 is smaller than the width of the first window 106 , the lateral width of the first conductivity type connection region 112 is smaller than the lateral width of the second conductivity type doped region 108 width. In this embodiment, the lateral width of the first conductive type connection region 112 is between 0.5˜0.8 times of the lateral width of the second conductive type doped region 108 .

In this embodiment, the first conductivity type is P-type conductivity, and the second conductivity type is N-type conductivity. Of course, in other embodiments, the first conductivity type can also be N-type conductivity, and the The second conductivity type can also be P-type conductivity, which is not limited to the examples listed here.

In the present invention, the first conductivity type connection region 112 is added at the PN junction interface between the first conductivity type doped region 107 and the second conductivity type doped region 108, and the lateral width of the first conductivity type connection region 112 is smaller than that of the second conductivity type. The lateral width of the doped region 108, and the doping concentration of the first conductivity type connection region 112 is greater than the doping concentration of the first conductivity type doped region 107, which can effectively avoid the sharp increase of the arc junction electric field of the PN junction, By locally increasing the concentration of the planar junction region of the PN junction, the breakdown voltage can be effectively reduced and better breakdown characteristics can be obtained.

In the present invention, the sidewall structure 110 is manufactured by using the deposition process and the etching-back process, and the sidewall structure 110 is used as the injection barrier layer of the first conductivity type connection region 112, so that the first conductivity type connection region 112 can be realized without using a photolithography process. The self-aligned injection can effectively reduce the cost of the manufacturing process on the one hand, and improve the stability of the manufacturing process on the other hand.

As shown in FIG. 8 , this embodiment also provides a Zener diode, which includes a substrate 101, an electric field blocking layer 102, a pattern mask, a first conductivity type doped region 107, a second conductivity type doped region The impurity region 108 , the sidewall structure 110 and the first conductivity type connection region 112 .

The substrate 101 may be a semiconductor substrate, for example, a Si substrate, a Ge substrate, a SiGe substrate, SOI (silicon on insulator) or GOI (germanium on insulator) and the like. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other Epitaxial structure, such as SGOI (silicon germanium on insulator), etc. In this embodiment, the substrate 101 is a Si substrate.

The electric field blocking layer 102 is located on the substrate 101 . The electric field blocking layer 102 is used to reduce the surface electric field of the substrate 101, prevent the subsequent breakdown of the second conductivity type doped region 108 from occurring on the surface of the substrate 101, and ensure that the device has low leakage. In this embodiment, the electric field blocking layer 102 may include a polysilicon layer and an insulating layer, the insulating layer is located between the polysilicon layer and the surface of the substrate 101, and may be formed by a vapor phase epitaxy process and a photolithography-etching process. The shape of the electric field blocking layer 102 may be circular, rectangular or the like.

The pattern mask is located on the substrate 101 and the electric field blocking layer 102 , and the pattern mask and the electric field blocking layer 102 have a first window 106 exposing the substrate 101 .

In this implementation, the pattern mask includes a silicon dioxide layer 103 and a silicon nitride layer 104 stacked in sequence, and the pattern mask and the electric field blocking layer 102 have a first window 106 exposing the substrate 101 . The shape of the first window 106 may be circular or rectangular.

The doped region 107 of the first conductivity type is located in the substrate 101 exposed by the first window 106 and extends below the electric field blocking layer 102 . The doped region 108 of the second conductivity type is located in the doped region 107 of the first conductivity type. In this embodiment, the doped region 107 of the first conductivity type has a first width of lateral diffusion and a first depth of vertical diffusion, and the doped region of the second conductivity type 108 has a second width of lateral diffusion and a depth of vertical diffusion A second depth, the first width is greater than the second width, and the first depth is greater than the second depth. As an example, the doping concentration of the doped region 107 of the first conductivity type is 1E15 cm ⁻³ to 1E17 cm ⁻³ , and the doping concentration of the doped region of the second conductivity type 108 is 1E19 cm ⁻³ to 1E20 cm ⁻³ . In this embodiment, the doping concentration of the doped region 107 of the first conductivity type is 1E16 cm ⁻³ , and the doping concentration of the doped region 108 of the second conductivity type is 5E19 cm ⁻³ . In this embodiment, the doped region 108 of the second conductivity type is located on the upper surface layer of the doped region 107 of the first conductivity type.

The sidewall structure 110 is located on the sidewall of the pattern mask to limit the first window 106 to the second window 111. For example, the material of the sidewall structure 110 can be silicon dioxide, and the width of the sidewall structure 110 can be set to be between 0.1 and 0.25 times the width of the first window 106, so that the second window 111 The width is between 0.5-0.8 times the width of the first window 106 .

The connection region 112 of the first conductivity type is located in the substrate 101 exposed by the second window 111, and is located between the doped region 107 of the first conductivity type and the doped region 108 of the second conductivity type, so The connection region 112 of the first conductivity type is closely adjacent to the doped region 107 of the first conductivity type and the doped region 108 of the second conductivity type, wherein the doping of the connection region 112 of the first conductivity type Concentration greater than the doping concentration of the first conductivity type doped region 107, the first conductivity type connection region 112 can effectively improve the first conductivity type doped region 107 and the second conductivity type doped region 108 The arc junction electric field of the formed PN junction. As an example, the doping concentration of the connection region 112 of the first conductivity type is 1E18cm ⁻³ to 1E19cm ⁻³ , for example, the doping concentration of the connection region 112 of the first conductivity type is 5E18cm ⁻³ .

As mentioned above, the Zener diode and its manufacturing method of the present invention have the following beneficial effects:

In the present invention, the connection region of the first conductivity type is added at the PN junction interface formed by the doped region of the first conductivity type and the doped region of the second conductivity type, and the lateral width of the connection region of the first conductivity type is smaller than that of the doped region of the second conductivity type. The lateral width, and the doping concentration of the first conductivity type connection region is greater than the doping concentration of the first conductivity type doping region, which can effectively avoid the sharp increase of the arc junction electric field of the PN junction, thereby locally increasing the PN junction The concentration of the planar junction region can effectively reduce the breakdown voltage and obtain better breakdown characteristics.

The present invention utilizes a deposition process and an etching-back process to fabricate a side wall structure, and uses the side wall structure as an injection barrier layer for the connection area of the first conductivity type, so that the self-alignment of the connection area of the first conductivity type can be realized without using a photolithography process Infusion, on the one hand, can effectively reduce the cost of the manufacturing process, and on the other hand, can improve the stability of the manufacturing process.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

A method of making a zener diode, comprising:

providing a substrate on which an electric field blocking layer is formed;

forming a pattern mask on the substrate, the pattern mask having a first window exposing a portion of the electric field blocking layer;

Etching and removing the electric field blocking layer in the first window to expose the substrate;

forming a doped region of a first conductivity type and a doped region of a second conductivity type located in the doped region of the first conductivity type in the substrate through the first window;

forming a sidewall structure on a sidewall of the first window to confine the first window to a second window; and

Implanting ions of the first conductivity type into the substrate based on the second window to self-align between the doped region of the first conductivity type and the doped region of the second conductivity type to form a first conductivity type A connection region, wherein the doping concentration of the connection region of the first conductivity type is greater than the doping concentration of the doping region of the first conductivity type.
The method according to claim 1, wherein forming a pattern mask on the substrate comprises:

sequentially depositing a silicon dioxide layer and a silicon nitride layer on the substrate;

forming a photoresist layer on the substrate, and forming a photolithographic window in the photoresist through a photolithography process;

etching the silicon nitride layer and silicon dioxide layer through the photolithographic window to form a first window in the silicon nitride layer and silicon dioxide layer exposing a portion of the electric field blocking layer; and

The photoresist layer is removed to form the pattern mask.
The method according to claim 1, wherein a doped region of the first conductivity type and a doped region of the second conductivity type located in the doped region of the first conductivity type are formed in the substrate through the first window. Doped regions include:

Implanting ions of a first conductivity type into the substrate through the first window and performing a first annealing, so that the ions of the first conductivity type diffuse to a first width in a lateral direction and to a first depth in a vertical direction; and

Implanting ions of the second conductivity type into the substrate through the first window and performing a second annealing, so that the ions of the second conductivity type diffuse to a second width in the lateral direction and diffuse to a second depth in the vertical direction; wherein, The first width is greater than the second width, and the first depth is greater than the second depth.
The method according to claim 1, wherein forming a side wall structure on the side wall of the first window comprises:

forming a dielectric layer on the bottom and sidewalls of the first window and the surface of the pattern mask by a deposition process; and

The surface of the pattern mask and the dielectric layer at the bottom of the first window are removed by an etching-back process, and the dielectric layer on the sidewall of the first window is partially retained to form the sidewall structure.
The method according to claim 1, characterized in that, the doping concentration of the doped region of the first conductivity type is 1E15cm -3 ~ 1E17cm -3 , and the doping concentration of the doped region of the second conductivity type is 1E19cm -3 to 1E20cm -3 , the doping concentration of the connection region of the first conductivity type is 1E18cm -3 to 1E19cm -3 .
The method according to claim 1, characterized in that the lateral width of the connection region of the first conductivity type is smaller than the lateral width of the doped region of the second conductivity type.
The method according to claim 6, characterized in that the lateral width of the connection region of the first conductivity type is between 0.5 and 0.8 times the width of the doped region of the second conductivity type.
A zener diode comprising:

Substrate;

an electric field blocking layer on the substrate;

a pattern mask located on the substrate and on the electric field blocking layer, the pattern mask and the electric field blocking layer having a first window exposing the substrate;

a doped region of the first conductivity type, located in the substrate where the first window is exposed, and extending below the electric field blocking layer;

a second conductivity type doped region located in the first conductivity type doped region;

a sidewall structure on a sidewall of the pattern mask to confine the first window to a second window; and

The connection region of the first conductivity type is located in the substrate where the second window is exposed, and is located between the doped region of the first conductivity type and the doped region of the second conductivity type, wherein the first conductivity type The doping concentration of the type connection region is greater than the doping concentration of the first conductivity type doping region.
The Zener diode according to claim 8, wherein the doped region of the first conductivity type has a first width of lateral diffusion and a first depth of vertical diffusion, and the doped region of the second conductivity type has a lateral diffusion A second width of diffusion and a second depth of longitudinal diffusion, the first width is greater than the second width, and the first depth is greater than the second depth.
The Zener diode according to claim 8, characterized in that, the doping concentration of the doped region of the first conductivity type is 1E15cm −3 to 1E17cm −3 , and the doping concentration of the doped region of the second conductivity type is is 1E19cm -3 to 1E20cm -3 , and the doping concentration of the connection region of the first conductivity type is 1E18cm -3 to 1E19cm -3 .
The Zener diode according to claim 8, characterized in that the lateral width of the connection region of the first conductivity type is smaller than the lateral width of the doped region of the second conductivity type.
The Zener diode according to claim 11, characterized in that the lateral width of the connection region of the first conductivity type is between 0.5 and 0.8 times the width of the doped region of the second conductivity type.
A zener diode comprising:

Substrate;

a doped region of the first conductivity type located in the substrate;

a second conductivity type doped region located in the first conductivity type doped region;

The first conductivity type connection region is located in the first conductivity type doped region, below the second conductivity type doped region, and directly contacts the bottom of the second conductivity type doped region, the first conductivity type doped region The doping concentration of the conductive type connection region is greater than the doping concentration of the first conductive type doped region; and

The electric field blocking layer is located on the substrate and covers both sides of the doped region of the first conductivity type.
The Zener diode according to claim 13, characterized in that the lateral width of the connection region of the first conductivity type is smaller than the lateral width of the doped region of the second conductivity type.
The Zener diode according to claim 13, characterized in that: the lateral width of the connecting region of the first conductivity type is between 0.5 and 0.8 times of the lateral width of the doped region of the second conductivity type.