JPH01194513A - Dynamic type frequency divider - Google Patents

Abstract

PURPOSE:To easily cause a dividable frequency to be variable and to decrease a dividable lower limit frequency by using variable capacity or fixed capacity. CONSTITUTION:By attaching variable capacity diodes DI1 and DI2 to the output of transfer gates 3 and 5 in a dynamic type divider 1 and causing the capacity to be variable, the holding time of a charge is changed and the dividable frequency is made variable. Since the joining capacity of the variable capacity diodes DI1 and DI2 is made variable by a voltage, a voltage for capacity variability is added from an external part. When fixed capacity C3 and C4 are provided instead of the variable capacity diodes DI1 and DI2, a lower limit operating frequency can be decreased. Thus, by incorporating the variable capacity or fixed capacity, the dividable frequency can be easily made variable from the external part of an integrated circuit or the dividable lower limit frequency can be decreased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a frequency divider, and particularly to a PLL for ultra-high frequencies.
The present invention relates to a frequency divider used in a (Phase Locked Loop) circuit or a counter circuit.

[Prior Art] Conventionally, this type of dynamic frequency divider has a configuration as shown in FIG. 3 and 5 and buffers 4 and 6. The logic levels of each point A, B, C, and D in FIG. 5 are as shown in Table 1 according to the input clock signals C and C (over par) (both have a phase difference of 180° from each other). In Table 1, the high level is "1" and the low level is "1".
0". As shown in Table 1, each point A, B, Both C and D are “1” and “0” once.
”, and outputs a 1/2 frequency divided output with respect to the input clock signal. The basic principle of this is that the charge is held according to the time constant T=CGRG by the gate capacitance CG of the inverter 2 and the sum RG of the transfer gate and the internal resistance of the inverter.

An example of such a circuit is given in the literature (M, ROCCHI
et, al,, rGaAs Digital
Dynamic Ic's for Appl
cation up to l0GH2JIE
EE Journal of 5olid 5a
te C1rcuits”, VOL 5C-15,
No, 3. The report can be found in JUNE 1983).

Table 1 [Problems to be Solved by the Invention] The conventional dynamic frequency divider described above maintains the logic state using a time constant consisting of the product of the gate capacitance of the inverter and the internal resistance of the transfer gate and inverter. Therefore, the frequency that can be divided is limited to, for example, from 5 GHz to 9 GHz because the charge is held.

This divisible frequency depends on the gate width and gate length, which are the characteristics of the GaAS Schottky junction field effect transistor that constitutes the circuit, and it is easy to lower the divisible frequency or change the divisible frequency band. The disadvantage is that it cannot be done.

[Differences between the invention and the prior art] In contrast to the above-mentioned conventional dynamic frequency divider, the present invention uses a variable capacitor or a fixed capacitor to easily vary the frequency that can be divided or to change the lower limit frequency that can be divided. The difference is that it can lower the

[Means for Solving the Problems] In order to solve the above problems, the dynamic frequency divider of the present invention has a variable capacitor or a fixed capacitor in the same circuit. Accordingly, the gist of the invention is to provide a dynamic frequency divider in which each stage includes an inverter, a transfer gate connected in series with the inverter and gated by a clock signal, and a buffer holding the output of the transfer gate. Each of the above stages further has a capacity.

[Large dust row] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention. In the figure, 1 is a dynamic frequency divider, 2 is an inverter, 3 is a transfer gate (1), 4 is a buffer (1), and 5
is the transfer gate (2), 6 is the buffer (2),
7 is the input end (1), 8 is the input end (2), 9 is the output end, 1
0 is a variable capacitance part, 1 is a capacitor, a variable voltage end, R1 is a high frequency blocking resistor (1), R2 is a high frequency blocking resistor (2), C1
is Pi, bus capacitor (1), C2 is bypass capacitor (2), Dll is variable capacitance diode (1), DI
2 is a variable capacitance diode (2), VC is a capacitance variable voltage, C is a human clock signal (1), and C (over par) is an input clock signal (2).

In this embodiment, variable capacitance diodes DII are connected to the outputs of transfer gates 3 and 5 in the dynamic frequency divider 1.
, DI2 are attached, and by changing the capacitance, the charge retention time is changed and the frequency that can be divided is changed. In order to vary the junction capacitance of the variable capacitance diode DI1°DI2 with voltage, a capacitance variable voltage is applied from the outside. High frequency blocking resistors R1 and R2 are installed to prevent the high frequency voltage in the dynamic frequency divider 1 from escaping towards the capacitance variable voltage VC.
and bypass capacitors CI and C2.

If the circuit of FIG. 1 is expressed as an equal number of circuits, it will be as shown in FIG. 4. By electronic computer circuit simulation, variable capacitance ff1cG1. FIG. 6 shows the results of calculating changes in the divisible frequency when changing CG2.

Dividable frequency is 5GH when CG1=CG2=OPF
z to 9GHz, whereas CGI=CG2=0.
From 2GHz to 6GHzS at 2PF CG1=CG2
It can be seen that when =0.6PF, the frequency changes from 0.9GHz to 4.0GHz.

Further, FIGS. 7(1) and 7(2) are computer simulation results showing that the divided waveform of low frequencies can be improved by inserting the capacitor CGI, 2. Figure 7 (1) is C
When GGI,2 is not present, FIG. 7(2) shows the case where CGGI,2 is set to 0.1PF. If no capacitor is included, the duty ratio will be a waveform far from 50%, but by adding a capacitor, the charge storage time, that is, the time constant, can be lengthened and the duty ratio can be made close to 50%. I know what I can do.

[Actual sales starvation] FIG. 2 is a circuit diagram of a second embodiment of the present invention.

The variable capacitance diode is omitted to one, and the basic operation is the same as the first embodiment. This embodiment has the advantage that the number of elements for frequency variation is 1/2 that of the first embodiment, and the layout space can be reduced.

[Dog Sweet Yu] FIG. 3 is a circuit diagram of a third embodiment of the present invention.

A fixed capacitor C3 and a fixed capacitor ff1c4 are provided in place of the variable capacitance diode of the first embodiment.

This embodiment aims at lowering the lower limit operating frequency and improving the divided waveform, and is useful as a subsequent stage when dynamic frequency dividers are connected in cascade in multiple stages.

[Effects of the Invention] As explained above, the present invention provides a dynamic frequency divider with built-in variable capacitance or fixed capacitance, thereby making it possible to easily vary the frequency that can be divided from outside the integrated circuit. This has the effect of lowering the possible lower limit frequency and improving the divided output waveform at lower frequency division frequencies.

[Brief explanation of the drawing]

1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, FIG. 3 is a circuit diagram of a third embodiment of the present invention, and FIG. 4 is a circuit diagram of a third embodiment of the present invention. 5 is a circuit diagram of a conventional dynamic frequency divider, and FIG. 6 is an electronic computer circuit simulation of the first embodiment in which the frequency range that can be divided is changed by variable capacitance. The graphs shown in Figure 7 (1) and (2) show the low frequency divided output waveform (500MHz
, 1/2 frequency division output) can be improved by a variable capacitor. 1...Dynamic frequency divider,...
...Inverter, 3...Transfer gate 1), 4.
......Buffer (1), 5...Transfer gate (2), 6.
...Buffer (2), 7...Input end (1), 8...Input end (2), 9...・Output end, 10...Variable capacitance part, 11...Capacitance variable voltage end, R1...High frequency line positive resistance (1), R2...
...High frequency blocking resistor (2), C1... Bypass capacitor (1), C2... Bypass capacitor (2), Dll... Variable capacitance diode (1), DI2......variable capacitance diode (
2), VC...Voltage for variable capacitance, C3...Middle surface constant capacitance (1), C4...Fixed capacitance (2), C... ...Input clock signal (1), C (over par)...High power clock signal (2). C3---One fixed customer t (1) C4--- One fixed @ flea (2) 3rd FXJ Figure 6 Cocoon Figure 7

Claims (1)

[Claims] Each stage includes an inverter, a transfer gate connected in series to the inverter and gated by a clock signal,
A dynamic frequency divider including a buffer for holding an output of a transfer gate, wherein each stage further includes a capacitor.