JP3273710B2 - Digital DLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital DLL circuit which has a delay chain and is used for phase adjustment such as clock skew countermeasures.

[0002]

2. Description of the Related Art Conventionally, this type of digital DLL (Del
The ay locked loop circuit performs phase matching using a delay chain such as an inverter chain as shown in FIG.

FIG. 9 shows a phase matching method.
As shown in (b), a required delay amount is automatically selected from delay amounts of a delay chain that change at a certain value, and the delay amount is held.

FIG. 10 is a diagram showing a semiconductor chip having a built-in DLL circuit using the above-mentioned delay chain, and FIG. 11 is a diagram showing the basic operation thereof.

[0005] As shown in FIG.
0 includes a DLL 101 having the above-mentioned delay chain, and its output is fed back to the DLL 101 as an in-chip clock CK2 via an internal circuit 102.

The DLL 101 of the semiconductor chip 100
When a phase difference occurs between the system clock CK1 and the on-chip clock CK2 as shown in FIG. 11, the rise of the on-chip clock CK2 is changed to the system clock CK1.
Is delayed by the delay chain until the next rise, and the phase is matched by holding the delay.

[0007]

However, in the delay chain of the conventional DLL circuit, the width of the delay change amount (step width) is constant as described above (FIG. 9).
(B)), the width of the change amount is the matching accuracy. However, there has been a problem that when conditions such as a process and a power supply voltage change, the alignment accuracy fluctuates.

That is, as shown in FIG. 12, even if the matching accuracy when the phases match in the normal state, the best state, and the worst state is 0.2 ns in the normal state,
If the best state is 0.5 times the normal state, it will be 0.1 ns, and if the worst state is 2.0 times the normal state, it will be 0.1 ns.
4 ns, alignment accuracy from 0.1 ns to 0.4 ns
Range.

In the DLL circuit, since the amount of change (alignment accuracy) is constant regardless of the level of the input frequency, even if the process changes to the worst state in which the process is slower, the accuracy of the alignment is improved. The amount of change was small. Therefore, when the input frequency is low, the required delay chain becomes large, and the area of the delay chain becomes large in proportion thereto.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a digital DLL circuit in which fluctuations in alignment accuracy are reduced in consideration of operating conditions in a best state and a worst state. It is to provide. Another object is to provide a digital DLL circuit which maintains high accuracy in a worst-case process without increasing the area of the delay chain.

[0011]

In order to achieve the above object, a feature of the present invention is that a delay chain having a variable delay amount is provided, and first and second delay chains are extracted with a predetermined delay amount extracted from the delay chain. In the digital DLL circuit for performing the phase adjustment with the clock, the delay chain has a variable width of the delay amount.

Preferably, the delay chain is formed by cascade-connecting a plurality of gate circuits, and capacitors having different capacities are respectively connected to respective output sides of the plurality of gate circuits at predetermined stages.

[0013]

According to the present invention having the above-described structure, since the variation width of the delay amount of the delay chain is made variable (for example, gradually widened), the process is changed between the best state and the worst state. Also, the change in alignment accuracy can be minimized. Further, high accuracy in the worst-state process can be maintained without increasing the area of the delay chain.

Further, the delay chain is constituted by cascade-connecting a plurality of gate circuits, and connecting capacitors having different capacities to respective output sides of predetermined stages of the plurality of gate circuits, respectively. The change width of the delay amount can be varied easily and accurately.

[0015]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a delay chain of a digital DLL circuit embodying the present invention. FIG. 2 is a block diagram showing the internal configuration of the DLL circuit having the delay chain of FIG.

In FIG. 1, the delay chain of the present embodiment is an inverter chain formed by cascade-connecting a plurality of inverters 1.
The delay amount is taken out for each of the inverters 1. In addition, capacitors 2 having different capacities are connected to the output terminal of the inverter 1 from which the amount of delay is taken out so that the variation width of the amount of delay is variable.

Referring to FIG. 2, the DLL circuit according to the present embodiment comprises:
A phase comparator 11 for comparing a phase difference between the system clock CK1 and the on-chip clock CK2, and a low-pass filter 12 for removing a high frequency region of the system clock CK1
And the phase comparator 11 and the low-pass filter 12
Up / Down the count number according to the output of
/ Down counter 13 and the delay chain 14 having the configuration shown in FIG.

Here, the delay chain 14 receives the input I
N is the system clock CK1 and the first stage inverter 1
, And a predetermined delay amount is selected based on the output of the Up / Down counter 13 and the clock CK in the chip is selected.
2 is provided.

FIG. 3 is a diagram showing two types of semiconductor chips 20A and 20B on which the DLL circuit of FIG. 2 is mounted.

In FIG. 1, a chip 20A is a chip having a best state (0.5 times the normal state) in which a process input frequency is fast, and a chip 20B is a worst state (normal state) in which a process frequency is slow. 2.0 times the time).

Each of the chips 20A and 20B includes a DLL circuit 21 having the configuration shown in FIG.
The output of L21 passes through the internal circuits 22A and 22B, and is output as DLL clocks CK2A and CK2B to the DLL.
The data is fed back to the circuit 21.

Next, the operation of this embodiment will be described.

When the chips 20A and 20B operate in the best state and the worst state, respectively, the intra-chip clocks CK2A and CK2B are generated by the delay chain 14 of the DLL circuit 21 as shown in FIG.
K1 is delayed until the next rise, and the phase finally matches. The matching accuracy at the time of matching is the same for the chip 20A and the chip 20B. As described above, in the case of the prior art, the result is as shown in FIG. 12, and the alignment accuracy is different for each chip.

A specific description of this point will be given while showing the relationship between the normal state and the best state or the worst state (FIGS. 5 and 6). In addition, input frequency: 50 MHz,
And skew: 4 ns as an example.

5 (a) and 5 (b), the phase adjustment in the normal state with an input frequency of 50 MHz and a skew of 4 ns is performed with respect to an input IN having a period of 20 ns (1/50 MHz) with a skew of 4 ns and a minimum of DLL circuit 21. Delay 2
Assuming ns, a phase difference of 6 ns occurs, and the delay amount to be generated by the delay chain 14 in the DLL circuit 21 is 14 ns. Assuming that the change amount of one stage of the delay chain 14 is 0.2 ns, this delay amount is generated by 14 ns ÷ 0.2 ns = 70 stages, and the alignment accuracy is 1% (0.2 ns / 20 ns). . The above is shown in FIG. Next, the best state will be described. Assuming that the fluctuation of the best state is (× 0.5), the phase difference is 3 ns and the required delay amount is 17 ns. However, since the change amount of the delay chain 14 is 0.1 ns, 17 ns ÷ 0.1 ns = 170 steps are required. The alignment accuracy is 0.5% (0.1 ns / 2
0 ns).

In the worst state, the variation is (× 0.
Assuming 5), the required delay amount is 8 ns,
8 ns ÷ 0.4 ns = 20 stages, and the alignment accuracy is 2% (0.4 ns / 20 ns).

The relationship between the normal state and the best state is first examined in the normal state, the best state, and the worst state.
Although there is only a difference of 3 ns between s and 17 ns, the number of stages for generating it is 70 in the normal state, whereas 170 is required in the best state, and the number of stages of the delay chain 14 is determined in the best state. .

Next, looking at the relationship between the normal state and the worst state, the required delay amount is 14 ns, whereas the required delay amount is 8 ns in the worst state, and the required number of stages is 8 ns ÷ 0.4 ns = 20.
It becomes a step. There is no problem with the number of stages, but the amount of change (alignment accuracy)
Is 0.2 ns in the normal state, but 0.4 ns in the worst state, and the alignment accuracy is determined in the worst state.

From the above, the alignment accuracy of the delay chain 14 is 0.4 ns in the worst state, and the required maximum delay amount is 170 steps × 0.2 ns from the best state.
= 34 ns. However, the alignment accuracy at the time of 34 ns is not required to be 0.2 ns.
0.5 = 0.8 ns is sufficient.

Therefore, when the process is best and fast, the point where the phases match is the delay chain 1
In contrast, when the process is in the worst state, the speed of the delay chain 14 becomes slow. Therefore, the point where the phases match is a point where the number of stages of the delay chain 14 is small.

Thus, in the present embodiment, the change amount of the delay chain 14 which is constant in the prior art is shifted to a point where the number of stages becomes larger as the process is faster, and the speed of the delay chain 14 at that time is reduced. Since the speed is increased, as shown in FIGS. 7A and 7B, it is possible to gradually increase the width as the number of stages increases. FIG. 7A shows the amount of change for each number of stages of the delay chain 14, and FIG. 7B shows the relationship between the amount of delay in a normal state and the amount of change for one stage.

If the input frequency is 50 MHz and the skew is 4
ns, the amount of change in the point at which the delay chain 14 locks in the process in the best state is 0.8 ns when converted to the normal state, and the amount of change in the point locked in the process in the worst state is When converted to a normal state, it can be set to 0.2 ns. Therefore, if the delay chain 14 is changed in the range of 0.2 ns to 0.8 ns, the alignment accuracy can be kept constant even if the process changes. Therefore, the change amount of the delay chain 14 may be in a relationship inversely proportional to the total delay amount in the state of the normal process up to that point.

The relationship between the number of stages and the amount of delay of the delay chain of the present embodiment shown in FIG. 8 is different from that of the prior art shown in FIG. The nonlinear characteristics are obtained by changing the capacitance of each stage of the capacitor shown in FIG. Due to this non-linear characteristic, the delay amount of each gate circuit in the subsequent stage region increases, and the alignment accuracy when the process variation is in the best state (the state in which the delay chain operates at high speed as a whole) is deteriorated. The number of stages of the delay chain can be reduced. On the other hand, in the worst state (the state in which the delay chain operates at a low speed as a whole), the lock point shifts to the smaller number of stages, the delay amount of each gate chain decreases, and the worst state alignment accuracy Is improved. Thus, for example, the alignment accuracy can be set to a constant value in the standard state regardless of the variation in the manufacturing process. The relationship between the number of stages of the delay chain and the amount of delay of the present embodiment shown in FIG. 8 is based on the case where the matching accuracy for setting the constant is set to a standard value, and the change in the capacitance of the capacitor of each stage is controlled. By changing this nonlinear characteristic,
The alignment accuracy can be set to an arbitrary constant value. In addition, for example, when the standard value is adjusted to a constant value, the number of stages of the delay chain required when the process variation is the best can be reduced. The effect of reducing the area can also be obtained. Furthermore, by using the method of this embodiment, if the input frequency is different, the matching accuracy can be guaranteed in a certain range.

In this embodiment, the delay chain 1
4 is composed of the inverter 1, but the NAND gate and the NO
It may be constituted by an R gate or the like.

[0035]

As described above in detail, according to the present invention, a delay chain having a variable delay amount is provided.
In the digital DLL circuit for performing phase matching between the first and second clocks with a predetermined delay amount extracted from the delay chain, the delay chain has a variable width of the delay amount. Even if the process changes to the state, the change in the alignment accuracy can be minimized. Further, high accuracy in the worst-state process can be maintained without increasing the area of the delay chain.

Further, the delay chain is constituted by cascade-connecting a plurality of gate circuits, and by connecting capacitors having different capacities to respective output sides of predetermined stages of the plurality of gate circuits, respectively. It is possible to easily and accurately change the variation width of the delay amount.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a delay chain of a digital DLL circuit embodying the present invention.

FIG. 2 is a block diagram showing an internal configuration of a DLL circuit having the delay chain of FIG. 1;

FIG. 3 is a diagram showing two types of semiconductor chips on which the DLL circuit of FIG. 2 is mounted.

FIG. 4 is a time chart illustrating an operation of the DLL circuit according to the embodiment.

FIG. 5 is a diagram illustrating a relationship between a best state and a worst state with respect to a normal state.

FIG. 6 is a diagram illustrating a relationship between a best state and a worst state with respect to a normal state.

FIG. 7 is a diagram illustrating a relationship between a change amount of a delay chain and a delay amount.

FIG. 8 is a diagram showing the effect of the embodiment.

FIG. 9 is a diagram showing a conventional delay chain.

FIG. 10 is a diagram showing a semiconductor chip incorporating a DLL circuit using a delay chain.

FIG. 11 is a diagram showing a basic operation of a conventional DLL circuit.

FIG. 12 is an explanatory diagram of a variation in alignment accuracy in a conventional DLL circuit.

[Explanation of symbols]

 1 Inverter 2 Capacitor 14 Delay chain 21 DLL circuit CK1 System clock CK2 In-chip clock

Continuation of the front page (72) Inventor Hiroaki Suzuki 580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Corporation Semiconductor System Technology Center (56) References JP-A-4-117819 (JP, A) JP-A-63-42224 (JP, A) JP-A-4-363908 (JP, A) JP-A-8-97715 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03L 7 / 06-7/099

Claims (1)

(57) [Claims] 1. A digital DLL circuit comprising a delay chain having a variable delay amount and performing phase matching between a first clock and a second clock with a predetermined delay amount extracted from the delay chain. A plurality of gate circuits are cascaded to make the change width of the delay amount variable ,
Different outputs are provided at each output side for each predetermined stage of the plurality of gate circuits.
Capacitors having different capacities, and a plurality of cascade-connected capacitors constituting the delay chain.
Delay of each gate circuit from the first stage to the last stage of the gate circuit
So that the volume of the capacitor becomes relatively large gradually.
A digital DLL circuit characterized by different amounts .