JPH01191197A - Testing method for active matrix substrate of display panel - Google Patents

Testing method for active matrix substrate of display panel

Info

Publication number
JPH01191197A
JPH01191197A JP63016247A JP1624788A JPH01191197A JP H01191197 A JPH01191197 A JP H01191197A JP 63016247 A JP63016247 A JP 63016247A JP 1624788 A JP1624788 A JP 1624788A JP H01191197 A JPH01191197 A JP H01191197A
Authority
JP
Japan
Prior art keywords
test
active matrix
electrode
matrix substrate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63016247A
Other languages
Japanese (ja)
Inventor
Kyoichi Urabe
卜部 恭一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP63016247A priority Critical patent/JPH01191197A/en
Publication of JPH01191197A publication Critical patent/JPH01191197A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To shorten the testing time by executing the test in a state that a testing substrate is superposed on an active matrix substrate to be tested and each projecting electrode on a test electrode of the testing substrate side is brought to conductive contact with the corresponding picture element electrode of the active matrix substrate side. CONSTITUTION:On a testing substrate 50, a flexible projecting electrode 53 is provided on a position corresponding to each picture element electrode 10 on plural pieces of test electrodes 52, and when this testing substrate 50 is superposed on an active matrix substrate to be tested, the tip of this projecting electrode 53 is brought to conductive contact simultaneously with all the picture element electrodes 10 of the active matrix substrate 40. By using this testing substrate 50, it is unnecessary to move a probe one by one, and by switching electrically or electronically a scanning electrode 20 of the active matrix substrate 40 side and the test electrode 52 of the testing substrate 50 side, respectively, the test is advanced, while scanning successively all picture elements in the active matrix substrate 40, for instance, in both the vertical and the horizontal directions. In such a way, the test time can be shortened by omitting the time for moving the probe.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は液晶表示パネル等のアクティブマトリックス基
板、すなわち画素の表示用の画素電極と所定方向に並ぶ
画素電極に対して共通に設けられた走査電極と各画素電
極と走査電極との間に接続された表示駆動用の駆動素子
とを備えるアクティブマトリックス基板を、表示パネル
に組み立てる前の単独の状態で試験をする方法に関する
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an active matrix substrate such as a liquid crystal display panel, that is, a scanning electrode that is provided in common to pixel electrodes for pixel display and pixel electrodes arranged in a predetermined direction. The present invention relates to a method for testing an active matrix substrate, which includes electrodes and drive elements for display driving connected between each pixel electrode and a scanning electrode, in a standalone state before being assembled into a display panel.

(従来の技術〕 上述の液晶形等の表示パネルは、よく知られているよう
に当初は電卓や腕時計の文字板のような固定パターンの
画像を表示する比較的簡単な構造のものから実用化され
たが、テレビ用等のより複雑な可変画像を表示する用途
にも適用範囲が拡大されるにつれて、その面内に多数個
の画素を行列状に配列したマトリックス構造のものが開
発されて来た。このマトリックス方式の表示パネルにお
いてもその大画面化や高表示密度化が進んで面内に含ま
れる画素数が増加するにつれて、駆動回路を含めた表示
全体の構成を簡単化しかつ画質を鮮明に保つために、ト
ランジスタ、ダイオード1非線形素子などの表示駆動素
子をその面内に分布させて組み込むいわゆるアクティブ
マトリックス方式の表示パネルが有利になり、現在敵方
程度の画素を含む比較的小形のものから実用化が進んで
いる。この種の表示パネル用駆動素子は、表示パネルを
構成する1対の基板中の一方の基板側に組み込まれるが
、両基板間の10ミクロン程度以下のごく狭い間隙内に
納めてしまう要があるので薄膜構造のものがこれに用い
られ、この駆動素子がトランジスタやダイオードの場合
にはそれ用の半導体膜にはふつう非晶質シリコンや多結
晶シリコンの薄膜が用いられる0本発明は表示パネルの
かかる駆動素子を組み込んだ側のアクティブマトリック
ス基板に関する。第4図は駆動素子としてダイオードを
用いたこのアクティブマトリックス基板の一部を拡大し
て示すものである。
(Prior Art) As is well known, display panels such as the above-mentioned liquid crystal type were initially put into practical use from relatively simple structures that displayed fixed pattern images such as the dials of calculators and watches. However, as the scope of application expanded to include displaying more complex variable images such as those for televisions, matrix structures were developed in which many pixels were arranged in rows and columns within the plane. As the screen size and display density of this matrix display panel progresses, and as the number of pixels included in the screen increases, the overall display configuration, including the drive circuit, is simplified and the image quality becomes clearer. In order to maintain this level, so-called active matrix display panels have become advantageous, incorporating display driving elements such as transistors and diodes and nonlinear elements distributed within their plane. This type of drive element for display panels is incorporated into one of the pair of substrates that make up the display panel, but there is a very narrow gap of about 10 microns or less between the two substrates. Since it is necessary to fit the device inside the device, a thin film structure is used for this, and when this driving element is a transistor or diode, a thin film of amorphous silicon or polycrystalline silicon is usually used as the semiconductor film for it. The present invention relates to an active matrix substrate on the side of a display panel incorporating such a driving element. FIG. 4 shows an enlarged part of this active matrix substrate using a diode as a driving element.

第4図で2個だけが示された画素電極10は表示パネル
内の各画素の表示用であって、実際には図の左右、上下
両方向にそれぞれ数百ずつ並べてアクティブマトリック
ス基板面上に行列配置される。
The pixel electrodes 10, of which only two are shown in FIG. 4, are for displaying each pixel in the display panel, and in reality, several hundred pixel electrodes 10 are arranged in both the left and right and up and down directions in the figure, and are arranged in matrix on the active matrix substrate surface. Placed.

この配置の所定方向、この例では左右方向に並ぶ画素電
極10に対して走査電極20が設けられ、各画素電極に
与えるべき表示電圧がこの走査電極に乗せられる。駆動
素子30は画素電極ごとに設けられるが、この例のよう
にダイオードである場合には、正負両方向のダイオード
30p、30nが設けられ、両ダイオードは互いに逆並
列接続される。この例では正方向のダイオード30pは
図示のように走査電極20上に作り込まれて接続膜7を
介して画素電極10に接続され、負方向のダイオード3
0nは逆に画素電極10上に作り込まれて接続膜7を介
して走査電極20と接続される0表示パネルの図示しな
いもう一方の基板上には走査電極20と交叉する方向。
Scan electrodes 20 are provided for the pixel electrodes 10 arranged in a predetermined direction of this arrangement, in this example the left and right direction, and a display voltage to be applied to each pixel electrode is placed on this scan electrode. The drive element 30 is provided for each pixel electrode, and when it is a diode as in this example, diodes 30p and 30n in both positive and negative directions are provided, and both diodes are connected in antiparallel to each other. In this example, the positive direction diode 30p is formed on the scanning electrode 20 as shown in the figure and connected to the pixel electrode 10 via the connection film 7, and the negative direction diode 30p is formed on the scanning electrode 20 and connected to the pixel electrode 10 via the connection film 7.
On the other hand, 0n is formed on the pixel electrode 10 and connected to the scanning electrode 20 via the connection film 7. On the other substrate (not shown) of the display panel, the direction intersects with the scanning electrode 20.

この例では図の上下方向に細長な対向電極が画素電極1
0と同じ幅で走査電極20が延びる方向に並べて設けら
れる0表示パネルの表示に当たっては、走査電極を例え
ば垂直走査し対向電極を水平走査しながら、両電極間に
表示電圧を走査周期ごとに正負に切り換えて与えること
により表示パネルを交流駆動する。垂直、水平側走査に
より特定された画素では、ある走査周期内に走査電極2
0に正の表示電圧が掛かり、正方向のダイオード30p
が導通してこの表示電圧を走査電極20から画素電極1
0に伝え、次の走査周期には走査電極20に負の表示電
圧が掛かり、負方向のダイオード30nが導通してこの
表示電圧が画素電極に伝えられる。
In this example, the opposing electrode, which is elongated in the vertical direction of the figure, is the pixel electrode 1.
When displaying on the 0 display panel, which has the same width as the 0 display panel and is arranged in the direction in which the scanning electrodes 20 extend, the scanning electrode is vertically scanned, the counter electrode is horizontally scanned, and the display voltage is changed between the two electrodes to be positive or negative at each scanning period. The display panel is driven by alternating current. In a pixel specified by vertical and horizontal scanning, the scanning electrode 2
A positive display voltage is applied to 0, and the diode 30p in the positive direction
conducts and transfers this display voltage from the scan electrode 20 to the pixel electrode 1.
0, and in the next scan period, a negative display voltage is applied to the scan electrode 20, the negative direction diode 30n becomes conductive, and this display voltage is transmitted to the pixel electrode.

第5図はこのアクティブマトリックス基板の構造を第4
図のY−Y矢視断面で示すもので、絶縁基板1はふつう
透明なガラスで、まずその表面にITO(インジウム・
錫酸化物)等の透明導電膜2を被着した上で、それから
画素電極10と走査電極20とをバターニングする。駆
動素子としての走査電極20上のダイオード30pは、
クローム等の1対の遮光膜3.5によって狭まれた例え
ばpin構成の非晶質シリコンの半導体IP14からな
り、その 上に窒化シリコン等の絶縁膜が第4図かられ
かるように両ダイオード30p、30nを共通に覆うよ
うに設けられる。接続膜7はこの絶縁膜6の窓6aを介
してその一端がダイオード頂部の遮光膜5に導電接触し
、他端が画素電極10に導電接触するように設けられる
。このように構成されたアクティブマトリックス基板は
もう一方の基板と組み合わされて、前基板を周縁部で相
互に接着し、両基板間の隙間に液晶等の表示媒体を封入
することにより表示パネルとされる。
Figure 5 shows the structure of this active matrix substrate.
The insulating substrate 1 is usually made of transparent glass, and the surface of the insulating substrate 1 is first coated with ITO (indium).
After depositing a transparent conductive film 2 such as tin oxide), the pixel electrode 10 and the scanning electrode 20 are patterned. The diode 30p on the scanning electrode 20 as a driving element is
It consists of a semiconductor IP 14 made of amorphous silicon in a pin configuration, for example, which is sandwiched between a pair of light-shielding films 3.5 made of chrome, etc., and an insulating film made of silicon nitride or the like is placed on top of it, as shown in FIG. , 30n in common. The connection film 7 is provided so that one end thereof is in conductive contact with the light shielding film 5 on the top of the diode through the window 6a of the insulating film 6, and the other end is in conductive contact with the pixel electrode 10. The active matrix substrate configured in this way is combined with the other substrate, the front substrate is bonded to each other at the periphery, and a display medium such as liquid crystal is filled in the gap between both substrates to form a display panel. Ru.

しかし、1枚のアクティブマトリックス基板内には敵方
ないしは数十万の画素が組み込まれるので、この内に若
干の欠陥画素が発生することがある。この欠陥の主なも
のは短絡と断線であり、前者としては例えば絶縁膜6の
不良による接続膜7と下側遮光膜3との接触や導電膜2
のパターニング不良による画素電極10と走査電極20
の直接短絡などがあり、後者としては接続膜7の破断や
走査電極20メ断線などがある。ふつう短絡の方が重欠
陥とされるが、重欠陥を完全になくすことは困難である
ので、欠陥画素が所定数例えば10個以下のアクティブ
マトリックス基板は良品とされる。この欠陥の有無や欠
陥数はアクティブマトリックス基板を表示パネルに組み
立てた上で表示試験を行なえば簡単にわかるのであるが
、組み立て後にそのアクティブマトリックス基板が不良
品と判明しても、それと組み合わせたもう一方の基板と
ともに廃棄するしかなく、組み立てに要した作業や相手
基板がすべてむだになってしまう、このため、アクティ
ブマトリックス基板に、対してそれを表示パネルに組み
立てる前の単独の状態で試験が行なわれる。この試験に
当たって最も厄介なのは、各画素電極をどのようにして
試験回路に接続するかであって、この従来の試験の要領
を第6図を参照して説明する。
However, since hundreds of thousands of pixels are incorporated into one active matrix substrate, some defective pixels may occur among them. The main defects are short circuits and disconnections, and the former include, for example, contact between the connecting film 7 and the lower light-shielding film 3 due to a defect in the insulating film 6, and the conductive film 2.
Pixel electrode 10 and scanning electrode 20 due to poor patterning
The latter includes a rupture of the connecting film 7 and a disconnection of the scanning electrode 20. Generally, short circuits are considered to be more serious defects, but since it is difficult to completely eliminate serious defects, active matrix substrates with a predetermined number of defective pixels, for example 10 or less, are considered good products. The presence or absence of defects and the number of defects can be easily determined by assembling the active matrix substrate into a display panel and performing a display test, but even if the active matrix substrate is found to be defective after assembly, it is possible to determine The active matrix board has no choice but to be discarded together with the other board, and all the work required for assembly and the mating board are wasted.For this reason, active matrix boards are tested on their own before being assembled into a display panel. It will be done. The most difficult thing in this test is how to connect each pixel electrode to the test circuit, and the procedure for this conventional test will be explained with reference to FIG.

まず、図示のアクティブマトリックス基板4o上の走査
電極20を基板端部のその接続部20aにおいてすべて
共通接続した上で、試験電圧源71と電流測定器72と
からなる試験回路の一端に接続する。−各画素電極10
をこの試験回路の他端に接続するためには探針60を用
い、この探針60を左右、上下両方向P、Qに自動的に
順次移動させながら各画素電極10に接触させ、そのつ
ど測定器72によりそれに流れる電流の過大、過小によ
り各画素の短絡としかし、この従来の方法では探針ない
しぼプローブを−々画素電極に接触させながら試験をし
なければならないので、アクティブマトリックス基板に
含まれる画素数が多くなるに従ってプローブの移動に時
間が掛かって試験時が増大する問題がある0例えば画素
が200行、400列に配置されているとき、その全体
の画素数は8万個にもなるが、2000画素の試験に約
1時間を要するのでアクティブマトリックス基板内の全
画素の試験に40時間もの長時間を要することになって
しまう、従って経済的な点からはアクティブマトリック
ス基板内の1710以下の画素を抜取試験するしかない
ことになる。
First, all the scanning electrodes 20 on the illustrated active matrix substrate 4o are connected in common at their connecting portions 20a at the ends of the substrate, and then connected to one end of a test circuit consisting of a test voltage source 71 and a current measuring device 72. -Each pixel electrode 10
In order to connect the probe to the other end of this test circuit, a probe 60 is used, and the probe 60 is brought into contact with each pixel electrode 10 while automatically sequentially moving in both left and right and up and down directions P and Q, and measurements are taken each time. However, in this conventional method, the test must be carried out while the probe or grain probe is in contact with each pixel electrode, so that the current flowing through the active matrix substrate may not be included in the active matrix substrate. As the number of pixels increases, it takes more time to move the probe, which increases the testing time.For example, when pixels are arranged in 200 rows and 400 columns, the total number of pixels can be as high as 80,000. However, since it takes about 1 hour to test 2000 pixels, it will take as long as 40 hours to test all the pixels on the active matrix substrate.Therefore, from an economic point of view, 1710 pixels on the active matrix substrate The only option is to perform a sampling test on the following pixels.

また、この従来の試験方法ではプローブと画素1a極と
の導電接触の信転性に問題がある。プローブの各画素電
極からの離間と導電接触が高速で操り返えされるので、
接触抵抗に若干の変動が生じやすい、しかし、1枚のア
クティブマトリックス基板に対して欠陥画素数が例えば
10個以下か否かを判定しなければならないので、画素
が前述の8万個程度以上あるとき接触抵抗に0.01%
以上の確率で変動すると、試験に全く信頼が置けないこ
とになってしまう。
Furthermore, this conventional testing method has a problem in reliability of conductive contact between the probe and the pixel 1a pole. Since the separation and conductive contact of the probe from each pixel electrode is manipulated at high speed,
Contact resistance tends to fluctuate slightly, but since it is necessary to determine whether the number of defective pixels on one active matrix substrate is, for example, 10 or less, the number of pixels is about 80,000 or more as mentioned above. When contact resistance is 0.01%
If the probability fluctuates as above, the test will become completely unreliable.

本発明はかかる従来の試験方法のもつ難点を克服して、
アクティブマトリックス基板に含まれる画素数が多(で
もその全画素について試験を短時間内にすることができ
、かつ結果の信頼性を向上できるアクティブマトリック
ス基板の試験方法をこの目的は本発明によれば、走査電
極と交叉する方向に延びる細長な試験電極を走査電極の
延びる方向に沿って並べて設け、かつこの試験電極上の
各画素電極に対応する位置に先端が各画素電極に導電接
触可能な可撓性の突出電極を設けた試験用基板を用い、
この試験用基板を試験をすべきアクティブマトリックス
基板と重ね合わせて試験用基板側の試験電極上の各突出
電極をアクティブマトリックス基板側の対応する画素電
極にIX導電接触せてアクティブマトリックス基板側の
走査電極および試験用基板側の試験電極を走査しながら
両電極間に試験電圧を印加し、アクティブマトリックス
基板を各画素ごとに試験することにより達成される。
The present invention overcomes the difficulties of such conventional testing methods, and
The present invention aims to provide a method for testing active matrix substrates that can test all the pixels within a short time even though the number of pixels included in the active matrix substrate is large, and that can improve the reliability of the results. , elongated test electrodes extending in a direction that intersects the scan electrodes are arranged side by side along the direction in which the scan electrodes extend, and the tips of the test electrodes are placed in conductive contact with each pixel electrode at positions corresponding to each pixel electrode. Using a test board with flexible protruding electrodes,
This test substrate is overlapped with the active matrix substrate to be tested, and each protruding electrode on the test electrode on the test substrate side is brought into IX conductive contact with the corresponding pixel electrode on the active matrix substrate side, and the active matrix substrate side is scanned. This is achieved by applying a test voltage between the electrodes and the test electrode on the test substrate side while scanning the electrodes, and testing the active matrix substrate for each pixel.

〔作用〕[Effect]

本発明による試験方法に用いる試験用基板には、上記構
成にいうようにその複数個の試験?!電極上各画素電極
に対応する位置に従来のプローブのかわりとなる可撓性
の2例えば導電性ゴムからなる突出電極が設けられ、こ
の試験用基板を試験をすべきアクティブマトリックス基
板と重ね合わせたとき、この突出電極の先端がアクティ
ブマトリックス基板の全画素電極に一斉に導電接触され
る。
The test board used in the test method according to the present invention may be used for multiple tests as described in the above configuration. ! A flexible protruding electrode made of conductive rubber, for example, was provided in place of a conventional probe at a position corresponding to each pixel electrode on the electrode, and this test substrate was superimposed on the active matrix substrate to be tested. At this time, the tips of the protruding electrodes are brought into conductive contact with all the pixel electrodes of the active matrix substrate at the same time.

本発明は、この試験用基板を用いることによりプローブ
を一々移動させる要をなくし、アクティブマトリックス
基板側の走査電極と試験用基板側の試験電極とをそれぞ
れ電気的ないしは電子的に切り換えて、アクティブマト
リックス基板内の全画素を例えば垂直、水平両方向に順
次走査しながら試験を進めるようにすることにより、従
来のプローブを移動させるに要していた時間を一切省い
て試験時間を従来の1〜2桁短縮するのに成功したもの
である。また、突出電極とこれに対応する画素電極との
間の導電接触は、試験用基板をアクティブマトリックス
基板と重ね合わせた後は試験期間を通じてそのままの状
態で保たれ、従来のようにプローブが一々画素電極と接
離されるようなことがないので、本発明はこれを利用し
てこの導電接触の接触抵抗を不変に保ち試験結果の(を
転性を大幅に向上することに成功したものである。
By using this test board, the present invention eliminates the need to move the probes one by one, and electrically or electronically switches the scanning electrodes on the active matrix board side and the test electrodes on the test board side. By sequentially scanning all pixels on the board, for example in both the vertical and horizontal directions, the time required to move the conventional probe is completely eliminated, reducing the test time by 1 to 2 orders of magnitude compared to conventional methods. It was successfully shortened. Additionally, the conductive contact between the protruding electrode and its corresponding pixel electrode remains in place throughout the test period after the test substrate is stacked with the active matrix substrate, allowing the probe to contact each pixel one by one as in the past. Since there is no contact or separation with the electrode, the present invention utilizes this to maintain the contact resistance of this conductive contact unchanged, and has succeeded in significantly improving the conductivity of the test results.

〔実施例〕〔Example〕

以下、第1図から第3図を参照しながら本発明の実施例
を詳しく説明する。第1図は太線で示されたアクティブ
マトリックス基板40と細線で示された試験用基板50
とを重ね合わせた状態で示すとともに試験回路を合わせ
て例示するものである。
Embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 3. FIG. 1 shows an active matrix substrate 40 indicated by thick lines and a test substrate 50 indicated by thin lines.
The test circuit is shown in a superimposed state, and the test circuit is also illustrated.

第1図のアクティブマトリックス基板40上には、行列
状に配置された多数個の画素電極10と、この例では行
方向に並ぶ画素電極に対して共通に設けられた走査電極
20と、各画素電極と走査電極との間に接続された駆動
素子30とが示されており、図で小さな方形で示された
駆動素子30はこの例ではダイオード等の二端子素子で
ある。駆動素子が三端子素子の場合は走査電極が列方向
にも設けられるが、試験は行列両方向の走査電極の内の
一方を試験回路に接続し他方を所定電位に置いた状態で
行なえばよいので、その要領は駆動素子が二端子素子で
ある場合と大差はない。
On the active matrix substrate 40 in FIG. 1, there are a large number of pixel electrodes 10 arranged in rows and columns, a scanning electrode 20 provided in common to the pixel electrodes arranged in the row direction in this example, and a scanning electrode 20 for each pixel electrode. A driving element 30 is shown connected between the electrode and the scanning electrode, and the driving element 30, which is shown as a small square in the figure, is a two-terminal element such as a diode in this example. If the driving element is a three-terminal element, scanning electrodes are also provided in the column direction, but testing can be performed with one of the scanning electrodes in both row and column directions connected to the test circuit and the other set at a predetermined potential. , the procedure is not much different from the case where the drive element is a two-terminal element.

アクティブマトリックス基板40と重ね合わされている
試験用基板50には、アクティブマトリックス基板側の
走査電極20と直交する方向に細長な試験電極52が絶
縁基板上に走査電極の延びる方向に並べて設けられてお
り、さらに各試験電極52の上にはアクティブマトリッ
クス基板側の画素電極10にそれぞれ対応する位置に可
撓性の突出1tF153が図の上下方向に並べて設けら
れる。この様子は第2図の斜視図により明瞭に示されて
いる。この第2図ではアクティブマトリックス基板40
と試験用基板50が互いに離れた状態で示されており、
図では試験用基板50の下面の試験電極52上に並べて
設けられた突出電極53とアクティブマトリックス基板
40の上面の画素電極10との対応が図の縦方向の細い
矢印で示されている。さらに第2図のX−X矢視断面で
ある第3図にはアクティブマトリックス基板40と試験
用基板50とが重ね合わされた状態が示されている。
On the test substrate 50 superimposed on the active matrix substrate 40, test electrodes 52 which are elongated in a direction orthogonal to the scanning electrodes 20 on the active matrix substrate side are arranged on an insulating substrate in the direction in which the scanning electrodes extend. Furthermore, flexible protrusions 1tF153 are provided on each test electrode 52 at positions corresponding to the pixel electrodes 10 on the active matrix substrate side, arranged in the vertical direction in the figure. This situation is clearly shown in the perspective view of FIG. In this FIG. 2, an active matrix substrate 40
and the test board 50 are shown separated from each other,
In the figure, the correspondence between the protruding electrodes 53 arranged on the test electrodes 52 on the lower surface of the test substrate 50 and the pixel electrodes 10 on the upper surface of the active matrix substrate 40 is indicated by thin arrows in the vertical direction of the figure. Further, FIG. 3, which is a cross section taken along the line X--X in FIG. 2, shows a state in which the active matrix substrate 40 and the test substrate 50 are overlapped.

これら第2図および第3図の試験用基板50上の突出電
極53は導電性のシリコーンラバーの半球状の突起であ
って、例えば次のようにして作られる。
The protruding electrodes 53 on the test substrate 50 shown in FIGS. 2 and 3 are hemispherical protrusions made of conductive silicone rubber, and are made, for example, as follows.

まず試験用基板50用の絶縁基板51はアクティブマト
リックス基板40用と同じく例えばガラス基板であって
よ(、その上に試験電極52用にITOや金属の膜をそ
の全面にごく薄り0.1〜0.5ミクロンの厚みに被着
した上で第2図に示すような形状にパターニングする。
First, the insulating substrate 51 for the test substrate 50 is made of, for example, a glass substrate like the active matrix substrate 40 (on top of which a thin film of ITO or metal is coated on the entire surface with a thickness of 0.1 After depositing to a thickness of ~0.5 microns, it is patterned into the shape shown in FIG.

突出電極53用の導電性シリコーンラバーとしては例え
ば東芝シリコーン社製のT CM8401を用い、0,
1fi程度の厚みの薄い銅板にアクティブマトリックス
基板の画素電極の配列ピッチに対応する0、3鶴程度の
ピッチで0.15m前後の径をもつ孔を多数個明けた金
属マスクを用いて、ペースト状のシリコーンラバーをす
り込み法により試験電極52上に付着させ、その加熱酸
化時の一種のりフロー効果によって半球状の形状にした
上で、そのまま硬化させることにより第3図に示したよ
うな突出電極53とする。あるいは、マスクとして通常
のフォトレジストを用い、試験電極52を形成ずみの絶
縁基板51の全面にまずこのフォトレジストを30ミク
ロン以上の厚みに塗着した上で、そのバターニングによ
り試験電極52上に同様に0.3鶴程度のピッチで0.
25n程度の径の窓を抜く、突出電極用シリコーンラバ
ーとしては例えば上掲社製のT CM8403を用いて
同様にすり込み法で窓内にこのシリコーンラバーを充填
した後、加熱硬化させた上でフォトレジストをIAji
l除去することにより円柱状の導電性シリコーンラバー
の突出電極を得る。
As the conductive silicone rubber for the protruding electrode 53, for example, TCM8401 manufactured by Toshiba Silicone Co., Ltd. is used.
Using a metal mask with a large number of holes with a diameter of about 0.15 m at a pitch of about 0.3 cranes, which corresponds to the arrangement pitch of the pixel electrodes of the active matrix substrate, in a thin copper plate with a thickness of about 1 fi, paste-like The silicone rubber is adhered onto the test electrode 52 by a rubbing method, formed into a hemispherical shape by a type of glue flow effect during heating and oxidation, and then cured to form a protruding electrode as shown in Fig. 3. 53. Alternatively, using a normal photoresist as a mask, first apply this photoresist to a thickness of 30 microns or more over the entire surface of the insulating substrate 51 on which the test electrode 52 has been formed, and then pattern it onto the test electrode 52. Similarly, at a pitch of about 0.3 cranes, 0.
For example, TCM8403 manufactured by the above-mentioned company is used as the silicone rubber for the protruding electrode from which a window with a diameter of about 25 nm is cut out.After filling the inside of the window with this silicone rubber using the same rubbing method, it is heated and cured. IAji photoresist
By removing 1, a cylindrical protruding electrode of conductive silicone rubber is obtained.

このようにして形成された突出電極53はいずれも可撓
性をもち、若干の高さの差があっても試験用基板50を
アクティブマトリックス基板に向けて押圧したときに僅
かに変形して突出電極53と画素電極IOとの確実な導
電接触が得られる。第3図に示すように試験用基板50
とアクティブマトリックス基板40との間の周縁部には
適宜の高さをもつストツバ54を設け、図示のように突
出電極53の先端が画素電極10に僅かに接触した状態
から、さらに押圧化δだけ抑え込むことにより突出電極
53を変形させてその画素電極10との導電接触を確実
にすることができる。
All of the protruding electrodes 53 formed in this way have flexibility, and even if there is a slight difference in height, they deform slightly and protrude when the test substrate 50 is pressed toward the active matrix substrate. Reliable conductive contact between the electrode 53 and the pixel electrode IO can be obtained. As shown in FIG.
A stopper 54 having an appropriate height is provided at the peripheral edge between the active matrix substrate 40 and the active matrix substrate 40, and from the state where the tip of the protruding electrode 53 slightly contacts the pixel electrode 10 as shown in the figure, the pressure is further increased by δ. By pressing down, the protruding electrode 53 can be deformed and its conductive contact with the pixel electrode 10 can be ensured.

第1図に戻って、試験電圧Eを発生する試験電圧源71
はこの実施例ではその極性切り換え用の切換スイッチ7
1a−t−備える。測定器72は通常の高感度の電流測
定器であってよいが、測定電流が10−”〜10−1^
と微小電流でふつうのものでは100m5程度の測定時
間が掛かるので、測定速度のできるだけ早いものを用い
るのが望ましい0選択スイッチ73も電子式の動作速度
の早い多点のものを用い、その被選択端子を試験用基板
50の画素電極52の各接続部52aと接続する。この
選択スイッチ73の選択端子は試験電圧[71と測定器
72からなる試験回路の一端に接続される。この実施例
ではアクティブマトリックス基板40の走査電極30は
その接続部20aを介して多点の切換スイッチ74の各
切換端子に接続され、この切換スイッチ74の一方の各
被切換端子は共通接続された上で試験回路の他端に接続
される。切換スイッチ74の他方の被切換端子は選択ス
イッチ75の被選択端子にそ机ぞれ接続され、この選択
スイッチ75の選択端子は試験回路の他端に接続される
Returning to FIG. 1, the test voltage source 71 that generates the test voltage E
In this embodiment, there is a changeover switch 7 for changing the polarity.
1a-t-provide. The measuring device 72 may be a normal high-sensitivity current measuring device, but if the measured current is 10-" to 10-1^
Since it takes about 100m5 to measure with a normal microcurrent, it is desirable to use one with the fastest measurement speed possible.The 0 selection switch 73 should also be an electronic multi-point switch with fast operation speed. The terminals are connected to each connection portion 52a of the pixel electrode 52 of the test substrate 50. A selection terminal of this selection switch 73 is connected to one end of a test circuit consisting of a test voltage [71] and a measuring device 72. In this embodiment, the scanning electrode 30 of the active matrix substrate 40 is connected to each switching terminal of a multi-point changeover switch 74 via its connecting portion 20a, and each of the switched terminals on one side of the changeover switch 74 is commonly connected. connected to the other end of the test circuit at the top. The other terminal to be switched of the changeover switch 74 is connected to the terminal to be selected of a selection switch 75, and the selection terminal of this selection switch 75 is connected to the other end of the test circuit.

以上のように構成された試験回路を用いてアクティブマ
トリックス基板40を試験する手順例を以下に説明する
。この試験に当たっては図示しない計算機等の制御回路
から選択スイッチ73に行方向に並ぶ例えば640個の
画素を選択できるように10ビツトの水平選択指令sh
が、切換スイッチ74に対しては1ビツトの切換指令S
cが、もう一方の選択スイ、チア5に対しては列方向に
並ぶ例えば400個の画素を選択できるように9ビツト
の垂直選択指令Sνがそれぞれ発しられ、測定器72か
らの試験結果を表わす試験信号TSがこの制御回路に与
えられるものとする。
An example of a procedure for testing the active matrix substrate 40 using the test circuit configured as described above will be described below. In this test, a 10-bit horizontal selection command sh was sent from a control circuit such as a computer (not shown) to the selection switch 73 so that, for example, 640 pixels arranged in a row could be selected.
However, a 1-bit switching command S is sent to the changeover switch 74.
For the other selection switch, cheer 5, a 9-bit vertical selection command Sν is issued to select, for example, 400 pixels arranged in the column direction, and represents the test result from the measuring device 72. It is assumed that a test signal TS is applied to this control circuit.

アクティブマトリックス基板では短絡欠陥が重欠陥でも
ありかつその発生率がふつうは高いので、試験はまず短
絡欠陥数により不良品を排除するのを第一義とする。こ
のため試験電圧源71に付属の切換スイッチ’71aを
例えば図示の状態に固定して試験電圧Eの極性を一定に
保った状態で、切換指令Scにより切換スイッチ74を
図示の状態に置き、アクティブマトリックス基板40の
全走査電極20を共通接続状態にいれた上で、選択スイ
ッチ73に水平選択指令shを送って試験用基板50の
各試験電極52を走査しながら順次試験回路に接続する
。この際、ある試験電極52に対応するアクティブマト
リックス基板40上の図の上下方向に並ぶ画素に1個で
も短絡欠陥があれば、試験結果は短絡欠陥ありとなるが
、制御回路はその欠陥ありの試験電極番号を記憶しなが
ら欠陥ありになった試験電極の総数を加算して行き、こ
の総数が許容数である例えばIOを越えたとき直ちに試
験を停止し試験中のアクティブマトリックス基板を不良
とする。
In active matrix substrates, short-circuit defects are also serious defects and their incidence is usually high, so the primary purpose of testing is to eliminate defective products based on the number of short-circuit defects. For this purpose, the changeover switch '71a attached to the test voltage source 71 is fixed, for example, in the state shown in the figure, and the polarity of the test voltage E is kept constant, and the changeover switch 74 is set in the state shown in the figure by the switching command Sc, and the changeover switch 74 is set in the state shown in the figure. After all the scanning electrodes 20 of the matrix board 40 are brought into a common connection state, a horizontal selection command sh is sent to the selection switch 73 to sequentially connect each test electrode 52 of the test board 50 to the test circuit while scanning it. At this time, if there is even one short-circuit defect in the pixels arranged in the vertical direction in the figure on the active matrix substrate 40 corresponding to a certain test electrode 52, the test result will indicate that there is a short-circuit defect, but the control circuit will detect the presence of the defect. While memorizing the test electrode number, add up the total number of defective test electrodes, and when this total exceeds the allowable number (for example, IO), immediately stop the test and mark the active matrix board under test as defective. .

全部の試験電8i52に対する走査を終えて欠陥ありの
試験電極の総和が10以下の場合は、切換指令Scによ
り切換スイッチ74を図示とは逆の切換位置に置いた上
で、前に記憶した欠陥ありの試験電極番号に対応する水
平選択指令shを選択スイッチ73に送ってその試験電
極を選択した状態で、垂直選択指令Svを選択スイッチ
75に送って走査電極20を走査しながら順次試験回路
に接続しながら、その試験電極に対応する上下方向に並
ぶすべての画素について短絡の有無を試験する。同様の
試験を前に短絡ありとされたすべての試験電極について
行なった結果、短絡ありの画素の総和が10以下であっ
たときそのアクティブマトリックス基板を短絡欠陥につ
いて良品とするが、その総和が10を越えたときはその
時点で試験を停止してアクティブマトリックス基板を不
良品とする。
If the total number of defective test electrodes is 10 or less after scanning all the test electrodes 8i52, place the changeover switch 74 in the opposite position to that shown in the figure according to the changeover command Sc, and then set the previously memorized defect. A horizontal selection command sh corresponding to the test electrode number of YES is sent to the selection switch 73 to select that test electrode, and a vertical selection command Sv is sent to the selection switch 75 to sequentially select the test circuit while scanning the scanning electrode 20. While connected, all pixels aligned in the vertical direction corresponding to the test electrode are tested for the presence or absence of short circuits. As a result of conducting a similar test on all the test electrodes that had previously been found to have short circuits, if the sum of the pixels with short circuits was 10 or less, the active matrix substrate was considered to be good for short circuit defects. When the value exceeds this value, the test is stopped at that point and the active matrix board is considered a defective product.

断線欠陥についての試験では、短絡欠陥試験のような試
験電極についての一括試験が不可能なので、切換スイッ
チ74を図示とは逆の切換位置に置いた状態で選択スイ
ッチ73.75に順次水平選択指令shと垂直選択指令
Sνをそれぞれ送って、アクティブマトリックス基板4
0内の画素を左右、上下両方向に走査しながら、全画素
の1個ずつについて断線の有無を試験する。この場合に
も断線欠陥ありの画素の総和が許容数を越えたとき試験
を停止して試験中のアクティブマトリックス基板を不良
品とする。また、駆動素子30がダイオードである場合
は正負両方向の試験電圧Eについて断線の有無を試験す
る要があるので、上の断線欠陥試験を切換スイッチ71
aを切換えて2度行なうなり、アクティブマトリックス
基板40内の各画素が走査されたときに、切換スイッチ
71aをそのつど切り換えながら正負両方向の試験電圧
について各画素の断線の有無を試験するなりする。この
ように断線欠陥試験はアクティブマトリックス基板内の
全画素についてする要があり、従ってその試験時間も短
絡欠陥試験のIO倍程度掛かることになるので、測定器
72に高速動作のものを用いるのがとくに望ましい、し
かし、幸い測定器としては電流が0か否かがわかればよ
いので、それ専用のものにして動作速度を高めることが
できる。この場合には断線欠陥試験か短絡欠陥試験かで
測定器72を切換えて使用できるようにするのが有利で
ある。このように断線欠陥の検出に専用の高速測定器を
用いれば、断線欠陥試験を短絡欠陥試験の3〜5倍程度
の時間内にすませることができる。
In the test for disconnection defects, it is impossible to perform a batch test on the test electrodes as in the short-circuit defect test, so with the changeover switch 74 placed in the opposite switching position from that shown, horizontal selection commands are sequentially sent to the selection switches 73 and 75. sh and vertical selection command Sν, respectively, to the active matrix substrate 4.
While scanning the pixels within 0 in both the left and right and up and down directions, each pixel is tested for the presence or absence of a disconnection. In this case as well, when the total number of pixels with disconnection defects exceeds the allowable number, the test is stopped and the active matrix board under test is determined to be a defective product. In addition, if the drive element 30 is a diode, it is necessary to test for the presence or absence of a disconnection with respect to the test voltage E in both the positive and negative directions.
When each pixel in the active matrix substrate 40 is scanned, the changeover switch 71a is switched each time to test each pixel for the presence or absence of disconnection with respect to test voltages in both positive and negative directions. In this way, it is necessary to perform the open circuit defect test on all pixels in the active matrix board, and the test time therefore takes about IO times that of the short circuit defect test. Therefore, it is recommended to use a high-speed measuring instrument 72. This is especially desirable, but fortunately the measuring device only needs to know whether the current is 0 or not, so it can be made exclusively for that purpose and the operating speed can be increased. In this case, it is advantageous to be able to use the measuring device 72 by switching between the open circuit defect test and the short circuit defect test. If a dedicated high-speed measuring instrument is used to detect disconnection defects in this way, the disconnection defect test can be completed in about 3 to 5 times the time of the short circuit defect test.

〔発明の効果〕〔Effect of the invention〕

以上述べたとおり本発明においては、各画素の表示用の
画素電極と所定方向に並ぶ画素電極に対して共通に設け
られた走査電極と各画素電極と走査電極との間に接続さ
れた表示駆動用の駆動素子とを備えるアクティブマトリ
ックス基板の試験に際して、走査電極と交叉する方向に
延びる細長な試験電極を走査電極の延びる方向に沿って
並べて設け、かつこの試験電極上の各画素電極に対応す
る位置に先端が各画素電極に導電接触可能な可撓性の突
出電極を設けた試験用基板を用い、この試験用基板を試
験をすべきアクティブマトリックス基板と重ね合わせて
試験用基板側の試験電極上の各突出電極をアクティブマ
トリックス基板側の対応する画素電極に導電接触させて
おいて、アクティブマトリックス基板側の走査電極およ
び試験用基板側の試験電極を走査しながら両電極間に試
験電圧を印加してアクティブマトリックス基板を各画素
ごとに試験するようにしたので、従来のように探針ない
しはプローブを一々アクティブマトリックス基板の画素
電極に接離しながら機械的に移動させることなく、アク
ティブマトリックス基板側の走査電極と試験用基板側の
試験電極とを純電気的ないし電子的に適宜走査しながら
、アクティブマトリックス基板内の画素ごとに試験する
ことができるので、試験時間を従来よりも大幅に短縮す
ることができる0例えばアクティブマトリックス基板内
に8万個の画素があるとき従来方法では全画素の試験に
40時間を要したが、本発明方法では短絡欠陥試験を1
0分以内、断線欠陥試験を1時間以内に完了することが
できる。また、試験用基板の突出電極はアクティブマト
リックス基板の画素電極との導電接触を両基板を重ね合
わせた当初の状態のままで全試験を完了できるので、従
来のプローブを接離する方法よりも接触抵抗が格段に安
定した状態で試験を行なって試験結果の信顛性を向上す
ることができる。
As described above, in the present invention, a pixel electrode for display of each pixel, a scan electrode provided in common for the pixel electrodes arranged in a predetermined direction, and a display drive connected between each pixel electrode and the scan electrode. When testing an active matrix substrate equipped with a drive element for use with a drive element, elongated test electrodes extending in a direction intersecting with the scan electrodes are arranged in parallel along the direction in which the scan electrodes extend, and each pixel electrode on the test electrodes corresponds to the test electrode. Using a test board with flexible protruding electrodes whose tips can make conductive contact with each pixel electrode, place this test board on the active matrix board to be tested, and insert the test electrodes on the test board side. Each of the protruding electrodes on the top is brought into conductive contact with the corresponding pixel electrode on the active matrix substrate side, and a test voltage is applied between both electrodes while scanning the scan electrode on the active matrix substrate side and the test electrode on the test substrate side. Since the active matrix substrate is tested for each pixel, there is no need to mechanically move the probe to and from the pixel electrode of the active matrix substrate one by one as in the conventional method. Since it is possible to test each pixel in the active matrix substrate while scanning the scanning electrode and the test electrode on the test substrate side purely electrically or electronically as appropriate, the test time can be significantly shortened compared to conventional methods. For example, when there are 80,000 pixels in an active matrix substrate, it would take 40 hours to test all the pixels with the conventional method, but with the method of the present invention, short circuit defect testing can be done in one time.
The wire breakage test can be completed within 1 hour. In addition, all tests can be completed with the protruding electrodes on the test substrate in conductive contact with the pixel electrodes on the active matrix substrate in the original state when the two substrates are stacked, so contact The reliability of the test results can be improved by conducting the test in a state where the resistance is much more stable.

また、実施例の説明かられかるように本発明方法は表示
パネルの重欠陥とされる短絡欠陥試験にとくに有利で、
アクティブマトリックス基板内の画素数の3%程度の試
験数によって全画素について短絡欠陥の有無を短時間内
に効率よく進めることが可能である。
Furthermore, as can be seen from the description of the embodiments, the method of the present invention is particularly advantageous for testing short-circuit defects, which are considered to be serious defects in display panels.
By testing about 3% of the number of pixels in the active matrix substrate, it is possible to efficiently check for short-circuit defects in all pixels within a short period of time.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図から第3図までが本発明に関し、第1図は本発明
による表示パネルのアクティブマトリックス基板の試験
方法の実施例における重ね合わされたアクティブマトリ
ックス基板および試験用基板を関連する試験回路例とと
もに示す構成回路図、第2図はアクティブマトリックス
基板と試験用基板とを相互にやや離間された状態で示す
斜視図、第3図は両基板の重ね合わされた状態の断面図
である。第4図および第5図は本発明方法の対象である
アクティブマトリックス基板の構造例を示すもので、第
4図はその一部拡大上面図、第5図はさらにその要部の
断面図である。第6図は従来のアクティブマトリックス
基板の試験方法の要領を示すアクティブマトリックス基
板と試験回路との構成回路図である0図において、 1:絶縁基板、2:導電膜、3,5:遮光膜、4:半導
体膜、6:′dA縁膜、6a:絶縁膜の窓、7:接続膜
、10:画素電極、20:走査電極、20a:走査電極
の接続部、30:駆動素子、30p、30n:駆動素子
としての正、負方向の断面図、40ニアクチイブマトリ
ツクス基板、50:試験用基板、51:絶縁基板、52
:試験電極、52a:試験電極の接続部、53:突出電
極、54:ストッパ、60:探針ないしはプローブ、7
1:試験電圧源、71a:試験電圧の極性切換用切換ス
イッチ、72:電流測定器、73:選択スイッチ、74
:切換スイッチ、75:選択スイッチ、δ:押圧代、E
:試験電圧、SC:切換指令、Sh:水平選択指令、S
v:垂直選択指令、TS:試験信号、である。 基板 第1図 第2図 第3図
1 to 3 relate to the present invention, and FIG. 1 shows a superimposed active matrix substrate and a test substrate in an embodiment of the method for testing an active matrix substrate of a display panel according to the present invention, together with an example of a related test circuit. FIG. 2 is a perspective view showing the active matrix board and the test board in a state where they are slightly spaced apart from each other, and FIG. 3 is a sectional view of the two boards in a superimposed state. 4 and 5 show an example of the structure of an active matrix substrate that is a target of the method of the present invention, with FIG. 4 being a partially enlarged top view, and FIG. 5 being a sectional view of the main part thereof. . FIG. 6 is a configuration circuit diagram of an active matrix substrate and a test circuit showing the gist of a conventional active matrix substrate testing method. In FIG. 4: Semiconductor film, 6: 'dA edge film, 6a: Insulating film window, 7: Connection film, 10: Pixel electrode, 20: Scanning electrode, 20a: Scanning electrode connection part, 30: Drive element, 30p, 30n : Cross-sectional view in the positive and negative directions as a driving element, 40 Near active matrix substrate, 50: Test substrate, 51: Insulating substrate, 52
: test electrode, 52a: connection part of test electrode, 53: protruding electrode, 54: stopper, 60: tip or probe, 7
1: Test voltage source, 71a: Test voltage polarity changeover switch, 72: Current measuring device, 73: Selection switch, 74
: Changeover switch, 75: Selection switch, δ: Pressing distance, E
: Test voltage, SC: Switching command, Sh: Horizontal selection command, S
v: Vertical selection command, TS: Test signal. Board Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1)表示パネル面内に行列状に配列される各画素の表示
用の画素電極と所定方向に並ぶ画素電極に対して共通に
設けられた走査電極と各画素電極と走査電極との間に接
続された表示駆動用の駆動素子とを備えるアクティブマ
トリックス基板の試験方法であって、走査電極と交叉す
る方向に延びる細長な試験電極を走査電極の延びる方向
に沿って並べて設け、かつこの試験電極上の各画素電極
に対応する位置に先端が各画素電極に導電接触可能な可
撓性の突出電極を設けた試験用基板を用い、この試験用
基板を試験をすべきアクティブマトリックス基板と重ね
合わせて試験用基板側の試験電極上の各突出電極をアク
ティブマトリックス基板側の対応する画素電極に導電接
触させた状態でアクティブマトリックス基板側の走査電
極および試験用基板側の試験電極を走査しながら両電極
間に試験電圧を印加してアクティブマトリックス基板を
各画素ごとに試験することを特徴とする表示パネルのア
クティブマトリックス基板の試験方法。
1) Connection between each pixel electrode and the scanning electrode and a scanning electrode provided in common for the display pixel electrodes of each pixel arranged in a matrix on the display panel and the pixel electrodes arranged in a predetermined direction. A method for testing an active matrix substrate comprising a drive element for driving a display according to the present invention, wherein elongated test electrodes extending in a direction intersecting with the scan electrodes are arranged in a row along the direction in which the scan electrodes extend; Using a test substrate with flexible protruding electrodes whose tips can conductively contact each pixel electrode at positions corresponding to each pixel electrode, this test substrate is superimposed on the active matrix substrate to be tested. With each protruding electrode on the test electrode on the test board side in conductive contact with the corresponding pixel electrode on the active matrix board side, both electrodes are scanned while scanning the scan electrode on the active matrix board side and the test electrode on the test board side. 1. A method for testing an active matrix substrate of a display panel, comprising testing the active matrix substrate for each pixel by applying a test voltage between them.
JP63016247A 1988-01-27 1988-01-27 Testing method for active matrix substrate of display panel Pending JPH01191197A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63016247A JPH01191197A (en) 1988-01-27 1988-01-27 Testing method for active matrix substrate of display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63016247A JPH01191197A (en) 1988-01-27 1988-01-27 Testing method for active matrix substrate of display panel

Publications (1)

Publication Number Publication Date
JPH01191197A true JPH01191197A (en) 1989-08-01

Family

ID=11911227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63016247A Pending JPH01191197A (en) 1988-01-27 1988-01-27 Testing method for active matrix substrate of display panel

Country Status (1)

Country Link
JP (1) JPH01191197A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002003083A1 (en) * 2000-07-05 2002-01-10 Oht Inc. Inspection apparatus and inspection method
CN104050907A (en) * 2013-03-15 2014-09-17 烽腾科技有限公司 Systems And Methods For Recognizing Defects In Circuits

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002003083A1 (en) * 2000-07-05 2002-01-10 Oht Inc. Inspection apparatus and inspection method
CN104050907A (en) * 2013-03-15 2014-09-17 烽腾科技有限公司 Systems And Methods For Recognizing Defects In Circuits
JP2014209100A (en) * 2013-03-15 2014-11-06 フォトン・ダイナミクス・インコーポレーテッド System and method for monitoring display during inspection in real time

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