JPH01189168A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor p-n-p transistor having a high current amplification factor, by providing an n-type base region and a p-type emitter region in a groove which is formed in a p-type collector region. CONSTITUTION:An island shaped p-type collector region 4 is formed in an n-type epitaxial layer for forming a transistor. A base region 5A, whose region is a groove, is formed in the groove in an n-type region. A p-type emitter region 6 is formed in the region 5A. As a result, a plane facing the p-type emitter region 6 in the p-type collector region 4 becomes relatively large. The width of the base depends on the diffusing depth of the n-type base region 5A. Thus, the semiconductor p-n-p transistor having a high current amplification factor is obtained.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device, particularly a semiconductor device having a PNP transistor, the present invention aims to provide a semiconductor device with a PNP transistor that can obtain a high current amplification factor, and a P2 substrate and the PNP transistor.
In a semiconductor device having a PNP transistor provided on an n-type T bitaxial layer formed on a type substrate, an n-type collector region formed in an island shape in the n-type epitaxial layer, and a p-type collector fa region formed on the n-type epitaxial layer. an n-type base region formed with a predetermined thickness in a groove formed in the groove, and an n-type emitter region formed in the groove on the n-type base region and substantially filling the groove. Configure.

(Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a semiconductor device having a PNP transistor.

[Conventional technology]

FIG. 8 shows a semiconductor device having a conventional PNP transistor. FIG. 8(a) is a plan view of the semiconductor device;
b) shows a cross-sectional view along the line ■-■. Semiconductor devices are
A p- type substrate 100, an n+ type buried layer 101, an n type epitaxial layer 102, an element isolation region 103, an n type collector region 104, an n type emitter region 105, an n type
It consists of a + type (or n type) space region 106 and an S + 02 film 107. ] Corresponding collector contacts 104a, emitter contacts 105a, and base contacts 106a are provided above the collector region 104, emitter region 105, and space region 106.

As is clear from FIG. 8, the back side of the collector region 104 facing the emitters Ijlt105 is relatively small.

Also, the base width WB1 is equal to the hole interval d and the collector and emitter regions 104. Depending on the diffusion depth X J 1 of 105, the aperture spacing d is determined by lithography. Further, in order to set a large current amplification factor, the collector and emitter regions 104 and 105 are made large, and therefore their respective junction capacitance and stray traffic are relatively large.

On the other hand, in the above semiconductor device, an NPN transistor is often formed on the same p-type substrate 100 in addition to a PNP transistor. This is because PNP transistors and NPNI-transistors can be formed using a common process. However, in the process of forming the n-type base region of the NPN transistor, the p-type "rector and emitter regions 104 of the PNP transistor. 1
05, the impurity temperature of the emitter region 104 of the PNP transistor is set to be relatively low in accordance with the n-type base region of the NPN transistor.

[Problem that the invention seeks to solve]

Therefore, the PNP transistor of the conventional semiconductor device has N
Compared to a PN transistor, the base transport efficiency is poor and the cutoff frequency is also unsatisfactory.Also, when NPN transistors are formed on the same substrate by a common process, the emitter injection efficiency is lower than that of an NPN transistor. As a result, a problem occurred in that the current amplification factor was low.

The present invention provides a PNPI that can achieve a high current amplification factor.
- An object of the present invention is to provide a semiconductor device having a transistor.

[Means for solving problems]

The above problem is caused by the p-type substrate and the n-type substrate formed on the p-type substrate.
In a semiconductor device having a PNP transistor provided on an epitaxial layer, a p-type collector f! is formed in an island shape on the n-type epitaxial layer. 414 and the p
An n-type base region formed with a predetermined thickness in a groove formed in a type collector region, and a p-type emitter region formed in the groove on the n-type base region and substantially filling the groove. This problem is solved by a semiconductor device having VI'fl.

[Effect]

The n-type base region and the p-type emitter region are respectively
It is provided within a groove formed in the mold collector region. Therefore, the surface of the p-type collector #J region facing the p-type emitter region is relatively large, and the base width depends on the depth of diffusion of the n-type base region.

Therefore, as a PNP transistor of a semiconductor device, one having a high current amplification factor is used.

〔Example〕

FIG. 1 shows a first embodiment of the present invention. FIG. 1 (a) is a plan view of the first embodiment, and FIG. 1 (b) is a sectional view taken along line -I.

The first embodiment of the semiconductor device includes a p m'1 substrate 1 and an n
It consists of a type epitaxial layer 2, an element isolation region 3, a p-type collector region 4, an n-type base region 5, a p-type emitter region 6, and a high impurity cJ concentration region. The n-type base region 5 and the p-type emitter region 6 are each a p-type collector region t4.
It is provided in a groove 8 formed in 4. For this reason, p
The surface of the p-type collector region 4 facing the p-type emitter region 6 is relatively large (the base width W8 depends on the diffusion depth XJ of the n-type base region 5. Since the mold emitter region 6 does not need to be set large as in the conventional example, the respective junction capacitance and stray capacitance are small.

Furthermore, by using, for example, p-type polysilicon for the p-type emitter region 6, the junction capacitance between the p-type emitter region 6 and the n-type base region 5 can be made extremely small. Therefore, according to this embodiment, the current amplification factor of the PNP transistor is improved compared to the conventional one.

Next, an example of the formation process of the first embodiment will be explained with reference to FIG. 2.

FIG. 2(a) shows a p-type silicon single crystal wafer used as an example of a p-type substrate.

As shown in FIG. 2(b), a p-type substrate 1 is coated with n-type silicon as an example of an n-type epitaxial layer 2 with a film thickness of 2 μm.
grow up. Note that the specific resistance of the n-type epitaxial layer 2 is 0.5Ω-crx to 1.5Ω-crx. It is OQ-α.

Next, B" ions are implanted into the n-type epitaxial layer l!'!2 and annealing is performed to form the element isolation region 3 as shown in FIG. 2(C).

The p-type collector region 4 is formed as shown in FIG. 2(d) by implanting B1 ions into the n-type epitaxial layer 2 separated by the element isolation region 3 and performing annealing.

Next, a SiN film 10 is formed to a thickness of, for example, 2,000 wafers, and a base window 11 is opened in the region where the base will be formed by lithography, as shown in FIG. 2(e). base window 11
The window width is, for example, 1 μm.

The n-type epitaxial layer 2 exposed through the base window 11 is etched to a depth of, for example, 0.6 μm, as shown in FIG. 2(1'), to form a groove 8. The etching may be dry etching, wet etching, or dry and wet etching.

Next, the PSG (or ASSG) film 13 is
The film was grown to a thickness of μ-, annealed, and then shown in Figure 2 (l
As shown in <n-type epitaxial layer 2 from the PSG film 13 side.
An n-type base region 5 is formed by performing n-type diffusion to the side. The base width W8 is, for example, 300 people.

Thereafter, the PSG film 13 is removed by etching as shown in FIG. 2(h).

Next, as shown in FIG. 2(i), p-type doped polysilicon g114 is grown to a thickness of, for example, 2 μm.

The polysilicon film 14 has a thickness of 5i as shown in FIG.
NI) Polished to 110.

Next, the SiN film 10 is removed by etching and a high impurity concentration region 7 is formed by p+ doping, thereby forming a first embodiment of the semiconductor device as shown in FIG. 2(k).

FIG. 3 shows the main part of a modification of the first embodiment.

In this embodiment, the impurity concentration of the base region is high, and an n+ type base region 5A is provided in place of the n type base region 5. In the process shown in FIG.
It can be formed by applying a diffusion source and adding annealing diffusion.

Next, a second embodiment of the present invention will be described with reference to FIG. In FIG. 4, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted.

In this embodiment, the high impurity concentration region 7A has approximately the same depth as 8. Therefore, the collector resistance is smaller than that of the first embodiment, and the characteristics of the PNP transistor can be improved. It goes without saying that instead of the n-type base region 5, an n+-type base region 5A may be provided as in the modification of the first embodiment.

FIG. 5 shows a third embodiment of the invention. In Figure 5, 1st
Parts that are the same as those in the drawings are marked with the same symbol, and their explanation will be omitted.

In this embodiment, an n+ type buried layer 20 is provided which is buried in the p- type substrate 1, is in contact with the n type epitaxial layer 2, and has a higher impurity concentration than the n type 1 bitaxial layer. By forming this n+ type buried layer 20, it is possible to simultaneously perform the element isolation region diffusion step and the collector diffusion step shown in FIGS. 2(c) and 2(d).

FIG. 6(a) shows the main part of the fourth embodiment of the present invention, FIG.
b) shows the main part of the first modification of the fourth embodiment, and FIG. 6(C) shows the main part of the second modification of the fourth embodiment. In Figure 6, 1st
The same parts as those in the figures and FIG. 3 are given the same reference numerals, and the explanation thereof will be omitted.

In this embodiment, the insulating film 30 is formed only on the sidewalls of the n-type base region 4 within the groove 12.

For example, 5102 or SiN is used for the insulating film 30.
? Ru. This insulating film 30 is formed by growing an insulating film on the n-type base region 5F to achieve an absolute R1! It can be formed by removing only the bottom part of the surface by anisotropic etching. Therefore, the base width WB can be controlled by this etching. In this embodiment, since the n-type base region 5 and the p-type emitter region 6 are in contact only at the bottom of 1178,
Junction capacitance can be set small.

In the first modification of this embodiment, the bottom of the groove 8 in the n-type base region 5 is an n1-type region 5a with a high impurity concentration. This improves the current amplification factor of the PNP transistor.

In the second modification of the present embodiment, an n'' type base region 4A is provided, and the same effects as in the first modification can be obtained.

Next, a fifth embodiment of the present invention will be described with reference to FIG. In FIG. 7, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted.

In this embodiment, in addition to a PNP transistor similar to that of the first embodiment, an NPN transistor is formed on the same p-type substrate 1 in a region separated from the PNP transistor by an element isolation region 3.

The NPN transistor includes an n-type collector region 41 constituted by the n-type epitaxial layer 2, and an n-type collector region 42 formed in the n-type collector region 41 with a predetermined thickness.
It consists of a type base region 43 and an n-type emitter region 44 formed within the trench 42 on the p-type base region II 3 and substantially filling the trench 42 . These PNP and tN'N
Although the transistors can be formed using a common process, the current amplification factor of a PNP transistor is improved compared to the conventional one even when a common process is used for forming an NPN transistor.

Note that the shapes of the n-type base regions 5.5A, 5a and the n-type base region 43 are not limited to the approximately U-shape as in the embodiment. Further, a heavily doped n-type buried layer may be provided between each p-type substrate 1 and n-type epitaxial layer ff14.41.

Although the present invention has been described above with reference to examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not intended to be taken away from the present invention.

〔Effect of the invention〕

According to the present invention, since the n-type base region and the n-type emitter region are respectively provided in the grooves formed in the n-type collector region, the surface of the n-type collector region facing the n-type emitter region is Since the base width is largely dependent on the diffusion depth of the n-type base region, it is possible to obtain a PNP transistor of a semiconductor device with a high current amplification factor, which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of the present invention, FIG. 2 is a diagram explaining a forming process of the first embodiment, FIG. 3 is a diagram showing main parts of a modification of the first embodiment, and FIG. 4 shows a second embodiment of the invention, FIG. 5 shows a third embodiment of the invention, and FIG. 6 shows a fourth embodiment of the invention and its first and second modifications. FIG. 7 is a diagram showing a fifth embodiment of the present invention, and FIG. 8 is a diagram showing an example of a conventional device. 1 to 7, 1 is a p-type substrate, 2 is an n-type epitaxial layer, 3 is an element isolation region, 4 is an n-type collector region, 5 is an n-type base region, 5A is an n++ base region, 5a is an n+ type region 6 is an n type emitter region, 7.7AG is a high impurity concentration region, 8 is a groove, 10 is a SiN film, 11 is a base window, 13 is a PSG film, 14 is a polysilicon film, 20 is an n++ 30 is an insulating film; 41 is an n-type collector region; 42 is a trench; 43 is an n-type base region; and 44 is an n-type emitter region. Patent applicant: Fujitsu Ltd. Fujitsu VLSI Ltd. Figure 1 Figure 3 showing the main parts of a modification of the first embodiment Figure 2 explaining the forming process of the first embodiment l)p Figure 2 (part 2) Figure 4 depicting the second embodiment of the present invention Figure 4 depicting the third embodiment of the present invention Figure 5 (a) (b) Fig. 6 A diagram showing the fifth embodiment of the present invention Fig. 7

Claims (5)

[Claims] (1) In a semiconductor device having a p-type substrate (1) and a PNP transistor provided on an n-type epitaxial layer (2) formed on the p-type substrate, an island-like structure is formed on the n-type epitaxial layer. a p-type collector region (4) formed in the p-type collector region; an n-type base region (5, 5A, 5a) formed with a predetermined thickness in the groove (8) formed in the p-type collector region; A semiconductor device comprising: a p-type emitter region (6) formed on the n-type base region and substantially filling the trench. (2) The p-type collector region (4) has approximately the same depth as the groove (8) and has a contact p^+-type region (7A ) The semiconductor device according to claim 1, wherein the semiconductor device has: (3) In a semiconductor device having a p-type substrate (1) and a PNP transistor provided on an n-type epitaxial layer (2) formed on the p-type substrate, the n an n-type buried layer (20) that is in contact with the n-type epitaxial layer and has a higher impurity concentration than the n-type epitaxial layer;
a type collector region (4), an n-type base region (5) formed with a predetermined thickness in a groove (8) formed in the p-type collector region, and an n-type base region (5) formed on the n-type base region in the groove. A semiconductor device comprising: a p-type emitter region (6) formed in the trench substantially filling the trench. (4) In a semiconductor device having a p-type substrate (1) and a PNP transistor provided on an n-type epitaxial layer (2) formed on the p-type substrate, an island-like structure is formed on the n-type epitaxial layer. a p-type collector region (4) formed in the p-type collector region; an n-type base region (5, 5A, 5a) formed with a predetermined thickness in the groove (8) formed in the p-type collector region; an insulating film (30) formed only on the sidewalls of the n-type base region; and a p-type emitter region (30) formed in the trench on the n-type base region and the insulating film and substantially filling the trench. 6) A semiconductor device comprising: (5) P-type substrate (1) and n formed on the p-type substrate
A semiconductor device comprising a PNP transistor and an NPN transistor provided on a type epitaxial layer (2), and an element isolation region (3) separating the PNP transistor and the NPN transistor on the p-type substrate, The PNP transistor is formed with a predetermined film thickness in a p-type collector region (4) formed in an island shape in the n-type epitaxial layer and in a first groove (8) formed in the p-type collector region. the NPN transistor comprises: an n-type base region (5); and a p-type emitter region (6) formed on the n-type base region in the first trench and substantially filling the first trench; , an n-type collector region (41) formed of the n-type epitaxial layer separated from the PNP transistor by the element isolation region; and a predetermined groove (42) formed in the n-type collector region. a p-type base region (43) formed with a film thickness of , and an n-type emitter region (44) formed on the p-type base region in the second trench and substantially filling the second trench. A semiconductor device characterized by comprising: