JPH01187852A - Semiconductor integrated logic circuit - Google Patents

Abstract

PURPOSE:To facilitate the test of an internal circuit without particularly providing an input terminal for the test by connecting a clock input terminal to the data input of a flip-flop, and incorporating at least one circuit connected through a delay circuit to the clock input of the flip-flop. CONSTITUTION:A flip-flop 1 is of a D type flip-flop, and its input terminal 3 is connected directly to a data input terminal D and connected through a delay circuit 2 having a delay time (d) to a clock input terminal C. T1 is a circuit control signal terminal for a test, and S1 is a signal terminal connected to an internal circuit. When a clock signal A1 of high frequency is applied at the time of really using, the terminal T1 becomes a low level. A clock signal A1 of low frequency is applied at the time of testing, the T1 becomes a high level. Accordingly, the internal circuit can be controlled by altering the frequency of the signal input to the terminal C.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated logic circuit, and particularly to a logic circuit including a test circuit.

[Conventional technology]

Conventionally, this type of circuit has been constructed using an LSI10 as shown in FIG.
There is a normal input terminal, I2.... Besides, at least one test input terminal T, 1°T32...T
Sn is provided and the internal circuit 11 is controlled by switching this signal to high level or low level to facilitate testing.

[Problem that the invention seeks to solve]

The above-described conventional semiconductor integrated logic circuit requires a test input signal terminal in addition to a normal input signal terminal, and therefore has the disadvantage that the number of pins as an LSI increases.

[Means for solving problems]

The semiconductor integrated logic circuit of the present invention includes at least one circuit whose input terminal is connected to the data input of the flip-flop and connected to the clock input of the flip-flop via a delay circuit. It is used as a means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In this figure, a flip-flop 1 is a D-type flip-flop, and an input terminal 3 is directly connected to a data input terminal and is also connected to a clock input terminal C via a delay circuit 2 having a delay time d.

TI is a test circuit control signal terminal, and SL is a signal terminal connected to the internal circuit.

When a lock signal AI is applied to this input terminal 3 as shown in FIG. Delay time d from A1
A waveform signal B1 having the following values is input. As a result, the output of flip-flop 1 is always at a low level.

On the other hand, when a relatively low frequency signal as shown in FIG. 2(b) is applied to this input terminal 3, the data input terminal of the flip-flop 1 receives the clock signal A2,
As in the case of Fig. 2(a), the waveform signal B2 delayed by the delay time d is inputted to the input terminal, but because the clock signal A2 has a low frequency, unlike the case of Fig. 2(a), a flip-flop is input. 1 always outputs a high level.

From the above, when applying the high frequency clock signal A1 during actual use, the test circuit control signal terminal TI becomes low level, and during testing, by applying the low frequency clock signal A2, the test circuit control signal terminal TI becomes low level. Since T1 is at a high level, the internal circuit can be controlled by changing the frequency of the signal input to the clock input terminal C.

Further, during actual use, the signal terminal S1 is supplied to the internal circuit as a normal clock signal.

FIG. 3 is a circuit diagram of another embodiment of the present invention.

In this figure, the flip-flop 5 is a D-type flip-flop.
and is connected to the data input terminal via a delay circuit 6 having a delay time d. T2 is a signal terminal to which the test circuit control signal terminal S2 is connected to the internal circuit.

The clock signal A1 shown in FIG. 2(a) is input to this input terminal 7.
When C is applied, the clock input terminal C of the flip-flop 5
The clock signal A1 is input as is to the data input terminal, and the delayed waveform signal B1 is input to the data input terminal. As a result, the output of the flip-flop 5 is always at a high level.

On the other hand, the clock signal A shown in FIG. 2(b) is input to the input terminal 7.
2, the delayed waveform signal B2 is input to the data input end of the flip-flop 5, so the output Q of the flip-flop 5 is always at a low level.

From the above, in the embodiment shown in FIG. 3, contrary to the embodiment shown in FIG. 1, the control signal terminal T2 is at a high level during actual use, is at a low level during testing, and internal circuit switching can be performed in the same way. can.

〔Effect of the invention〕

As described above, the present invention has a clock input terminal connected to a data input of a flip-flop, and includes at least one circuit connected to a clock input of a flip-flop via a delay circuit. This has the effect that internal circuit testing can be easily performed without providing any special input terminals.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2(a),
(b) is a waveform diagram showing the waveform of the signal applied to the circuit;
FIG. 3 is a circuit diagram of another embodiment of the present invention, and FIG. 4 is a circuit diagram of a conventional example. 1.5...Flip-flop, 3,7...
...Signal input terminal, 2,6...Delay circuit with delay time d, TI, T2...Test circuit control signal, Sl, 82...To internal circuit Connected signals, AI, A2...Clock signal, Bl
, B2...Delayed signal, 10...LS
I, 11...Internal circuit, ■, ~Eng.・・・・・・
- LSI input terminal, TS, ~TS, ... test input terminal, 01 - O0 ... LSI output terminal. Agent Patent Attorney Susumu Uchihara $ 3 2 $ 4 r

Claims (1)

[Claims] A semiconductor integrated logic circuit having a clock input terminal, the clock input terminal being connected to a data input of a flip-flop, and including at least one circuit connected to the clock input of the flip-flop via a delay circuit. Features of semiconductor integrated logic circuits.