JPH01186021A - Superheterodyne receiver - Google Patents

Abstract

PURPOSE:To obtain a local oscillating frequency lower than the frequency of a reception band and to simplify the constitution of a local oscillation circuit by employing double superheterodyne system for the entire configuration of a receiver and varying the step width of 1st and 2nd frequencies depending on the change in the frequency division ratio of a PLL. CONSTITUTION:A reception signal Sr from an antenna 1 is mixed with a signal S1 outputted from a VCO 21 of a PLL 20 under the control of a microcomputer 30 by a 1st mixing circuit 3 to output a 1st intermediate frequency signal Si1. The signal Si1 is mixed with a signal S2 in a 2nd local oscillation frequency from the VCO 41 by a 2nd mixing circuit 5 via an IF1 4. The signal S1 from the PLL 20 is halved by a frequency dividing circuit 22, the frequency division signal is frequency-divided into 1/N at a variable frequency dividing circuit 23 and supplied to a phase comparing circuit 24. The signal is compared with a reference frequency f0 from a shaping circuit 25 by the circuit 24, the step width of the signal S1 from the VCO 21 is varied and the frequency f1 is brought to a prescribed range with respect to the reception frequency band.

Description

[Detailed description of the invention] The explanation will be given in the following order.

A. Industrial application field B. Summary of the invention C Conventional technology D Problems to be solved by the invention E. Means to solve the problem (Figure 1) F. Effect G'X flow Side 1 First embodiment (Figures 1 and 2) G2 Other embodiments Effect of H invention A. Industrial application field This invention relates to a super receiver.

B. Summary of the Invention The present invention provides a super receiver with a double super configuration and a second local oscillation frequency of, for example, 2.
By adopting two values, the reception characteristics are improved and the overall configuration is simplified.

C. Conventional technology As an IC for a synthesizer receiver, an IC that combines a PLL for a local oscillation circuit and a microcomputer for controlling the division ratio of a variable frequency dividing circuit of this PLL according to the receiving frequency is used. be.

Therefore, if such Ic is used, it should be possible to configure a synthesizer receiver relatively easily and obtain excellent reception characteristics.

Problems to be Solved by the Invention However, in the variable frequency dividing circuit of Ic mentioned above, the upper limit of the frequency that can be divided (that can be done manually) is about 40M11z due to the relationship of the frequency division ratio and the like.

Therefore, the reception band should be set to 150kllz to 30M, for example.
If it is set to Hz, the intermediate frequency will be 10.7 M1lz, so the interference characteristics (image characteristics) cannot be improved much.

For this reason, a preselector or an open circuit between the antennas is required on the input side of the first-stage single-frequency amplifier, and a tuning coil is required for this preselector or antenna tuning circuit. Since electromagnetic and static coupling with the receiver must be avoided, the need for such a tuning coil is disadvantageous for space factors and overall component placement, and is an impediment to receiver miniaturization. Put it away.

In addition, the antenna same 1fil [IL path includes - for tuning.
A J variable capacitance diode is required, and in order to improve reception characteristics, countermeasures against tracking errors are also required.

Furthermore, assuming that the reception band and intermediate frequency are the above-mentioned numerical example, the local oscillation frequency is lo, 85MHz to 40.7
The frequency range of MIIz must be changed, and the frequency change ratio is 3.75 times or more. However, it is difficult to obtain such a large frequency change ratio with a single variable capacitance diode, so it is necessary to switch between two variable capacitance diodes, or to turn on and off an auxiliary capacitor to the variable capacitance diode. It is necessary to find a way to do this, and this must be done using a high-frequency circuit called a local oscillation circuit, which makes the configuration complicated.

In this respect, if a frequency divider circuit (prescaler) with a frequency division ratio of, for example, 1/2 is provided before the uJ variable frequency divider circuit of the PLL, even if the local oscillator frequency is 80MIIz, the variable frequency divider circuit can be used. Since the frequency input to the
．． The frequency can be 15 MHz to 80 MIIz, and the intermediate frequency can be 50 MHz.

If such a local oscillation frequency and intermediate frequency are used, the above-mentioned problems can be eliminated.

However, in this case, even if the reference frequency supplied to the phase comparison circuit of the PLL is, for example, 5 kHz, the local oscillation frequency will change by 1. This results in a 10kHz jump.

This invention attempts to solve the above problems.

G: Means for Solving the Problems Therefore, in the present invention, the entire structure is made into a double super structure, and the first local oscillation wave number (11) and the second local oscillation frequency f2 are set to be different from the receiving frequency. 2).

1=゛ The operational reception characteristics are mainly determined by the first local oscillation No. 1d, and the step width of the receiving frequency is determined by the first and second local oscillations (6
Determined by the number.

G Example G1 First practical hi example In the example shown in Fig. 1, reception band...147kHz2 to 30MH2
MW band (long/medium wave band)...147kHzA-16
14kllzSW+fII (short wave band)...161
Step width of 5kHz2 to 30MH2 reception frequency MW Natsume...3kHzSW band
...b k) lz.

J-, that is, the received signal Sr of antenna +11 is supplied to the first mixer circuit (3) through the quotient frequency amplifier (2), and is also supplied from the Vex (21) for the first local oscillation circuit to the mixer circuit (3). A second local excavation signal S1 is supplied to the signal Sr, and the frequency of the signal Sr is converted into a first intermediate frequency signal Si1.

In this case, this frequency conversion is upper heterodyne, where fr: reception frequency (signal 5r) fL: first local oscillation frequency (signal 5L) r1□: first intermediate frequency (signal 3i1), then fl□ = ft −fr ...= (i
). The details will be described later, but as shown in FIG. 2A, the first local oscillation frequency [1 is
For example, f t =55.992M1lz ~85.84M1l
Over the range of Z, it changes stepwise every 6 kHz in M W 4j) and every 10 kHz in the SW band. Moreover, f i 1=55.845 MHz.

Then, the first word Sii from the mixer circuit (3) is
Intermediate frequency filter (4) (pass band is, for example, Fit
±10kHz) to the second mixer circuit (5), the first local oscillation signal S2 is also supplied from the VCO (41) for the second local excavation circuit to the mixer circuit (5), and the signal SiL is supplied to the second mixer circuit (5). The frequency is converted into an intermediate frequency signal Si2.

In this case, this frequency conversion is lower-heterodyne, f2: second local excavation frequency (signal S2) [12: second
Assuming the intermediate frequency (signal 5i2), it is 112 times fi1-r2 (ii). Although the details will be described later, as shown in FIG. 2B, the second local oscillation frequency f2 is set in the MW band for any step value of the frequency rz, corresponding to the reception frequency fr. Then f 2 = 55.39M)lz or 55.387M
In HzSW band, f2 = 55.39MHz or 55.585MH
It is controlled by two values of z. That is, in the hiw band, r 2 = 55.39M1lz -3kHz
In the nSW band, f2-55.39MHz -5k)
lx X n However, n=o or l... (iii) Controlled. Moreover, E i 2 = 455kllz.

Then, the signal Si2 from the mixer circuit (5) is passed through the second intermediate frequency filter (6) (the pass band is, for example, fi2±
2.3kHz), and further through an intermediate frequency amplifier (
7) to a demodulation circuit (8) where the audio signal is demodulated, and this signal is supplied to a speaker (10) through a low frequency amplifier (9).

Further, the VCO (21) constitutes a part of the PLL (20). That is, the signal S1 from the VCO (21) is supplied to the frequency divider circuit (22) and divided into 1/2 frequency, and this frequency divided signal is supplied to the variable frequency divider circuit (23) to 1/H. This frequency-divided signal is supplied to the phase comparator circuit (24) and also to the formation circuit (25).
The reference signal So of the reference frequency fO is supplied to the comparison circuit (24)
The comparison output of this comparison circuit (24) is supplied to the VCO (21) through a low-pass filter (26) as its control signal.

In this case, the frequency division ratio N of the frequency dividing circuit (23) is N in the MW band, N in the -9332 to 9576 SW band, corresponding to the reception frequency fr.
= can be changed in increments of "1" over the range of 5746 to 8584. Also, the frequency r of the reference signal So
O is controlled to fo-3kHz in the MW band and fo=5kHz in the SW band.

A microcomputer (30) is provided to control the frequency division ratio N and the second local oscillation frequency [2 as described above in accordance with the receiving frequency fr.

→''In other words, (31) is the CPLI, (32) is the ROM in which programs for the above-mentioned channel selection processing etc. are written, (33) is the RAM for the work area, (
34) to (36) are the output boat, (37) is the human powered boat, and these circuits (32) to (37) are the system hash (3
8) to the CPU (31). A control signal Sc for switching the frequency ro of the reference signal So between 3 kHz and 5 kHz when receiving the MW band and when receiving the SW band is extracted from the boat (34) and sent to the forming circuit (25). At the same time, the data of the frequency division ratio N is taken out and supplied to the frequency division circuit (23).

In addition, when receiving the MW band from the boat (35), n
-U, the control signal 5llI is at "L" level, n-1 is at 'h' level, and when receiving the SW band, the control signal 5llI is at the "L" level.
At 4 o'clock, it becomes "L" level when n = 0, it becomes H" level when n = 1, and it becomes "L" at 16 o'clock when receiving the MW band.
The level control signal Ss is taken out, and the level signal Sm
, Ss are supplied to the paces of transistors Qx, Q2.

Terminals ゛1゛3 to which a constant DC voltage Vr is supplied
and ground, a resistor WR3, a resistor R>, and the collector-emitter of the transistor Q1 are connected in series, and the midpoint of the junction "C" of the resistors R3 and R1 is connected to the ground. In between, a resistor "aH2" and the collector-emitter of the transistor Q2 are connected in series, and these resistors R1 to
The voltage v2 obtained at the connection midpoint of R3 is VCO (41)
is supplied as its control voltage.

Furthermore, in Bo) (36) and (37), rO
Number keys from J to "9" 5o=S9, enter key b
e, operation keys (operation switches) such as an up key Su and a down key Sd for scanning the reception frequency fr in the upward and downward directions are connected,
These operation keys 5o-5d are dynamically scanned by the boat (36) and their key outputs are
7).

In addition, in FIG. 1, the rotation Iar (22) surrounded by a chain line
-(25), (31)-(38) are integrated into one chip IC.

According to such a configuration, when the keys 5o-3d\ri are operated, the reference frequency co, the frequency division N, and the voltage v2 are controlled in accordance with the operated keys, and the reception frequency rr is set.

In other words, the MW band receiver 47. Sometimes 5s−=l″L′
'', transistor Q2 is turned off, and S-1 is turned off or 5111-11'' is turned off corresponding to the reception frequency fr.
becomes. In this case, when Sm="L",
Since the transistor Q1 is also turned off, V2 becomes Vr, and the oscillation frequency r2 of the VCO (41) is r2 = 55.39M1lz (n = 0)
Also, when the S tide is -'"l]", the transistor QL is turned on, so V2-Vr-Rt/ (R
t+1(3), and the frequency f2 becomes r2-55.387M1lZ (n=1) corresponding to this voltage (2).

Similarly, when receiving the SW band, the transistor Q1 is turned off when Ss is "L", and the receiving frequency becomes Ss-"L" or Ss="L". As a result, when Ss-''L'', r 2-5
5.39M117. (n −0), Ss−“H”
When, f t = 55.385 Mllz (n -1)
becomes. In other words, the frequency 12 is the same as the frequency division output of the frequency division circuit (23) at the time of footsteps.
The criterion ('ei vS o is fl-2XNXf, since their frequencies are equal to each other.

Therefore, in the MW band, f1 = 2X3XN (kHz), in the SW band, It = 2X5XN (kHz)... (iv
).

Then, by transforming equations (i) and (ii), fr=
ft fix f ffi = f i2 + [z, so from these, rr mouth f1-[12-f2... (v), and further substitute equations (iii) and (iv) into equation (V). In the MW band, [r=6N 455 (553903n)=6N
-55845+3 n (k) lz ) ... (
vl) In SW band, fr = 1ON -455(55390-5n) = 1O
N -55845+ 5 n (kHz)...
(vi).

And in the MW band, N = ! 1332~! +ri'/6, n-0 or 1, so from formula (vl) when N = 9332, f r = 6 X 9332-55845+ 3 n
=147+3n =147 or 150 (kHz)N -9333
When, f r = 6 X 9333-55845+ 3 n
= 153 + 3n = 153 or 156 (kHz), and in the same way as above, when N = 95'/6, [r = 6X95° / 6 - 55845 + 3 n = 16
11+3 n = 1611 or 1614 (kllz).

Therefore, while changing the frequency division ratio N by 1-1'', the second local oscillator frequency f is changed for each value of the frequency division ratio N.
2 to 71 (n-0 or l) as shown in 2nd l8
By changing to , in MW, its reception frequency fr
can be changed in 3kllz steps.

Also, in the SW band, N -5746 to 8584, n = 0 or l, so from equation (vi) when N = 5746, f r = 10 x 5746 - 55845 + 5
n=1615+5 n=1615 or 1620 (kflz)N=
When 574'/, r r = '10 X 5'/4'7 5. ')84
5+5n-1625+5n=1625 or 1630 (kllx),
Similarly, when N = 8584, f r = 10 x 8584 55845 + 5
n = 29995 + 5 n = 29995 or 30000 (kHz).

Therefore, while changing the frequency division ratio N by "1",
By changing the second local oscillation frequency f2 to a binary value (n=0 or l) as shown in FIG.
It can be changed using the z step.

Thus, according to the invention, from 14'/kHz to 3
It is possible to receive radio waves such as broadcasting over a wide band of 0M1lz, but in this case, according to the present invention, PLL (2
0) with a frequency division ratio of 1/2 in the front stage of the variable frequency divider circuit (23).
Since the frequency dividing circuit (22) is provided, the variable frequency dividing circuit (22) is provided.
Even if the frequency that can be manually generated in 23) is about 40 Mtlz, the oscillation frequency f1 of the VCO (21) can be about 8 () MHz, and therefore the receiving band is 147 kHz.
Since the intermediate frequency fi1 can be made as high as 55.845Mlz even if the frequency is 30Mlz to 30Mlz, the anti-corrosion characteristics can be improved.

In addition, since there is no need to provide a preselector or antenna tuning circuit before the first-stage crystal frequency amplifier (2), there is no need for a tuning coil that can cause trouble due to electromagnetic coupling or electrostatic coupling, and the receiver can be It can be made smaller. Also, there is no need to take measures against tracking error in the antenna tuning circuit.

Furthermore, the frequency range of the local frequency f1 is f1=55.992MH2 to 85.84MH2 for its reception band.
MHz, and the change ratio of the frequency f1 is 1.53 times,
Due to its small size, the VCO (21) only needs to use one variable capacitance diode, and there is no need to turn on and off other variable capacitance diodes or auxiliary capacitors at high frequencies, thus simplifying the configuration. With,
Also from this point of view, miniaturization is possible.

In addition, by providing the frequency dividing circuit (22), the frequency division ratio N
Even if the local frequency fl is changed by 11'', the local frequency fl changes by twice the reference frequency fa, that is, by 6klz in the MW band and by 1okHz in the SW band. , the second local oscillation frequency f2 takes two values for one value of the frequency division ratio N, as shown in FIG. That is, it can be changed in steps of 3 kHz in the MW band and 5 kHz in SW++.

Furthermore, by providing the frequency dividing circuit (22), when the frequency division ratio N is changed by 1, the local oscillation frequency f1 can be prevented from changing by twice the reference frequency Co.
The reference frequency rO is set to 1/2 of the original frequency, that is, M
1.5kHz in W band, 2.5kHz in SW band
There is also a way to keep it as such. However, in this case,
While the reference frequency "0" becomes low and the C/N decreases, in this invention, the reference frequency fo is raised to a value equal to the step width of the receiving frequency [r, so the C/N decreases. A good PLL (20) can be obtained.

G2 Other Examples Note that in the above, the frequency f in vco (41)
2 switching is done without using a variable capacitance diode.
This can also be done by switching and connecting fixed capacitors.

In addition, the frequency division ratio m of the frequency dividing circuit (22) is m=
2, but it can also be an integer of m≧2, in which case the second local frequency f2 for one frequency division ratio N value
may be changed to m stages.

Effects of the Invention According to this invention, the variable frequency divider circuit (2) of the PLL (20)
3), a frequency divider circuit (22) with a frequency division ratio of 1/2 is provided, so even if the frequency that can be input to the variable frequency divider circuit (23) is about 40 MHz, the oscillation of the VCO (21) will not occur. The frequency f1 can be set to about 80M1, and therefore, even if the reception band is 147kHz to 30M1lz, the intermediate frequency fil can be made as high as 55.845MHz, so that the interference characteristics can be improved.

In addition, it is no longer necessary to provide a preselector or antenna tuning circuit before the first stage high-frequency amplifier (2), which eliminates the need for a tuning coil that causes draughts due to electromagnetic and capacitive coupling, making the receiver more compact. can be converted into Furthermore, there is no need to take measures against tracking errors in the antenna tuning circuit.

Furthermore, the frequency range of the local frequency f1 is f 1” 55.992MHz to 85.8MHz with respect to its reception band.
4MHz, and the change ratio of the frequency f1 is as small as about 1.53 times, so it is only necessary to use one variable capacitance diode for vco (21), and at a crystal frequency (
There is no need to add a variable volume diode or an auxiliary capacitor to the system, which simplifies the configuration and also allows for miniaturization.

In addition, by providing the frequency dividing circuit (22), the frequency division ratio N
Even if the local frequency ft is changed by l” I J, the local frequency ft is
twice the reference frequency fo, i.e. 6k in the MW band
Although it changes by 10 kHz in the SW band, the overall structure is a double super, and as shown in Fig. 2, the second local oscillation frequency r2 changes for one value of frequency division ratio N Since two values are taken, the reception frequency rr is the step width of the reference frequency GEo, that is,
It can be changed in steps of 3 kHz in the MW band and 5 kHz in the SW band.

Furthermore, by providing the frequency divider circuit (22), when the frequency division ratio N is changed by 1, the local frequency f1 can be prevented from changing by twice the subfrequency ft). , the reference frequency fo is set to 1/2 of the original frequency, that is, 1.51Jz in the MW band and 2.5k in the SW band)
A method of setting the value to lz may also be considered. However, in this case, the reference frequency fo becomes low and the C/N decreases.In contrast, in this invention, the reference frequency fo is raised to a value equal to the step width of the reception frequency fr. Therefore, a PLL (20) with a good C/N can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of the present invention, and FIG. 2 is a diagram for explaining the same. (20) is PLL, and (30) is Myconi/.

Claims (1)

[Claims] A received signal is supplied to a first mixer circuit, and a first local oscillation signal is supplied to the first mixer circuit so that the received signal has an intermediate frequency higher than the highest frequency of the received signal. is frequency-converted into a first intermediate frequency signal, and this first intermediate frequency signal is supplied to a second mixer circuit, and a second local oscillation signal is supplied to the second mixer circuit, so that the first intermediate frequency signal is In a super receiver in which the frequency is converted into a second intermediate frequency signal, and this second intermediate frequency signal is supplied to a demodulation circuit to demodulate and extract the audio signal, a PLL is provided, and this PLL has a VCO and Between the variable frequency divider circuit,
Another frequency divider circuit is provided, and the oscillation signal of the VCO is supplied to the first mixer circuit as the first local oscillation signal, and while the frequency division ratio of the variable frequency divider 11 is one value, A super receiver configured to change the receiving frequency in frequency steps equal to the reference frequency of the PLL by changing the frequency of the second local oscillation signal in accordance with the frequency division ratio of the another frequency dividing circuit. .