JPH01185936A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01185936A
JPH01185936A JP63009458A JP945888A JPH01185936A JP H01185936 A JPH01185936 A JP H01185936A JP 63009458 A JP63009458 A JP 63009458A JP 945888 A JP945888 A JP 945888A JP H01185936 A JPH01185936 A JP H01185936A
Authority
JP
Japan
Prior art keywords
layer
trench
active region
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63009458A
Other languages
Japanese (ja)
Inventor
Takao Miura
隆雄 三浦
Kazunori Imaoka
今岡　和典
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP63009458A priority Critical patent/JPH01185936A/en
Priority to EP19890100464 priority patent/EP0325161A3/en
Priority to KR8900438A priority patent/KR920003317B1/en
Publication of JPH01185936A publication Critical patent/JPH01185936A/en
Priority to US07/755,596 priority patent/US5148247A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To prevent a leak between adjacent elements, a leak inside an identical element and a narrow channel effect by a method wherein a substrate only on the side which is lower than a device active region to be formed on the upper part at the side face of a trench is made as a high-concentration layer and a fixed charge layer is formed in a part facing the device active region in an insulating film inside the trench. CONSTITUTION:A high-concentration layer 21 is formed only on the side which is lower than a device active region 20 to be formed on the upper part at the side face of a trench 6. A fixed charge layer 12 is formed in an insulating film 7 inside the trench 6 and in a part facing at least the device active region 20. Because the high-concentration layer 21 of, e.g., boron of P<+> is formed at the lower side of the device active region 20, it is possible to prevent a depletion layer from being formed at the interface between a substrate and the insulating film 7 inside the trench. Because the fixed charge layer 12 is formed in the oxide film 7 inside the trench, it prevents that the substrate is depleted; in addition, an impurity inside the high-concentration layer 21 is not spread in the transverse direction. By this setup, it is possible to prevent a leak between adjacent elements, a leak in an identical element and a narrow channel effect.

Description

【発明の詳細な説明】 （概要） トレンチアイソレーション等の素子弁Ｍ　６１　”４を
もつ半導体装置に関し、 隣接素子間リーク、同一素子内リーク、狭チャネル効果
を生じないようにすることを目的とし、トレンチの側面
上部に形成される素子活性領域より下側のみの基板を高
濃度層にすると共に、トレンチ内の絶縁膜中で少なくと
も素子活性領域に対向する部分に固定電荷層を形成した
構成とする。[Detailed Description of the Invention] (Summary) The purpose of this invention is to prevent leakage between adjacent elements, leakage within the same element, and narrow channel effect in a semiconductor device having an element valve M61''4 such as trench isolation. , a structure in which a high concentration layer is formed on the substrate only below the element active region formed on the upper side of the trench, and a fixed charge layer is formed in at least a portion of the insulating film in the trench that faces the element active region. do.

〔産業上の利用分野〕[Industrial application field]

本発明は、トレンチアイソレーション等の素子力ｍ構造
をもつ半導体装置に関する。The present invention relates to a semiconductor device having an element force m structure such as trench isolation.

このような構造の半導体装置では、後述のように、基板
とトレンチ内の酸化膜との界面に空乏層が形成され、こ
の空乏層によって隣接素子間リーク及び同一素子内リー
クを生じる。そこでこの空乏層を形成されないようにす
るために基板にボロン不純物領域を形成するが、このよ
うにすると狭チャネル効果を生じる。In a semiconductor device having such a structure, as will be described later, a depletion layer is formed at the interface between the substrate and the oxide film in the trench, and this depletion layer causes leakage between adjacent elements and leakage within the same element. Therefore, in order to prevent the formation of this depletion layer, a boron impurity region is formed in the substrate, but this causes a narrow channel effect.

そこで、上記隣接素子間リーク、同一素子内リーク、狭
チャネル効果を生じない半導体装置が望まれている。Therefore, a semiconductor device is desired that does not cause the above-mentioned leakage between adjacent elements, leakage within the same element, and narrow channel effect.

〔従来の技術〕[Conventional technology]

例えばトレンチアイソレーション構造では、基板とトレ
ンチ内に形成されｌｃ酸化膜との界面に界面準位ができ
、これによって界面に空乏層が形成され、トランジスタ
の拡散層（Ｎ”　）（ソース及びドレイン）がトレンチ
の両側にある場合は、一方の拡散層のキャリアが空乏層
を介して他方の拡散層にリークしてしまう（これを隣接
素子間リークという）。一方、同一素子内のトレンチの
側壁にも空乏層が形成されているため、ゲートがオフ状
態でも同一素子内でのソース・ドレイン間でリークして
しまう（これを同一素子内リークという）。For example, in a trench isolation structure, an interface state is created at the interface between the substrate and the LC oxide film formed in the trench, and this forms a depletion layer at the interface, which leads to the diffusion layer (N'') of the transistor (source and drain). are on both sides of the trench, carriers in one diffusion layer leak to the other diffusion layer via the depletion layer (this is called leakage between adjacent devices). Since a depletion layer is formed in both, even when the gate is off, leakage occurs between the source and drain within the same element (this is called intra-element leakage).

そこで、このような空乏層が形成されないようにするた
めに、従来、アイソレーション界面にボロン不純物を基
板よりも高濃度に注入する。このようにすれば、空乏層
の形成を防ぐことはできるが、ボロンをドーピングした
後の熱処即工程において、ボロンが基板内に広く拡散さ
れてしまい、いわゆる狭チャネル効果を生じる。このた
めに、トランジスタの電流駆動能力が低下してしまう問
題点があった。Therefore, in order to prevent the formation of such a depletion layer, boron impurities are conventionally implanted into the isolation interface at a higher concentration than the substrate. Although the formation of a depletion layer can be prevented in this way, boron is diffused widely into the substrate in the heat treatment step immediately after doping with boron, resulting in a so-called narrow channel effect. For this reason, there is a problem in that the current driving ability of the transistor is reduced.

本発明は、隣接素子間リーク、同一素子内リーク、狭チ
ャネル効果を生じない半導体装置を提供することを目的
とする。An object of the present invention is to provide a semiconductor device that does not cause leakage between adjacent elements, leakage within the same element, or narrow channel effect.

〔問題点を解決するための手段〕[Means for solving problems]

第１図は本発明の原理図を示す。同図中、２１は高濃度
層で、トレンチ６の側面上部に形成される素子活性領域
２０より下側のみに形成する。FIG. 1 shows a diagram of the principle of the present invention. In the figure, reference numeral 21 denotes a highly doped layer, which is formed only below the element active region 20 formed on the upper side of the trench 6.

１２は固定電荷層で、トレンチ６内の絶縁膜７中で少な
くとも素子活性領域２０に対向する部分に形成してなる
。A fixed charge layer 12 is formed in at least a portion of the insulating film 7 in the trench 6 facing the element active region 20.

〔作用〕[Effect]

素子活性領域２０の下側に例えばＰ＋のボロンの高濃度
層２１を形成しているので、基板とトレンチ内の酸化膜
７との界面に空乏層が形成されるのを防ぎ、これにより
、隣接素子間リークを防止できる。又、トレンチ内の酸
化膜７中に固定電荷［１１２を形成しているので、これ
が基板の空乏化を防ぎ、同一素子内リークを防止でき、
しかも、高ｍ度ＦＩ４２１の不純物が横方向に広がるこ
とはないので狭チャネル効果を防止できる。Since a high concentration layer 21 of, for example, P+ boron is formed below the element active region 20, it is possible to prevent a depletion layer from being formed at the interface between the substrate and the oxide film 7 in the trench. Inter-element leakage can be prevented. Furthermore, since a fixed charge [112] is formed in the oxide film 7 in the trench, this prevents depletion of the substrate and prevents leakage within the same element.
Moreover, since the impurities of the high m degree FI 421 do not spread laterally, the narrow channel effect can be prevented.

（実施例〕 第２図は第１図に示す半導体装ｄを製造する：［程の一
実施例を説明する図である。第２図（Ａ）において、シ
リコン基板１の上に酸化シリコン膜２、窒化シリコン膜
３、ＣＶＤ法による酸化シリコン膜４をこの順に形成し
、更に表面にレジスト膜５を形成する。次に同図（Ｂ）
において、レジスト膜５をマスクとしてエツチングを行
ない、更に、レジスト膜５を除去し、次に同図（Ｃ）に
示す如く、トレンチ６を形成する。(Example) FIG. 2 is a diagram illustrating an example of manufacturing the semiconductor device d shown in FIG. 1. In FIG. 2. A silicon nitride film 3 and a silicon oxide film 4 are formed in this order by the CVD method, and a resist film 5 is further formed on the surface.Next, the same figure (B)
In this step, etching is performed using the resist film 5 as a mask, and then the resist film 5 is removed, and then a trench 6 is formed as shown in FIG.

次に、ＣｖＤ−・酸化シリコン膜４を除去し、同図（Ｄ
）において、トレンチ６内に酸化膜７（５００人〜１０
００人）を形成し、次に、アルミニウム水溶液に浸すこ
とによって表面にアルミニウム分子膜８を形成する。次
に、同図（Ｅ）において、後で形成されるソース、ドレ
インのＮ＋拡散層９１、９２（トレンチの側面上部に形
成される素子活性領域）より下側で、トレンチ６内に６
００℃の温度でポリ・ボロン・フィルム１０を充填する
。Next, the CvD- silicon oxide film 4 is removed and the same figure (D
), an oxide film 7 (500 to 10
00 persons) is formed, and then an aluminum molecular film 8 is formed on the surface by immersing it in an aluminum aqueous solution. Next, in FIG. 6(E), a 6-layer structure is formed in the trench 6 below the source and drain N+ diffusion layers 91 and 92 (device active regions formed on the upper side surfaces of the trench), which will be formed later.
The poly boron film 10 is filled at a temperature of 00°C.

次に同図（Ｆ）において、７００℃の温度でトレンチ６
内にポリ・シリコン層１１を埋込み形成する。このとき
、アルミニウム分子膜８からアルミニウムが酸化膜７に
拡散されてここに負電荷１２（θで示す）が形成される
一方、ポリ・ボロン・フィルム１０中のボロンが基板１
へ拡散され、Ｐ＋の不純物層１３が形成される。更に、
表面の窒化シリコン膜３を除去する。Next, in the same figure (F), the trench 6 is heated at a temperature of 700°C.
A polysilicon layer 11 is embedded therein. At this time, aluminum is diffused from the aluminum molecular film 8 into the oxide film 7 and a negative charge 12 (indicated by θ) is formed there, while boron in the poly-boron film 10 is diffused into the oxide film 7.
A P+ impurity layer 13 is formed. Furthermore,
The silicon nitride film 3 on the surface is removed.

なお、負電荷１２を形成する方法としては、上記の伯、
アルミニウムをイオン注入したり、アルミニウム薄膜を
形成して拡散したり、膜自身で負電荷をもつ膜を成長さ
せるようにしてもよい。In addition, as a method of forming the negative charge 12, the above-mentioned method,
It is also possible to ion-implant aluminum, form a thin aluminum film and diffuse it, or grow a film that itself has a negative charge.

このように、本発明は、トレンチ内の素子活性領域の下
側にボロン不純物層１３を形成したため、前述した隣接
素子間リークを防止でき、一方、本発明は、酸化膜７の
中に負電荷１２を形成したため、基板１側には正゛占荷
が誘起されることになり、前述した同一素子内リークを
防止でき、又、不純物が横方向に広がることはないので
秋チャネル効果を防止できる。従来の場合のゲート電圧
対リーク電流特性は例えば第３図（△）に示ず如くであ
り、リーク電流は比較的高くばらついているが、本発明
の場合は同図（［３）に示寸如くであり、リーク電流は
低く抑えられていることがわかる。As described above, in the present invention, since the boron impurity layer 13 is formed under the element active region in the trench, the above-mentioned leakage between adjacent elements can be prevented. 12, positive loading is induced on the substrate 1 side, which prevents the leak within the same element as described above, and also prevents the fall channel effect since impurities do not spread laterally. . The gate voltage vs. leakage current characteristic in the conventional case is as shown in Figure 3 (△), for example, and the leakage current varies relatively high, but in the case of the present invention, the characteristics are as shown in Figure 3 ([3]). It can be seen that the leakage current is suppressed to a low level.

第４図は本発明装置を製造する工程の他の実施例を説明
する図である。このものは第４図＜Ａ）に至る工程まで
は第２図（Ａ）〜（Ｃ）までの工程を用いる。第４図（
Ａ）において、１〜レンチ内に酸化膜７を形成し、次に
、同図（Ｂ）において表面に窒化シリコン膜３２を形成
する。次に、同図（Ｃ）において、窒化シリコン膜３２
を異方性エツチングしてトレンチ６内の窒化シリコン膜
３２を除去し、更に、拡散ｍ９１、９２より下側で、ト
レンチ６内にＣ１０法（Ｃｈｅｍｉｃａｌ　Ｌｉｑｕｉ
ｄＤｅｐｏｓｉｔｉｏｎ、化学液相成長法）にてＳＯＧ
　（スピン・オン・グラス）層１５を充填する。FIG. 4 is a diagram illustrating another embodiment of the process for manufacturing the device of the present invention. This product uses the steps shown in FIGS. 2(A) to 2(C) up to the step leading to FIG. 4<A). Figure 4 (
In A), an oxide film 7 is formed in the trenches 1 to 1, and then a silicon nitride film 32 is formed on the surface in FIG. 1B. Next, in the same figure (C), the silicon nitride film 32
The silicon nitride film 32 in the trench 6 is removed by anisotropic etching, and the C10 method (Chemical Liquid
SOG using dDeposition, chemical liquid phase growth method)
(Spin-on-glass) layer 15 is filled.

次に、同図（Ｄ）において、表面に窒化シリコン膜３３
を形成し、更に、同図（Ｅ）において、窒化シリコン膜
３３を異方性エツチングし、又、ＳＯＧ層１５を除去す
る。このとき、底部の酸化膜７も除去される。次に、回
転イオン注入法でボロンを基板１に注入してＰ＋の不純
物層１３を形成するが、トレンチ内には上側が２つの窒
化シリコン膜３２．３３からなる厚い層、下側が窒化シ
リコン膜３２のみからなる薄い層であるので、ボロンは
■側の窒化シリコン膜３２を介して下側のみに注入され
、上側には注入されない。Next, in the same figure (D), a silicon nitride film 33 is formed on the surface.
Further, as shown in FIG. 3E, the silicon nitride film 33 is anisotropically etched and the SOG layer 15 is removed. At this time, the oxide film 7 on the bottom is also removed. Next, boron is implanted into the substrate 1 using a rotational ion implantation method to form a P+ impurity layer 13. Inside the trench, there is a thick layer consisting of two silicon nitride films 32 and 33 on the upper side and a silicon nitride film on the lower side. Since it is a thin layer consisting only of 32, boron is implanted only into the lower side through the silicon nitride film 32 on the side 3, and is not implanted into the upper side.

次に、窒化シリコン膜３＋　、３２．３３を除去し、表
面にアルミニウム分子膜を形成し、熱処理を行なう。こ
れにより、同図（Ｆ）において、酸化膜７に負電荷１２
が形成される。次に、トレンチ内にポリ・シリコン層１
１を形成する。Next, the silicon nitride films 3+, 32 and 33 are removed, an aluminum molecule film is formed on the surface, and heat treatment is performed. As a result, in the same figure (F), the oxide film 7 has a negative charge of 12
is formed. Next, a polysilicon layer 1 is placed inside the trench.
form 1.

このものは、イオン注入で不純物層１３を形成している
ので、第２図に示す熱処理による場合よりら深さやドー
ピング酒を高粘度に制御できる。In this case, since the impurity layer 13 is formed by ion implantation, the depth and doping liquid can be controlled to a higher viscosity than in the case of the heat treatment shown in FIG.

その他の効果は第２図に示すものと同様である。Other effects are similar to those shown in FIG.

第５図は本発明装置を製造する工程の更に他の実施例を
説明する図である。このものは第５図（Ａ）に至る工程
までは第４図（Ｂ）までの工程を用いる。第５図（Ａ＞
において、ＳＯＧ膜１５を充填した後、酸化シリコンＭ
　４２をＣＶＤ法で形成し、更に、窒化シリコン膜３３
を形成する。FIG. 5 is a diagram illustrating still another embodiment of the process for manufacturing the device of the present invention. This product uses the steps up to FIG. 4(B) up to the step up to FIG. 5(A). Figure 5 (A>
After filling the SOG film 15, silicon oxide M
42 is formed by the CVD method, and a silicon nitride film 33 is further formed.
form.

次に、同図（Ｂ）において、窒化シリコン膜３３を異方
性エツチングし、次に、同図（Ｃ）において、酸化シリ
コンｌｌｌ３４２を全面エツチングし、残った窒化シリ
コンＰＡ３３をマスクとしてｓｏＧ膜１５を除去する。Next, the silicon nitride film 33 is anisotropically etched as shown in FIG. remove.

次に、窒化シリコン膜を全面エツチングすると、窒化シ
リコン膜３３及び酸化シリコン膜４２をマスクとして下
部の窒化シリコン膜３２も同時に除去されて同図（Ｄ）
となる。次に、酸化シリコン膜４２．４＋及び下部の酸
化Ｗｉ７を除去して同図（Ｅ）とする。次に、同図（Ｅ
）において、ガス拡散又は固相拡散により、ボロンの不
純物層１３を形成する。ガス拡散では、三塩化ボロン（
ＢＣＣ１０液体を用い、２Ｂ（、Ｉｌｓ→２Ｂ＋３Ｃ２
ｚの化学反応でボロン（Ｂ）の不純物層１３を形成し、
固相拡散では、窒化ボロン（ＢＮ）の固体を用い、２８
Ｎ→２Ｂ＋Ｎ２の化学反応でボロン（Ｂ）の不純物層１
３を形成する。次に、窒化シリコン膜３＋　、３２を除
去し、同図（Ｆ）に示す如く酸化Ｍｌ　７に負電荷１２
を形成し、ポリ・シリコン層１１を形成する。Next, when the entire surface of the silicon nitride film is etched, the lower silicon nitride film 32 is also removed at the same time using the silicon nitride film 33 and silicon oxide film 42 as a mask, as shown in FIG.
becomes. Next, the silicon oxide film 42.4+ and the oxidized Wi7 at the bottom are removed to form the same figure (E). Next, the same figure (E
), a boron impurity layer 13 is formed by gas diffusion or solid phase diffusion. In gas diffusion, boron trichloride (
Using BCC10 liquid, 2B(, Ils→2B+3C2
A boron (B) impurity layer 13 is formed by a chemical reaction of z,
In solid phase diffusion, solid boron nitride (BN) is used, and 28
Boron (B) impurity layer 1 is formed by the chemical reaction of N→2B+N2
form 3. Next, the silicon nitride films 3+ and 32 are removed, and as shown in FIG.
A polysilicon layer 11 is formed.

なお、上記各実施例は負電荷１２を酸化膜７の全面（ト
レンチの側面及び底面）に形成した構成であるが、これ
に限定されるものではなく、第６図に示す如く、酸化膜
７の上部（トレンチの上部）のみに形成するようにして
もよい。この場合、アルミニウムをイオン注入する方法
を用い、その注入角度を所定角度つけることによりトレ
ンチの上部のみに形成する。Although each of the above embodiments has a configuration in which the negative charges 12 are formed on the entire surface of the oxide film 7 (the side surfaces and the bottom surface of the trench), the present invention is not limited to this, and as shown in FIG. It may be formed only on the upper part of the trench (the upper part of the trench). In this case, a method of implanting aluminum ions is used, and the implantation angle is set at a predetermined angle, so that the trench is formed only in the upper part.

例えば、同図（Ａ）において、後で拡散１９１。For example, in the same figure (A), diffusion 191 is performed later.

９２を形成する際に同時に形成される空乏Ｈ１６，。Depletion H16, which is formed simultaneously when forming 92.

１６２の下端より下方までのみ負電荷１２を形成し、か
つ、不純物層１３を空乏層１６１．１６２の下端に接し
ないように形成する。この場合、不純物層１３が空乏層
１６１．１６２に接していないのでＰＮ接合の耐圧を大
きくとり得、このように高耐圧を必要とする装置に最適
である。一方、同図（Ｂ）において、同図（Ａ）と同様
に空乏層１６１．１６２の下端より下方までのみ負を荷
１２を形成し、かつ、不純物層１３を空乏層１６１゜１
６２の下端より上方で拡散層９１、９２の下端より下方
に形成する。この場合、不純物ｌＡ１３が空乏Ｊｉ１１
６１、１６２に接しているのでＰＮ接合の耐圧は低く、
このように高耐圧を必要としない装置に最適である。The negative charges 12 are formed only below the lower ends of the depletion layers 161 and 162, and the impurity layer 13 is formed so as not to contact the lower ends of the depletion layers 161 and 162. In this case, since the impurity layer 13 is not in contact with the depletion layers 161 and 162, the breakdown voltage of the PN junction can be increased, which is optimal for devices that require such a high breakdown voltage. On the other hand, in the same figure (B), similarly to the same figure (A), the negative load 12 is formed only from the lower end of the depletion layer 161.162, and the impurity layer 13 is
It is formed above the lower ends of the diffusion layers 91 and 92 and below the lower ends of the diffusion layers 91 and 92. In this case, impurity lA13 is depleted Ji11
Since it is in contact with 61 and 162, the withstand voltage of the PN junction is low.
In this way, it is ideal for devices that do not require high withstand voltage.

同図（Ｃ）は、拡散層９１　、９２の下端と不純物層１
３が接している例を示す。この場合は、接合耐圧はより
低くなるが、接合リーク電流低減の効果は、同図（Ａ）
および（Ｂ）の場合と同様、著しいものがある。The same figure (C) shows the lower ends of the diffusion layers 91 and 92 and the impurity layer 1.
An example where 3 are in contact is shown. In this case, the junction breakdown voltage will be lower, but the effect of reducing the junction leakage current will be as shown in the same figure (A).
As in the case of (B) and (B), there are significant cases.

又、上記各実施例は特にエピタキシャル層を用いた構成
ではないが、本発明は第７図に示すような高濃度基板１
７の上に低濃度エピタキシャル層１８を形成した構成の
ものにも適用できる。第７図（Ａ）において、高濃度基
板１７の上に低濃度エピタキシャル層１８を形成し、高
ｍ度基板１７まで形成したトレンチの側壁及び底部の酸
化１１７に負電荷１２を形成する。一方、同図（ｂ）に
おいて、同図（Ａ）に示す基板１７、エピタキシャル層
１８の構成で、負電荷１２を少なくともＮ＋拡散層１９
１　、１９２の下端まで形成する。Further, although each of the above embodiments does not particularly use a structure using an epitaxial layer, the present invention is applicable to a highly concentrated substrate 1 as shown in FIG.
It can also be applied to a configuration in which a low concentration epitaxial layer 18 is formed on top of the epitaxial layer 7 . In FIG. 7A, a low concentration epitaxial layer 18 is formed on a high concentration substrate 17, and negative charges 12 are formed on the oxide 117 on the side walls and bottom of the trench formed up to the high concentration substrate 17. On the other hand, in the same figure (b), with the structure of the substrate 17 and the epitaxial layer 18 shown in the same figure (A), the negative charges 12 are at least transferred to the N+ diffusion layer 19.
1, 192 to the lower end.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明によれば、素子活性領域の下
側に例えばＰ＋のボロンの高濃度層を形成しているので
、基板とトレンチ内の酸化膜との界面に空乏層が形成さ
れるのを防ぎ、これにより、隣接素子間リークを防止で
き、又、トレンチ内の酸化膜中に固定電荷を形成してい
るので、これが同一素子内リークを防止でき、しかも、
高ａｔａｍ２１の不純物が横方向に広がることはないの
で狭ヂャネル効果を防止できる。As explained above, according to the present invention, since a high concentration layer of, for example, P+ boron is formed below the element active region, a depletion layer is formed at the interface between the substrate and the oxide film in the trench. This prevents leakage between adjacent elements, and since fixed charges are formed in the oxide film within the trench, this prevents leakage within the same element.
Since impurities with high atam21 do not spread laterally, narrow channel effects can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の原理図、 第２図は本発明装置の￥！Ｊ造工稈の一実施例の図、第
３図は従来例及び本発明のゲート電圧対リーク電流特性
図、 第４図は本発明装置の製造工程の他の実施例の図、 第５図は本発明装置の製造工程の更に他の実施例の図、 第６図は本発明において負電荷をトレンチ上部のみに形
成づる実施例の図、 第７図は低濃度エピタキシャル層を用いた実施例の図で
ある。 図において、 １は基板、 ３．３＋　、３２．３３は窒化シリコン膜、４．４＋　
、４２は酸化シリコン膜、 ６はトレンチ、 ７は酸化膜、 ８はアルミニウム分子膜、 ９１．９２．１９１，１９２．２０は素子活性領域、 １０はポリ・ボロン・フィルム、 １１はポリ・シリコン層、 １２は負電荷（固定電荷層）、 １３はボロン不純物層、 １５はＳＯＧ膜、 １６１、１６２は空乏層、 １７は高濃度基板、 １８は低濃度エピタキシャル層、 ２１は高濃度層 を示す。 ビ 本袴明の厘理目 烙１図 外＞ｅＥ（Ｖ）→　　　　　　　　＋−−シ五（Ｖ）→
才ミ」特グ］Ｘｎオ崎をｙｌのゲー戸殴耳りナリニ７酸
月に外陰ｂ１第３図 第２図 １Ｉ４図 第Ｓ図Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a diagram of the device of the present invention! A diagram of one embodiment of J artificial culm, FIG. 3 is a gate voltage vs. leakage current characteristic diagram of the conventional example and the present invention, FIG. 4 is a diagram of another embodiment of the manufacturing process of the device of the present invention, and FIG. 5 6 is a diagram of still another embodiment of the manufacturing process of the device of the present invention, FIG. 6 is a diagram of an embodiment in which negative charges are formed only in the upper part of the trench in the present invention, and FIG. 7 is an embodiment using a low concentration epitaxial layer. This is a diagram. In the figure, 1 is the substrate, 3.3+, 32.33 is the silicon nitride film, 4.4+
, 42 is a silicon oxide film, 6 is a trench, 7 is an oxide film, 8 is an aluminum molecule film, 91.92.191, 192.20 are element active regions, 10 is a poly-boron film, 11 is a poly-silicon layer , 12 is a negative charge (fixed charge layer), 13 is a boron impurity layer, 15 is an SOG film, 161 and 162 are depletion layers, 17 is a high concentration substrate, 18 is a low concentration epitaxial layer, and 21 is a high concentration layer. Bihon Hakama Akira's Rimoku 1 outside the diagram > eE (V) → +-- Shigo (V) →
[Special] Xn Osaki, yl's game door, listen to Nalini 7 acid moon, vulva b1 Fig. 3 Fig. 2 Fig. 1 I 4 Fig. S Fig.

Claims (5)

【特許請求の範囲】[Claims] （１）トレンチアイソレーシヨンの素子分離構造をもつ
半導体装置において、 トレンチ（６）の側面上部に形成される素子活性領域（
２０）より下側のみの基板を高濃度層（２１）にすると
共に、 該トレンチ（６）内の絶縁膜（７）中で少なくとも上記
素子活性領域（２０）に対向する部分に固定電荷層（１
２）を形成してなることを特徴とする半導体装置。(1) In a semiconductor device with a trench isolation element isolation structure, an element active region (
20), a high concentration layer (21) is formed on only the lower side of the substrate, and a fixed charge layer (21) is formed on at least a portion of the insulating film (7) in the trench (6) facing the element active region (20). 1
2) A semiconductor device comprising: （２）該高濃度前（１３）は、その上端が該素子活性領
域（９＿１、９＿２）形成によって形成される空乏層（
１６＿１、１６＿２）下端より下方に形成してなること
を特徴とする請求項１記載の半導体装置。(2) Before the high concentration (13), the upper end thereof is a depletion layer (
16_1, 16_2) The semiconductor device according to claim 1, wherein the semiconductor device is formed below the lower end. （３）該高濃度層（１３）は、その上端が該素子活性領
域（９＿１、９＿２）形成によって形成される空乏層（
１６＿１、１６＿２）下端より上方で、かつ、該素子活
性領域（９＿１、９＿２）下端より下方に形成してなる
ことを特徴とする請求項１記載の半導体装置。(3) The upper end of the high concentration layer (13) is a depletion layer (
2. The semiconductor device according to claim 1, wherein the device active regions (9_1, 9_2) are formed above the lower ends thereof and below the lower ends of the element active regions (9_1, 9_2). （４）該高濃度層（１３）は、その上端が該素子活性領
域（９＿１、９＿２）に接するように成ることを特徴と
する請求項２記載の半導体装置。(4) The semiconductor device according to claim 2, wherein the high concentration layer (13) has its upper end in contact with the element active region (9_1, 9_2). （５）該空間電荷層（１２）は、該素子活性領域（９＿
１、９＿２）及び該空乏層（１６＿１、１６＿２）の両
方に対向する部分に形成してなることを特徴とする請求
項２又は３もしくは４記載の半導体装置。(5) The space charge layer (12) is connected to the device active region (9_
5. The semiconductor device according to claim 2, wherein the semiconductor device is formed in a portion facing both the depletion layer (16_1, 16_2) and the depletion layer (16_1, 16_2).
JP63009458A 1988-01-21 1988-01-21 Semiconductor device Pending JPH01185936A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP63009458A JPH01185936A (en) 1988-01-21 1988-01-21 Semiconductor device
EP19890100464 EP0325161A3 (en) 1988-01-21 1989-01-13 Semiconductor device having trench isolation
KR8900438A KR920003317B1 (en) 1988-01-21 1989-01-17 Semiconductor device having trench isolation structure
US07/755,596 US5148247A (en) 1988-01-21 1991-09-05 Semiconductor device having trench isolation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63009458A JPH01185936A (en) 1988-01-21 1988-01-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01185936A true JPH01185936A (en) 1989-07-25

Family

ID=11720843

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Application Number Title Priority Date Filing Date
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Country Link
US (1) US5148247A (en)
EP (1) EP0325161A3 (en)
JP (1) JPH01185936A (en)
KR (1) KR920003317B1 (en)

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US5148247A (en) 1992-09-15
EP0325161A3 (en) 1990-09-05
KR890012390A (en) 1989-08-26
EP0325161A2 (en) 1989-07-26
KR920003317B1 (en) 1992-04-27

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