JPH01185176A - Processing method using electrostatic adsorption - Google Patents
Processing method using electrostatic adsorptionInfo
- Publication number
- JPH01185176A JPH01185176A JP63006767A JP676788A JPH01185176A JP H01185176 A JPH01185176 A JP H01185176A JP 63006767 A JP63006767 A JP 63006767A JP 676788 A JP676788 A JP 676788A JP H01185176 A JPH01185176 A JP H01185176A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- electrostatic chuck
- temperature
- chuck
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003672 processing method Methods 0.000 title claims description 9
- 238000001179 sorption measurement Methods 0.000 title claims description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000004380 ashing Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- 230000035939 shock Effects 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 29
- 239000000919 ceramic Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- -1 etc.) Polymers 0.000 description 1
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
PURPOSE:To alleviate a thermal shock by controlling temperatures of both a semiconductor substrate and an electrostatic chuck so that said temperatures are approximately equal, before adsorbing said base on said chuck. CONSTITUTION:This method applies an electrostatic chuck 8 to a down flow ashing apparatus. When the down flow ashing of a resist is conducted, the temperature of a wafer 1 is required to be about 150-300 deg.C. Then, before said wafer 1 is adsorbed on an electrostatic chuck 8, the wafer 1 is heated or cooled beforehand so that temperatures of both said chuck and wafer are approximately equal. Thus, it becomes possible to conduct processing by the use of said electrostatic chuck 8 even if a temperature change is large.
Description
【発明の詳細な説明】
〔概 要〕
本発明は静電吸着を用いた処理方法に係り、特に半導体
ウェハ温度制御を静電吸着を用いて行なう方法に関し、
高温、例えば２００〜３００°Ｃ程度の温度で静電チャ
ックを用いてもチャックの絶縁物が割れない処理方法を
提供することを目的とし、
真空中で静電チャックにより半導体基板を静電吸着する
処理方法において、前記静電チャックに前記半導体基板
を吸着させる前に、あらかじめ該半導体基板を加熱ある
いは冷却し、該半導体基板と静電チャックの温度差を小
さ（することを構成とする。Detailed Description of the Invention [Summary] The present invention relates to a processing method using electrostatic adsorption, and in particular to a method of controlling the temperature of a semiconductor wafer using electrostatic adsorption. The purpose of the present invention is to provide a processing method in which the insulator of the chuck does not crack even when an electrostatic chuck is used at a temperature of Before the semiconductor substrate is attracted, the semiconductor substrate is heated or cooled in advance to reduce the temperature difference between the semiconductor substrate and the electrostatic chuck.
本発明は静電吸着を用いた処理方法に係り、特に半導体
ウェハ温度制御を静電吸着を用いて行なう方法に関する
。The present invention relates to a processing method using electrostatic chucking, and more particularly to a method of controlling the temperature of a semiconductor wafer using electrostatic chucking.
半導体製造プロセスでは真空装置が多用されているが、
この際真空中で半導体素子基板（以下ウェハと記す）を
吸着保持できる静電チャックがゴミ対策等のために垂直
又は下向に保持したり、電子ビーム（ＥＢ）、Ｘ線露光
のためウェハの固定、平坦化したり、またエツチング、
デポジションのためのウェハの温度制御等積々の用途に
用いられている（特公昭５７−４４７４７号公報）。Vacuum equipment is often used in the semiconductor manufacturing process, but
At this time, an electrostatic chuck that can hold the semiconductor element substrate (hereinafter referred to as wafer) in a vacuum is used to hold the wafer vertically or downwardly to prevent dust, etc., or to hold the wafer vertically or downwardly for electron beam (EB) or X-ray exposure. Fixing, flattening or etching,
It is used for many purposes such as temperature control of wafers for deposition (Japanese Patent Publication No. 44747/1983).
静電チャックは２図及び３図に示すように絶縁物２中に
単数又は複数の電極３を埋め込み電極３と試料（ウェハ
）■又は電極間に直流電圧を印加し、試料と電極間に働
くクーロン力により試料１を吸着するものである。As shown in Figures 2 and 3, an electrostatic chuck embeds one or more electrodes 3 in an insulator 2 and applies a DC voltage between the electrodes 3 and a sample (wafer) or electrodes to act between the sample and the electrodes. The sample 1 is adsorbed by Coulomb force.
静電チャックに使用する絶縁物２として第４図に示した
テフロン、ポリイミド（商品名カプトン等）シリコーン
等の樹脂２ａを用いたもの（例えば特開昭５９−６４２
４５号公報）は安価で、製造が容易、しかも軟かいので
ウェハとの密着性が良好で、また温度制御性が良い等の
メリットはあるが摩耗のために寿命が短かく耐熱性の問
題から１５０°Ｃ以上の高温で使用することができない
。これに対して第５図に示すように絶縁物にセラミック
２ｂを用いたもの（例えば特公昭６０−５９１０４号公
報、特開昭６０−２６１３７７号公報）は固く摩滅しに
くく高温でも使用できるというメリットがあるがセラミ
ックは割れやすく、熱衝撃に弱いという問題があった。As the insulator 2 used in the electrostatic chuck, a resin 2a such as Teflon, polyimide (product name: Kapton, etc.), silicone, etc. shown in FIG.
No. 45) is inexpensive, easy to manufacture, and has advantages such as good adhesion to the wafer because it is soft and good temperature control, but has short lifespan due to wear and problems with heat resistance. It cannot be used at high temperatures above 150°C. On the other hand, as shown in Fig. 5, insulators using ceramic 2b (for example, Japanese Patent Publication No. 60-59104, Japanese Patent Application Laid-Open No. 60-261377) have the advantage of being hard and resistant to wear and can be used even at high temperatures. However, ceramics have the problem of being easily broken and susceptible to thermal shock.
特にチャックと著しく温度が異なる試料を吸着させた時
にセラミックにクラックが入りやすいことは高温で静電
チャックを用いる場合の問題であった。In particular, when using an electrostatic chuck at high temperatures, the ceramic tends to crack easily when adsorbing a sample whose temperature is significantly different from that of the chuck.
本発明は高温、例えば２００〜３００°Ｃ程度の温度で
静電チャックを用いても割れない処理方法を提供するこ
とを目的とする。An object of the present invention is to provide a processing method that does not cause cracking even when an electrostatic chuck is used at a high temperature, for example, about 200 to 300°C.
上記課題は本発明によれば真空中で静電チャックを利用
して半導体基板を静電吸着する処理方法において、前記
静電チャックに前記半導体基板を吸着させる前に予め該
半導体基板を加熱あるいは冷却させ該半導体基板と静電
チャックと同程度の温度にしておくことを特徴とする静
電吸着を用いた処理方法によって解決される。特に真空
中では対流がなく、又空気等のガスによる熱伝導がない
ので、試料の温度変化が大気中より少なく上記の加熱又
は冷却操作、を別の場所で行ってから試料を静電チャッ
クまで搬送してよい。According to the present invention, the above-mentioned problem is solved in a processing method of electrostatically adsorbing a semiconductor substrate using an electrostatic chuck in a vacuum, in which the semiconductor substrate is heated or cooled in advance before the semiconductor substrate is adsorbed to the electrostatic chuck. This problem can be solved by a processing method using electrostatic adsorption, which is characterized by keeping the semiconductor substrate and the electrostatic chuck at about the same temperature. In particular, in a vacuum, there is no convection, and there is no heat conduction by gases such as air, so the temperature change of the sample is less than in the atmosphere, so the above heating or cooling operation is performed in another location, and then the sample is placed on the electrostatic chuck. May be transported.
〔作 用］
本発明によれば半導体基板を静電チャックする前に温度
を制御しているので熱衝撃を緩和することができる。[Function] According to the present invention, since the temperature is controlled before electrostatically chucking the semiconductor substrate, thermal shock can be alleviated.
アルミナセラミックを用いた静電チャックで試料と静電
チャックの温度差が１００°Ｃ以下であればセラミック
のクラックは発生しなかった。したがって静電チャック
の寿命を長くすることができた。In an electrostatic chuck using alumina ceramic, no cracks occurred in the ceramic if the temperature difference between the sample and the electrostatic chuck was 100°C or less. Therefore, the life of the electrostatic chuck could be extended.
以下本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１図は本発明の方法を実施するダウンフローアッシン
グ装置の概略図である。FIG. 1 is a schematic diagram of a downflow ashing apparatus implementing the method of the present invention.
第１図に示したダウンフロー（ダウンストリーム又はア
フターグロー）アッシング装置に静電チャックを適用し
た。ダウンフローエツチングによりＳｉＯ□やＰＳＧ等
エツチングを行なう場合や０２＋Ｎ２ （又はＮ、０．
Ｈ，等）のハロゲンを含まないガスでレジストのダウン
フローアッシングを行なう場合はウェハを１５０〜３０
０°Ｃ程度の温度にする必要がある。従来はウェハと加
熱ステージ上に平置きして処理を行うがウェハの温度制
御が悪く又ゴミの影響を受けやすい。ウェハを下向きに
し、ステージに下から機械的に押付けてもよいが、押付
けのためウェハ表面の一部がおおわれ、その部分が処理
されなくなる。したがって、静電チャックを用いるのが
理想的であるが前記熱衝撃の問題があった。An electrostatic chuck was applied to the downflow (downstream or afterglow) ashing device shown in FIG. When etching SiO□, PSG, etc. by down flow etching, or when etching 02+N2 (or N, 0.
When performing downflow ashing of the resist with a halogen-free gas such as H, etc., the wafer is
The temperature needs to be around 0°C. Conventionally, processing is performed by placing the wafer flat on a heating stage, but the temperature of the wafer is poorly controlled and is easily affected by dust. Although the wafer may be turned downward and mechanically pressed against the stage from below, a portion of the wafer surface will be covered due to the pressing, and that portion will not be processed. Therefore, although it would be ideal to use an electrostatic chuck, there is the problem of thermal shock.
以下本実施例を工程順に説明する。This example will be explained below in the order of steps.
■ まず第１図に示したダウンフローアッシング装置で
真空ロードロツタ（図示せず）を通じて膜厚１μのレジ
ストのついたウェハ１を搬送室４の搬送アーム５上に、
表側を下向きにしてのせる（この機械は図示していない
）。■ First, using the down flow ashing device shown in FIG. 1, the wafer 1 with a resist film of 1 μm in thickness is placed on the transfer arm 5 of the transfer chamber 4 through a vacuum load rotor (not shown).
Place it face down (this machine is not shown).
■ 搬送アーム５を予備加熱ステージ６の下に動かし該
ステージ６を下げてウェ、ハ１の裏面に接触させ３０秒
間ウェハ１を加熱する。予備加熱ステージ６は約２７０
°Ｃに加熱しておいた。(2) Move the transfer arm 5 below the preheating stage 6, lower the stage 6, bring it into contact with the back surface of the wafer 1, and heat the wafer 1 for 30 seconds. Preheating stage 6 is approximately 270
It had been heated to °C.
■ 次に予備加熱ステージ６を上げ搬送アーム５を反応
室ステージ７の下に動かし該ステージ７を下げて静電チ
ャック８に電圧を印加しウェハ１を吸着させる。反応室
ステージ７は２５０°Ｃに加熱されている。(2) Next, the preheating stage 6 is raised, the transfer arm 5 is moved below the reaction chamber stage 7, the stage 7 is lowered, and a voltage is applied to the electrostatic chuck 8 to attract the wafer 1. Reaction chamber stage 7 is heated to 250°C.
■ 反応室ステージ７とヒゲアームを別位置に動かした
後、ステージ７を下げ、反応室１４と搬送室４とを分離
させた後、ガス９（ここでは０２＋Ｎ２）を流しマグネ
トロン１０を発振させてμ波を発生し、プラズマ室１１
にプラズマを作る。■ After moving the reaction chamber stage 7 and the whisker arm to different positions, lowering the stage 7 and separating the reaction chamber 14 and the transfer chamber 4, the gas 9 (02+N2 in this case) is flowed and the magnetron 10 is oscillated to generate μ. Generate waves and plasma chamber 11
to create plasma.
するとプラズマ室１１でつくられた活性種１３（０原子
と思われる）がウェハ１上に輸送され、ウェハ上のレジ
ストと反応し、レジストを除去する０反応時間は１分で
ある。Then, the active species 13 (supposed to be 0 atoms) created in the plasma chamber 11 are transported onto the wafer 1, react with the resist on the wafer, and the 0 reaction time for removing the resist is 1 minute.
■ 反応終了後ステージ７を上げアームをウェハの下に
動かし静電チャック８の電圧を切ってウェハをアーム上
に移す。(2) After the reaction is completed, raise the stage 7 and move the arm below the wafer, turn off the voltage on the electrostatic chuck 8, and transfer the wafer onto the arm.
■ アーム上のウェハを真空ロードロックを通じて外部
へ搬送する。■ Transfer the wafer on the arm to the outside through the vacuum load lock.
このようにして得られた処理において静電チャックのセ
ラミックにはクランクは発生していなかった。第１図で
１２はヒータ、１５は導波管である。In the treatment thus obtained, no cranking occurred in the ceramic of the electrostatic chuck. In FIG. 1, 12 is a heater and 15 is a waveguide.
なお上記の実施例でそれぞれのステージとウェハの間に
Ｈｏ等のガスを圧力１０Ｔｏｎ程度導入しウェハとステ
ージ間の熱伝導を良くするといっそう温度制御性がよく
、予備加熱時間も１０秒以下にすることができる。なお
この実施例ではウェハを加熱する場合であるが、冷却す
る場合でも、特に連結した反応室で続々処理をしていく
場合、前の反応室と温度が異なっている場合には本方法
でウェハ温度を静電チャックステージに合わせるのが有
効である。In the above example, if a gas such as Ho is introduced between each stage and the wafer at a pressure of about 10 tons to improve heat conduction between the wafer and the stage, temperature controllability will be even better, and the preheating time will also be less than 10 seconds. be able to. Although this example deals with heating the wafer, this method can also be used to cool the wafer, especially when processing is performed one after another in connected reaction chambers, or when the temperature is different from the previous reaction chamber. It is effective to match the temperature to the electrostatic chuck stage.
又反応室は他にもＲＩＥやＲＩＰＥ 、又プラズマＣＶ
Ｄ等ウェハ温度の精密制御が必要な場合にはすべてこの
方法が有効である。In addition, the reaction chamber can also be used for RIE, RIPE, and plasma CV.
This method is effective in all cases where precise control of wafer temperature is required, such as in D.
以上説明したように本発明によれば温度変化の大きい場
合でも静電チャックを用いて処理することが可能となる
。又ウェハを下向きに保持できるので、ゴミの付着が少
なく歩留りが向上する。As explained above, according to the present invention, it is possible to perform processing using an electrostatic chuck even when there is a large temperature change. Furthermore, since the wafer can be held downward, there is less dust adhesion and the yield is improved.
第１図は本発明の方法を実施するダウンフローアッシン
グ装置の概略図であり、第２図がら第５図迄は従来の技
術を説明するための静電チャックの図である。
１・・・ウェハ、 ２・・・絶縁物、３・・
・電極、 ４・・・搬送室、５・・・搬送ア
ーム、 、６・・・予備加熱アーム、７・・・反応
室ステージ、 ８・・・静電チャック、９・・・ガス
、 １０・・・マグネトロン、１１・・・プ
ラズマ室、 １２・・・ヒータ、１４・・・反応室
、 １５・・・導波管。FIG. 1 is a schematic diagram of a downflow ashing apparatus that implements the method of the present invention, and FIGS. 2 to 5 are diagrams of an electrostatic chuck for explaining the conventional technology. 1... Wafer, 2... Insulator, 3...
- Electrode, 4... Transfer chamber, 5... Transfer arm, , 6... Preheating arm, 7... Reaction chamber stage, 8... Electrostatic chuck, 9... Gas, 10. ... Magnetron, 11... Plasma chamber, 12... Heater, 14... Reaction chamber, 15... Waveguide.
Claims (1)
する処理方法において、前記静電チャックに前記半導体
基板を吸着させる前に、あらかじめ該半導体基板を加熱
あるいは冷却し、該半導体基板と静電チャックの温度差
を小さくすることを特徴とする静電吸着を用いた処理方
法。1. In a processing method in which a semiconductor substrate is electrostatically attracted by an electrostatic chuck in a vacuum, before the semiconductor substrate is attracted to the electrostatic chuck, the semiconductor substrate is heated or cooled in advance, and the semiconductor substrate and the electrostatic A processing method using electrostatic adsorption that is characterized by reducing the temperature difference between chucks.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63006767A JPH01185176A (en) | 1988-01-18 | 1988-01-18 | Processing method using electrostatic adsorption |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63006767A JPH01185176A (en) | 1988-01-18 | 1988-01-18 | Processing method using electrostatic adsorption |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01185176A true JPH01185176A (en) | 1989-07-24 |
Family
ID=11647328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63006767A Pending JPH01185176A (en) | 1988-01-18 | 1988-01-18 | Processing method using electrostatic adsorption |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01185176A (en) |
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