JPH01184945A - Driving device - Google Patents

Abstract

PURPOSE:To prevent the step out of driving signals by a method wherein a junction capacitance is set in such a way that the driving signals to be outputted from driving circuits, which are actuated in association with each other, are synchronized with each other. CONSTITUTION:A driving device is constituted in such a structure that the surface area of the junction between an N-type epitaxial layer 26 in a transistor (right side) of an upper-stage driving circuit 1 and a P-type semiconductor substrate 20 (and a P<+> diffused layer 25) is made large and a delay time due to a junction capacitance C1 can not be ignored. Moreover, the driving device can be constituted in such a structure that the surface area of the junction between an epitaxial layer 26 in a transistor (left side) of a lower-stage driving circuit 2 and the substrate 20 (and the layer 25) is made small and a delay time due to a junction capacitance C2 becomes small. That is, in case delay times due to junction capacitances C1, C2, CBE1 and CBE2 are respectively assumed to be tC1, tC2, tCBE1 and tCBE2, the surface areas of the junctions between the layers 26 and the substrate 20 (and the layer 25) are designed in such a way as to have a value of CBE1+tC1=tCBE2+tC2. Thereby, the delay time of the circuit 1 and the delay time of the circuit 2 are matched to each other and an output synchronized with that of the circuit 1 is obtained from the circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a drive device configured with an integrated circuit, and is used, for example, as a drive device for switching elements in an inverter circuit or a chopper circuit.

[Prior Art] Recently, drive circuits made of integrated circuits have been put into practical use in a wide range of application fields, such as motor drive circuits, switching regulator drive circuits, display drive circuits, and printer head drive circuits. In this type of drive circuit, the output circuit has a multi-stage configuration so as to obtain sufficient drive capability. Therefore, isolation technology between the elements constituting the multi-stage output circuit becomes important. Conventional isolation techniques can be roughly divided into junction isolation methods and dielectric isolation methods.

Among these, the junction separation method includes a self-separation method and a PN junction separation method.

FIG. 4(a) shows a cross-sectional structure of an integrated circuit using the self-isolation method. A low breakdown voltage MO3 type element 11 and a high breakdown voltage MO3 type element 12 are formed on the semiconductor substrate 10 without intervening an isolation region. With this self-separation property, there is no need to form separate isolation regions for each element, and the process is simple, but only MOS type elements can be used as constituent elements, and the MOS type elements have a common train or source. Therefore, it has the disadvantage of lacking in versatility.

FIG. 4(b) shows a cross-sectional structure of an integrated circuit using the PN junction isolation method. In the figure, an N-type epitaxial layer 26 is formed on a P-type semiconductor substrate 20, and a low-voltage NPN transistor 21 and an N
Channel and P-channel MOS transistors 22
．． 23 and a high-voltage NPN transistor 24 are formed, respectively. In this PN junction isolation method, when the breakdown voltage becomes high, an epitaxial layer 26 with a large thickness d is required as a field region, and the area of the P+ diffusion layer 25 for isolation increases, which tends to increase the chip size. Recently, various improvements have been made, and it has become possible to obtain high breakdown voltage even with a relatively small chip size. Furthermore, from a process perspective, conventional processes can be used, and elements can be integrated electrically independently, regardless of the type of output power element.

FIG. 4(e) shows a cross-sectional structure of an integrated circuit using the dielectric separation method. In the dielectric separation method, a dielectric material (for example, a silicon arsenic film of Si
○2) A plurality of single-crystal silicon islands 34 are arranged separated from each other via an insulating layer 35 consisting of In this example, a single crystal silicon island 34 is used to form P-channel and N-channel MO3 type devices 31,
32 and N P N +- transistor 33 is formed. This dielectric isolation method has good insulation isolation performance between elements, but the manufacturing process is more complicated than the PN junction isolation method.

From the above points of view, the PN junction split layer method is often used as an element isolation method for drive devices with medium breakdown voltages and medium currents.

FIG. 5 shows a circuit example of a two-channel output drive device A using the PN junction separation method. This drive device A includes an upper drive circuit 1, a lower drive circuit 2, an oscillation control circuit 3 provided on the same potential side as the lower drive circuit 2, and an oscillation control circuit i.
The operating power supplies of the 0 oscillation control circuit 3, which includes a level shifter circuit 4 that shifts the output of ¥43 to the voltage level of the upper drive circuit 1, and the lower drive circuit 2 are connected to the power supply terminal cc2 and the ground terminal GND2. It is taken from control power supply ■2. An output circuit including transistors Qs and Qs of a totem pole configuration is provided at the output section of the drive circuit 2, and a drive output is obtained from the output terminal 0UT2. The operating power supply for the upper drive circuit 1 is taken from a control power supply V connected to a power supply terminal Vcc and a ground terminal GND. The output section of the drive circuit 1 includes transistors Q, , Q having a totem pole configuration.

An output circuit including an output terminal OUT is provided, and a drive output is obtained from an output terminal OUT.

This drive device A drives an inverter circuit IV. The inverter circuit IV consists of a DC power supply E, a series circuit of switching elements Q, Q2, each consisting of a power MO3FE'r connected to both ends of the DC power supply E, and an inductance element connected to both ends of one switching element Q2. It consists of a series circuit of a capacitor C and a capacitor C. First, when the switching element Q2 is turned off and the switching element Q1 is turned on, the capacitor C is charged from the DC power supply E via the switching element Q1 and the inductance element.

Next, when the switching element Q is turned off and the switching element Q2 is turned on, the charge in the capacitor C becomes an inductance element and is discharged through the switching element Q2. By repeating this operation, an alternating current flows through the series circuit of the inductance element and the capacitor C.

[Problems to be Solved by the Invention] In the above conventional example, when the switching element Q1 is on and the switching element Q2 is off, the power supply voltage E is applied to the ground terminal GND, and conversely, when the switching element Q is off or off and switching element Q2 is on, the potential of ground terminal GND1 is equal to that of ground terminal GND.
It becomes the same potential as 2. Therefore, the ground terminal GND
, will change between the power supply voltage of the DC power source E and O volts, and therefore the upper stage drive circuit 1 needs to have a sufficient withstand voltage. This is because the semiconductor substrate 20 is always at the same potential as the ground terminal GND2, and the ground terminal GN
This is because when D becomes the power supply voltage of the DC power supply E, the upper drive circuit 1 operates at a voltage level higher than the semiconductor substrate 20 by the power supply voltage of the DC power supply E.

FIG. 6 shows a cross-sectional structure of an output transistor used in the drive circuit 1.2. The transistors shown are both N
It is a PN type, and the left side is for low voltage and the right side is for high voltage. The latter is used for the upper drive circuit 1, and the former is used for the lower drive circuit 2. In the figure, C7 is the upper drive circuit 1
The junction capacitance 08ε1 that exists between the N-type epitaxial layer N26 and the P-type semiconductor substrate 20 of the high-voltage transistor used in the transistor is the junction capacitance that exists between the base and emitter of the same transistor. Similarly, C2 is the junction capacitance that exists between the N-type epitaxial layer 26 and the P-type semiconductor substrate 20 of the low voltage transistor used in the lower drive circuit 2, and CHF2 is the junction capacitance that exists between the base and emitter of the same transistor. It is the capacity. Although other junction capacitances also exist,
Here, only the junction capacitance that greatly affects the delay time of signal transmission between the input and output of the drive circuit 1.2 is illustrated. In addition,
The junction capacitance Jlt C+, C2 mainly consists of a barrier capacitance generated when the PN junction between the N-type epitaxial layer 26 and the P-type semiconductor substrate 20 is reverse biased, and the junction capacitance Cr
3El l CflE2 mainly consists of a diffusion capacitance generated when the PN junction between the base and emitter is forward biased, but both may include other stray capacitances.

FIG. 7 shows these junction capacitances in a specific drive circuit. Although FIG. 7 shows a circuit example of the upper stage drive circuit 1, it is assumed that the lower stage drive circuit 2 has the same circuit configuration as the upper stage drive circuit 1.

The configuration of the circuit shown in FIG. 7 will be explained below. Power terminal■
One end of resistor R is connected to cc1, and the other end of resistor R5 is connected to the collector of transistor Q1□. The emitter of the transistor Q1□ is connected to the ground terminal GND. A resistor R1 is connected between the base of the I transistor Q l 2 and the input terminal IN. The base and emitter of the transistor Q1 and the base and emitter of the transistor Q +o are connected to the collector and emitter of the transistor Q l 2, respectively, and the collector of the transistor Q + + is connected via the resistor R2.
The collector of transistor Q+o is connected to power supply terminal Vcc via resistor R3. transistor Q,
The base and emitter of a transistor Q are connected to the collector and emitter of the transistor Q, respectively, and the collector of the transistor Q is connected to a power supply terminal Vcc+ via a resistor R4. The collectors of transistors Q10 and Q have 1
~The bases of transistors Q7 and Q8 are connected, respectively. The collector of transistor Q7 is connected to the power supply terminal Vccl,
The emitter of transistor Q is connected to the ground terminal GND, and the emitter of transistor Q7 and transistor Q
The collector of 8 is the output terminal OUT.

It is connected to the.

When the input terminal IN becomes "High" level, the transistor Q l 2 is turned on, the transistors Q and o are turned off, and the transistor Q7 is turned on. Also, transistor Q11 is turned off, and transistor Q11 is turned off.

is turned on, and transistor Q8 is turned off. therefore,
The output terminal OUT becomes "High" level. Also,
When the input terminal IN becomes the "Lo-" level, the transistor Q1□ is turned off, transistors 1 to Q1° are turned on, and the transistor Q7 is turned off.

is off, and I transistor Q8 is on. Therefore, the output terminal OUT becomes "'Low" level.

In the above circuit, the l transistor Q8 has a base-emitter junction capacitance CBE6, a collector-substrate junction capacitance C8, etc., and similar junction capacitances exist for each other transistor, but these are collectively referred to as the upper stage. In the drive circuit 1 shown in FIG.
This will be referred to as the inter-substrate junction capacitance ffi C2.

Here, the upper and lower drive circuits 1 and 2 have exactly the same configuration, and CBEI = CB2, CI = C
Assume that 2. In this case, if the drive circuits 1.2 operate at the same voltage level, the delay times for signal transmission between input and output should be the same. However, since the drive circuit 1 operates at a high voltage level and the drive circuit 2 operates at a low voltage level, the delay times of signal transmission between input and output are not the same. In other words, in the upper drive circuit 1, the ground terminal G
When ND reaches the level of the DC power supply E, the collector-substrate junction capacitance C1 is charged by the high voltage, and when the ground terminal GND reaches zero level, the charged charge is discharged, so that the collector-substrate junction capacitance C1 is charged. The charging and discharging speed of the capacitor C1 is fast. On the other hand, in the lower drive circuit 2, since the collector-substrate junction capacitance C2 is charged and discharged only by the voltage of the control power supply v2 applied between the power supply terminal Vcc2 and the ground terminal GND2, the collector-substrate junction capacitance C2
The charging and discharging speed of 2 is slow.

Therefore, as a delay element for signal transmission between input and output, in the upper drive circuit 1, the base-emitter indirect sound volume ff1C
Only BEI can be considered as base-emitter junction capacitance CBE2 and collector-substrate junction capacitance C2 in the lower drive circuit 2.

FIG. 8 shows the delay in signal transmission between the input and output of the drive circuit 1 shown in FIG. 7. In the drive circuit 1 shown in FIG.
Ransistors Q7-Q1. The base-emitter junction capacitances CBE7 to CBE11 of are discharged by the preceding stage transistors, so the base-emitter junction capacitances ffi
Of the CBEI, the base of the first stage transistor Q + 2 is substantially involved in the delay time of signal transmission between input and output.
The emitter-to-emitter junction capacitance nCo is only 12. If the charging speed of this junction capacitance CBE12 is slow, the input terminal I N
After the + level rises, the l transistor Q l
The timing at which transistor Q2 turns on is delayed, which delays the timing at which transistor Q2 turns on and the timing at which transistor Q8 turns off. Therefore, the timing at which the level of the output terminal OUT rises is delayed, resulting in a rise delay time tl.
occurs. Furthermore, if the discharge speed of the junction capacitor MC8E,2 is slow, the timing at which the transistor Q12 turns off is delayed after the level of the input terminal IN falls, which turns off the transistor Q7 and turns on the transistor Q. The timing is delayed. Therefore, the output terminal OUT,
The timing at which the level falls is delayed, resulting in a falling delay time t2.

On the other hand, in the drive circuit 2, not only the delay times L+ and h are caused by the base-emitter junction capacitance CBE2, but also a delay is caused by the collector-substrate junction capacitance C2. In other words, the junction capacitance C2 between collector and substrate
If . + occurs. Also,
Since it takes time to discharge the junction capacitance C2, the output terminal OUT.

The timing at which the level falls is also delayed, resulting in a falling delay time t2'.

Therefore, when comparing the upper and lower drive circuits 1 and 2, the lower drive circuit 2 has a longer delay time. However, there is a problem in that a signal that deviates from the normal lowering plate is output, making it impossible to drive normally. In particular, as shown in FIG. 5, in the inverter circuit IV connected to the series circuit of switching elements Q, Q2 or the DC power supply E, before the switching element Q2 is turned off by the lower drive circuit 2, When the switching element Q is turned on by the upper stage drive circuit 1, a large instantaneous current may flow due to simultaneous turning on, and there is a problem in that the stress on the switching elements Q, Q2 increases.

The present invention has been made in view of these points, and an object of the present invention is to provide a drive device consisting of a collector circuit including at least two drive circuits, in which the drive circuits operate in conjunction with each other. The purpose is to prevent synchronization.

[Means for Solving the Problems] In order to solve the above problems, the present invention has an N-type epitaxial layer 26 on a P-type raw conductor substrate 20, and the epitaxial layer 26 is made of It consists of an integrated circuit in which a plurality of semiconductor elements are formed separated by an impurity diffusion layer 25,
The drive circuit 1.2 includes a drive circuit 1.2 formed of the plurality of semiconductor elements, and each drive circuit 1.2 has a first junction capacitance ffiCl formed between the epitaxial layer 26 of the semiconductor element and the semiconductor substrate 20, C2 and a second junction capacitance CBε, , C formed between the control input terminal of the semiconductor element
In the drive device including BH3, the first junction capacitance C,,C2 and the second junction capacitance,
This is characterized by setting fl CBEI and CBH3.

Note that in the above configuration, P type and N type may be replaced.

[Function] In this way, the present invention enables the first junction capacitors MC, , C2 and the second junction capacitors to be synchronized so that the drive signals output from the drive circuits 1 and 2 that operate in relation to each other are synchronized. CBEI
+ Since CBH3 is set, even if the operating voltage levels of the drive circuits 1.2 are different, the delay time of signal transmission between the output terminals can be matched, and the drive circuits 1.2 operate in conjunction with each other. There is no possibility of loss of synchronization due to a difference in delay time.

"Execution PA1" FIG. 1 is a cross-sectional view of a main part of an integrated circuit used in the first embodiment of the present invention. This integrated circuit is divided into an N-type epitaxial layer 26 formed on a P-type semiconductor substrate 20. P+ for na
This is an integrated circuit with a PN junction isolation structure in which a diffusion layer 25 is provided and a plurality of semiconductor elements are formed. Both of the illustrated L transistors are of N P N type, and the one on the left is for low breakdown voltage, and the one on the right is for high breakdown voltage. The aftereffect is used in the upper drive circuit 1,
The former is used for the lower drive circuit 2. For each of the transistors 1 to 1 in the upper and lower stages, the collector-substrate junction capacitances C, C2 are determined by the N-type epitaxial layer 26 divided by the P+ diffusion layer 25 and the P-type semiconductor substrate 20 (and the P+ diffusion layer 25). It changes depending on the bonding surface quality (strictly speaking, it also depends on the impurity diffusion concentration, etc.).

As explained in the conventional example, the collector-substrate junction capacitance C1 in the upper drive circuit 1 is charged with a higher voltage than the collector-substrate junction capacitance C2 in the lower drive circuit 2, and the charged charge is discharged. Therefore, the collector-substrate junction capacitance C1 does not contribute as a delay element, and the delay time of the lower drive circuit 2 is longer than that of the upper drive circuit 1. Therefore, in this embodiment, as shown in FIG. 1, the N-type epitaxial layer 26 and the P-type semiconductor substrate 20 (and P
+diffusion layer 25), the structure is such that the delay time due to the junction capacitance C1 cannot be ignored. Furthermore, the transistor of the lower drive circuit 2 (in the figure,
The structure may be such that the junction surface area between the N-type epitaxial layer 26 and the P-type semiconductor substrate 20 (and the P+ diffusion layer 25) on the left side) is reduced to reduce the delay time due to the junction capacitance C2, or both The structures may be used in combination as appropriate.

In other words, junction capacitance C+ Ic 21CBEI Ic B
The delay time due to H3 is tc+, tc2 . tc
Assuming that aE++tcea2, it is sufficient to design the junction surface characteristics between the N-type epitaxial layer 26 and the P-type semiconductor substrate 20 (and the P+ diffusion layer 25) so that tCBEI +tc 1 = tc BF2+ LC2. The transistors in the upper drive circuit 1 are required to have a high withstand voltage, and the transistors in the lower drive circuit 2 can have a low withstand voltage, so designing the bonding surface as described above is advantageous from the viewpoint of withstand voltage design. It is.

In this way, the delay time of the upper drive circuit 1 and the delay time of the lower drive circuit 2 are matched, and the lower drive circuit 1
It is possible to obtain an output that is synchronized with the drive circuit 1 in the upper stage. By applying this one-money device to the inverter circuit IV shown in FIG. This will prevent such inconvenience from occurring.

[Embodiment 2] FIG. 2 is a sectional view of a main part of an integrated circuit used in a second embodiment of the present invention. This integrated circuit also has a PN junction isolation structure similar to that of the above-mentioned embodiment. Both transistors shown in the figure are of the NPN type, and the one on the left is for low breakdown voltage, and the one on the right is for high breakdown voltage. The latter is used for the upper drive circuit 1, and the former is used for the lower drive circuit 2.

In this embodiment, the collector-substrate indirect association IC,
By changing the structure of the transistor instead of changing c2, the base-emitter junction capacitance C8211
Changing CBE2. Therefore, in this case, as in the conventional example, the delay time due to the junction capacitance C1 of the upper drive circuit 1 is negligibly small, the delay time of the upper drive circuit 1 is tcBE, and the delay of the lower drive circuit 2 is negligible. the time is(
tc BE2+ tc 2). L transistor in the upper drive circuit 1 (right side in the figure)
The base-emitter indirect association M CBE l of the transistor is determined according to the junction area between the base region and the emitter region of the same transistor, and as shown in FIG. Meeting!
iCBE 1 can be increased. This results in
The delay time tcBε of the upper drive circuit 1 can be increased by designing the structure so that tc BEI = tc BE2 + tc 2.
It is possible to match the delay times of the drive circuit 2 and the lower drive circuit 2. Similarly, in the lower drive circuit 2), the base-emitter indirect connection M CBE of the transistor (left side in the figure)
2 may be used, or both of the above structures may be used simultaneously. Furthermore, a structure that is a combination of the structure described in Example 1 and the structure of this example may be used.

[Example 3] FIG. 3 is a circuit diagram of a third embodiment of the present invention.

In this embodiment, the DC/current power source for the inverter circuit IV is created by a chopper circuit CH.

Inverter circuit IV and chopper circuit CH are control circuit 6
are shared. The control circuit 6 includes an oscillation control circuit and a level shifter circuit, and is composed of a one-chip integrated circuit together with the drive circuit 1.2.7. The first and second output signals of the control circuit 6 are passed through the first and second drive circuits 1.2 to the switching elements Q, , Q, of the inverter circuit IV.
The third output signal of the control circuit 6 is supplied to the switching element Qo of the chopper circuit CH via the third drive circuit 7. Here, by using the above-described structure for each of the first to third drive circuits 1, 2.7, it is possible to extract synchronized drive signals from each drive circuit 1, 2.7. Thereby, the inverter circuit IV and the chopper circuit CH can be operated synchronously, and power supply distortion can be reduced. In other words,
The inverter circuit IV is configured to be supplied with direct current by either the smoothing capacitor provided on the output side of the chopper circuit CH or the rectifier circuit provided on the input side, and the input current from the AC power source 8 is connected to the chopper circuit CH.
and control circuit 6 so that the flow alternately flows to inverter circuit IV.
By configuring this, it is possible to reduce the period during which the input current from the AC power supply 8 is stopped, and it is possible to reduce power supply distortion (Japanese Patent Application No. 188461/1988).
(see issue).

Although the above embodiments have been described with reference to two or three drive circuits, the present invention can be applied as long as there are two or more drive circuits that operate in conjunction with each other. Note that the state in which drive circuits that operate in conjunction with each other are synchronized does not necessarily mean that they output a signal that is exactly in phase with one signal or a signal that is in the opposite phase of one signal, but also when one signal falls. This also includes a case where the other signal rises while maintaining a certain phase relationship from one signal to the other.

In addition, although an inverter circuit and a chopper circuit have been shown as specific examples of circuits driven by the drive circuit, it is also possible to apply it to drive circuits for displays and printer heads that include multiphase pulse motors and multiple driven elements. It goes without saying that there is.

[Effects of the Invention] As described above, the present invention provides a drive device comprising an integrated circuit with a PN contact separation structure including at least two drive circuits, in which drive signals output from drive circuits that operate in conjunction with each other are used. Since the junction capacitance is set so that the signals are synchronized, it is possible to prevent problems caused by out-of-synchronization of the drive signals.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a main part of an integrated circuit used in a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a main part of an integrated circuit used in a second embodiment of the present invention, and FIG. 4(a) to 4(c) are cross-sectional views for explaining the element separation technology in a conventional integrated circuit, FIG. 5 is a circuit diagram of the conventional example, and FIG. 6 is a block circuit diagram of the third embodiment. FIG. 7 is a sectional view of a main part of an integrated circuit used in the above, FIG. 7 is a circuit diagram of a main part of a conventional drive circuit, and FIG. 8 is a waveform diagram for explaining the operation of the same. 1.2 is the drive circuit, C, C2 is the first junction capacitance, CB
εI and CBE2 are the second junction capacitances.

Claims (2)

[Claims] (1) An integrated circuit comprising an N-type epitaxial layer on a P-type semiconductor substrate, the epitaxial layer being separated by a P-type impurity diffusion layer to form a plurality of semiconductor elements, and the plurality of semiconductor elements at least two drive circuits formed by the semiconductor element, each drive circuit being formed between a first junction capacitor formed between the epitaxial layer of the semiconductor element and the semiconductor substrate, and a control input terminal of the semiconductor element. In a drive device including a second junction capacitor, the first and second junction capacitors are set so that drive signals output from drive circuits that operate in conjunction with each other are synchronized. Characteristic drive device. (2) Claim 1 characterized in that P type and N type are replaced.
Drive device as described.