JP4168720B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit on a dielectric isolation substrate provided with a totem pole circuit as an output circuit.
[0002]
[Prior art]
With the progress of dielectric isolation technology combining bonded substrate (hereinafter abbreviated as SOI substrate) and trench isolation technology, high voltage MOS devices such as diodes, insulated gate bipolar transistors (hereinafter abbreviated as IGBT), MOSFETs and the like Development of a power IC (IC: integrated circuit) in which a drive / control / protection circuit is integrated on a single silicon substrate has been actively conducted. In this dielectric separation system, a plurality of high voltage bipolar devices can be integrated, and there is no limitation on the circuit configuration mounted on the power IC. As a result, for example, a totem pole circuit to which an IGBT is applied and an integrated circuit on which multiple stages of the totem pole circuit are mounted are formed on one chip (on one semiconductor substrate).
[0003]
FIG. 6 shows a circuit configuration example of a power IC having a totem pole circuit 1 composed of two n-channel MOSFETs (N1, N2) (for example, Patent Document 1). In the figure, N1, N2, and N3 are high breakdown voltage n-channel MOSFETs, and P1 is a high breakdown voltage p-channel MOSFET. In this circuit, the signal output from the output terminal Do of the totem pole circuit 1 is controlled by the signal input from the input terminal Vin. The totem pole circuit 1 is widely applied to motor drive inverter ICs and display drive ICs.
[0004]
In the figure, a p-channel MOSFET (P1) and an n-channel MOSFET (N3), and a resistor R and a constant voltage diode ZD are circuit elements for forming a signal Vg2 for driving the upper arm side MOSFET (N2). is there. P1 operates by receiving an output signal from the level shift circuit 3 in the previous stage, and the level shift circuit 3 is further controlled by the control circuit 4 in the previous stage. On the other hand, N3 is driven by a signal Vg3 from the control circuit 4. Vg3 is synchronized with the signal Vg1 that drives N1.
[0005]
The power supply of the control circuit 4 is supplied from the control circuit side terminal VL, and the voltage is a low voltage of 15V or less. On the other hand, power for driving the totem pole circuit 1 and the level shift circuit 3 is supplied from the output side power supply terminal VH. A high voltage power supply exceeding the control circuit side power supply terminal VL is connected to the output side power supply terminal VH, and the magnitude of the power supply voltage varies depending on the driving load.
[0006]
N1 and N2, and P1 and N3 to which the output side power supply voltage is applied from VH, and the devices constituting the level shift circuit 3 are high breakdown voltage devices, and the high breakdown voltage circuit unit 5 is configured by these.
[0007]
The current for driving the load connected to Do is supplied from N2 and N1. The current flowing through N1 is a current flowing from the load to the ground, and the current flowing through N2 is a current flowing from VH to the load. Therefore, the current flowing through the load is determined by the current driving ability of N1 and N2. In the totem pole circuit, there is no current flowing through N1 and N2 at the same time except at the time of switching.
[0008]
In the circuit of FIG. 6, the case where the high withstand voltage output circuit section 5 is formed on a dielectric isolation substrate combining SOI substrate and trench isolation will be described.
[0009]
FIG. 7 shows an arrangement example of each element. In FIG. 7, the wiring pattern is omitted for simplification. In FIG. 7, circuit areas (P1, ZD, R), N1, N3, and N2 for driving the level shift circuits 3 and N2 are sequentially arranged from the control circuit 4 side, and these areas are adjacent to each other. Has a dielectric isolation region 7 interposed therebetween.
[0010]
A circuit for driving N2 is constituted by P1, ZD, and R, and P1 and ZD are separated from each other by a dielectric separation region. The level shift circuit 3 is also composed of a plurality of high voltage elements and is dielectrically separated. However, for simplification, in FIG. 7, each is represented as one circuit region.
[0011]
Further, the area area of N1 and N2 is determined by the magnitude of the drive current required for each element.
[0012]
FIG. 8 shows a BB cross section extending from N1 to N2 in FIG. In FIG. 8, an SOI substrate 123 in which an n-type or p-type semiconductor substrate 100 and an n-type semiconductor substrate 300 are bonded together with an oxide film 200 is used. Further, the terminal names of the elements in FIG. 8 are made to match the terminal names in FIG. Hereinafter, the sectional view of FIG. 8 will be described.
[0013]
The drain electrode 8 of N2 is connected to VH, the gate electrode 10 is connected to the drain of P1 in FIG. 6, and a signal of Vg2 is inputted. The source electrode 9 is connected to Do and the drain electrode of N1. On the other hand, the Vg3 signal is input to the gate electrode of N3 from the control circuit 4 of FIG. The source electrode 14 is connected to the ground terminal. N3 and N2 are each formed in a region completely surrounded by the dielectric isolation region 7. Therefore, there is no electrical interference between the two elements.
[0014]
Next, FIG. 9 shows switching waveforms when a capacitive load is connected to Do in the circuit of FIG. 6 and an n-channel MOSFET having a current drive capability of 200 mA is applied as N2. FIG. 9 shows the waveform of the output voltage (Vout) of Do and the waveform of the current (Iout) flowing through the load via the terminal. The magnitude of the power supply voltage connected to VH is 80V.
[0015]
Vout when N2 is OFF is 0V. As soon as N2 is turned on, a current for charging the load capacitance flows, and Vout rises to the power supply voltage. The waveform of this charging current is Iout, and the peak value of Iout in FIG. 9 is 200 mA. This peak value is determined by the current drive capability of N2.
[0016]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-68540, FIG. 1, etc.
[Problems to be solved by the invention]
Here, when it is desired to shorten the rise time of Vout (the time when Vout is changed from 10% to 90%), the charging current may be increased. As described above, since the peak value of the charging current is determined by the current driving capability of N2, in order to increase the peak value, it is preferable to increase the driving current of N2. However, in order to increase the drive current, it is necessary to increase the N2 channel width, which leads to an increase in the device area of N2, that is, an increase in the chip area of the power IC.
[0018]
Similarly, even when a resistive load or an inductance load is connected to Do in FIG. 6, it is necessary to expand the device area of N2 when increasing the load current flowing from the IC side to the load. This increases the chip area of the power IC and leads to an increase in IC cost.
[0019]
Therefore, in the circuit of FIG. 6, when it is desired to increase the drive current of N2, how to suppress the increase in the chip area of the IC accompanying it becomes a problem.
[0020]
In addition, as shown in FIG. 8, the dielectric separated element is capacitively coupled to the adjacent element. Thus, for example, the voltage variation of the N2 side region is generated by the switching operation of N2, N2 and N3 and the displacement current Idis through the adjacent capacitance C _ISO formed on the dielectric isolation region 7 between the regions forming the occurrence To do. This displacement current Idis does not flow into the load, but flows to the ground via N3. Therefore, the displacement current Idis flowing through the adjacent capacitance C _ISO, in conventional totem-pole circuit comprises a kind of leakage current, the reactive current.
[0021]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device in which a totem pole circuit is formed on a dielectric isolation substrate capable of preventing the increase in chip size and effectively using a displacement current.
[0022]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor integrated circuit device comprising a totem pole circuit having a lower arm side and an upper arm side constituted by two n-channel MOS devices dielectrically separated from each other as an output circuit. Side n-channel MOS device and a diode formed through a dielectric isolation region, and electrically connect the anode of the diode and the low-potential side main electrode of the n-channel MOS device on the upper arm side and, electrically connecting the high-potential-side main electrode of the n-channel MOS device the cathode and the lower arm of the diode, the configuration of the connection point between the cathode of said drain and said diode and an output of said output circuit To do.
[0023]
Also, in a semiconductor integrated circuit device having a totem pole circuit in which a lower arm side and an upper arm side are constituted by two n-channel MOS devices that are dielectrically separated from each other as an output circuit, an n-channel MOS device on the upper arm side A low-potential side main electrode of the n-channel MOS device on the upper arm side and a high-potential side main electrode of the n-channel MOS device on the lower arm side. Are connected to the semiconductor region, and the connection point is used as an output of the output circuit.
[0024]
Further, in a semiconductor integrated circuit device including a totem pole circuit in which a lower arm side and an upper arm side are constituted by two n-channel MOS devices that are dielectrically separated from each other as an output circuit, a first semiconductor substrate and a second semiconductor The second semiconductor base material of the semiconductor substrate having an insulating film interposed between the base materials is divided into a plurality of semiconductor regions separated by dielectrics, and the first semiconductor region among the divided semiconductor regions Forming an n-channel MOS device on the upper arm side, forming an n-channel MOS device on the lower arm side in the second semiconductor region, adjoining the first semiconductor region, and forming a diode in the third semiconductor region And electrically connecting the anode of the diode and the low-potential main electrode of the n-channel MOS device on the upper arm side, Electrically connecting the high-potential main electrode of the arm side of the n-channel MOS device, the connection point between the cathode of said drain and said diode configured to an output of the output circuit.
[0025]
Further, in a semiconductor integrated circuit device including a totem pole circuit in which a lower arm side and an upper arm side are constituted by two n-channel MOS devices that are dielectrically separated from each other as an output circuit, a first semiconductor substrate and a second semiconductor The second semiconductor base material of the semiconductor substrate having an insulating film interposed between the base materials is divided into a plurality of semiconductor regions separated by dielectrics, and the first semiconductor region among the divided semiconductor regions Forming an n-channel MOS device on the upper arm side, forming an n-channel MOS device on the lower arm side in the second semiconductor region, and the lower potential side main electrode of the n-channel MOS device on the upper arm side Connecting a connection point with the high-potential side main electrode of the n-channel MOS device on the arm side to a third semiconductor region formed adjacent to the first semiconductor region; A configuration in which the output of the serial output circuit.
[Action]
In this way, the diode is connected in series between the upper arm side device and the output terminal of the totem pole circuit, and the connection direction is set so that the output terminal is forward from the upper arm side device. Further, the region for forming the diode is formed as a dielectric-isolated region independently and is adjacent to the region for forming the upper arm side device.
[0026]
When the upper arm side device is in the off state, that is, when the lower arm side device is in the on state, the diode is also at the ground potential. When the lower arm side device is turned off and the upper arm side device is turned on, the diode forming region and the upper arm side device are formed in the diode adjacent to the upper arm side device due to voltage fluctuation in the upper arm side device region. Displacement current Idis (= C _ISO × (dV / dt): dV / dt is applied to both sides of the dielectric isolation region through the inter-adjacent capacitance C _ISO formed between the dielectric isolation regions. Voltage changes with time). This displacement current flows into the output terminal and becomes a load current. Therefore, it is not an invalid current as in the conventional example.
[0027]
Further, since this displacement current flows into the load without passing through the upper arm side device, the load current can be increased without increasing the occupied area (device region) of the upper arm side device.
[0028]
Further, the displacement current can be used as the load current by simply forming the semiconductor region without forming the diode in the region where the diode is formed. In this case as well, the load current can be increased without increasing the area occupied by the upper arm side device.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention. In addition, the same code | symbol was described in the same location as FIG.
[0030]
The main part of this semiconductor integrated circuit device is composed of a control circuit 4 and a high voltage circuit 5. The high withstand voltage circuit unit 5 includes level shift circuits 3, P 1, N 3, R, ZD and a totem pole circuit 1. The totem pole circuit 5 includes N1, N2, and D1. The difference from the circuit of FIG. 6 is that a diode D1 is inserted. D1 is connected in the forward direction from N2 to Do. Next, an outline of this circuit will be described.
[0031]
A power source for driving the control circuit 4 is supplied from the control circuit side power supply terminal VL, and a control signal is input to the control circuit 4 from the input terminal Vin. A power source for driving the high-breakdown-voltage circuit unit 5 is supplied from the output side power supply terminal VH, and an output current of the totem pole circuit 1 is output from the output terminal Do. The control circuit 4 outputs a signal for controlling the level shift circuits 3, N3, and N1. The level shift circuit 3 outputs a gate signal of P1. The gate signal of N2 is output from the drain of P1, and ZD prevents this gate signal from becoming an overvoltage. P1 and N3 are turned on and off in opposite phases. N1 and N2 of the totem pole circuit 1 are turned on and off in opposite phases, and when N2 is on, a current flows to the load via D1. At this time, a displacement current Idis flows from the adjacent capacitance C _ISO (capacitance formed between N2 and a semiconductor region of FIG. 3 described later) formed in the dielectric isolation region to a load connected to Do. When the load is a capacitor, this Idis is added, so that the rise of the capacitor voltage is accelerated and the response speed can be increased.
[0032]
On the other hand, when N1 is turned on, a discharge current flows through N1 from the capacitor connected to Do, and the voltage of the capacitor becomes ground. At this time, N3 is turned on in the same phase as N1 or slightly earlier than N1. D1 functions to prevent the discharge current from flowing into N3 and reduce the current capacity of N3. By providing this D1, the current drive capability of N3 can be reduced and the occupied area in the semiconductor chip can be reduced as compared with FIG. Further, the current driving capability of D1 may be equal to that of N2, and the occupation area is a diode, so that it may be 1/10 or less of N2.
[0033]
Although the n-channel MOS device on the lower arm side in FIG. 1 is shown as a MOSFET, it may be an IGBT (insulated gate bipolar transistor).
[0034]
FIG. 2 shows an example of element arrangement when the high voltage circuit portion 5 of FIG. 1 is formed on a dielectric isolation substrate (SOI substrate). As in FIG. 7, the wiring pattern and the like are omitted, and only the region where the element is formed is shown. Further, the level shift circuit 3 and P1, ZD, and R are expressed as one circuit area.
[0035]
Also in this element arrangement, isolation between regions is performed by the dielectric isolation region 7 as in FIG. In this figure, compared with FIG. 7, a D1 formation region is provided between the N2 formation region and the N3 formation region. In the present invention, the arrangement is not particularly limited except that the D1 formation region is arranged adjacent to the N2 formation region.
[0036]
Here, D1 needs to have a current driving capability equivalent to that of N2, but the area occupied by the D1 formation region, which is a diode, can be reduced to 1/10 or less as compared with the N2 formation region.
[0037]
FIG. 3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. This figure is a cross-sectional view of the main part taken along line AA in FIG. Using a SOI substrate 123 in which a semiconductor substrate 300 is bonded to a p-type or n-type semiconductor substrate 100 with an oxide film 200 interposed therebetween, a dielectric isolation region 7 is formed on the semiconductor substrate 300 to form a semiconductor substrate. The material 300 is divided into islands to form a plurality of semiconductor regions. N2, D1, N3, etc. are formed on separate islands. The element configuration is the same as in FIG. D1 is formed in the adjacent region of N2 via the dielectric isolation region 7. Displacement current Idis described in Figure 1, it flows through the adjacent capacitance C _ISO formed on the dielectric isolation region 7 lying between the region for forming the N2 and D1. In this figure, formation regions such as N1, ZD, and R are omitted. The terminal 6 is connected to the anode electrode 12 of D1 and the source electrode 9 of N2.
[0038]
In the following, the configuration and operation of the semiconductor integrated circuit device of the first embodiment will be described again using the cross-sectional structure of FIG.
[0039]
The drain electrode 8 of N2 is connected to VH, and the gate electrode 10 is connected to the drain electrode of P1. A gate signal Vg2 for controlling the operation of N2 is input to the gate electrode 10. The source terminal 9 is connected to the anode terminal 12 of D1 and the drain terminal 13 of N3. The cathode terminal 11 of D1 is connected to the drain terminal of N1 together with Do. In this figure, the drain terminal of N1 is omitted. The gate terminal 15 of N3 is connected to the control circuit 4 and receives the gate signal Vg3. The source terminal is connected to the ground.
[0040]
In the above connection state, consider that N2 is off and N1 and N3 are on. In this state, since the voltages of the cathode electrode 11 and the anode electrode 12 of D1 are the ground voltage, the region of D1 is the ground voltage. On the other hand, the pn junction between the N2 p-well region and the n drift region is in a reverse bias application state, and a depletion layer spreads in the N2 region and has a potential gradient.
[0041]
When N1 and N3 are turned off and N2 is turned on, the inside of the region N2 rises to the power supply voltage. This potential increase occurs instantaneously, and a displacement current Idis is generated through capacitive coupling (C _{ISO in} FIG. 1) with the adjacent D1 due to the voltage change. This current flows from the cathode electrode 11 of D1 into Do.
[0042]
Therefore, the displacement current accompanying the switching of N2 can be used as the load current. Then, when N2 is turned on, the current flowing from VH to the load is added with the drive current of N2 and this displacement current, and the current supplied to the load is increased without expanding the device area of N2. Is possible.
[0043]
FIG. 4 shows an evaluation result when the circuit of FIG. 1 is actually manufactured on a semiconductor substrate with the configuration shown in FIG. Evaluation conditions and device conditions (specifications) of N2 are the same as those in FIG.
[0044]
When the peak value of Iout is observed, a current of 380 mA flows. This current corresponds to about twice the driving capability of N2. That is, the load current can be increased up to twice without doubling the occupied area (device region) of N2. This is a result of using the displacement current Idis generated by switching of N2 as a load current, and the effect of the present invention can be confirmed from the result.
[0045]
Incidentally, the displacement current Idis is dependent on adjacent capacitance C _ISO, it can be adjusted by changing the area N2 and D1 are in contact.
[0046]
FIG. 5 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to the second embodiment of the present invention.
[0047]
The difference from FIG. 3 is that D1 is not formed and that portion is a semiconductor region. In this case as well, since C _ISO is formed in the same manner as in FIG. 3, the same effect as in FIG. 3 is obtained. It is done. However, when N1 and N3 are turned on, the current flowing into N1 from the load side also slightly flows into N3, which is an adjacent element, via ZD, so it is necessary to slightly increase the current driving capability (occupied area) of N3. There is. However, even in this case, since the increase in the area occupied by N2 can be prevented, the chip size can be reduced compared to the conventional structure. Although the case where the SOI substrate is n-type is shown above, it may be p-type.
[0048]
【The invention's effect】
According to the present invention, in a totem pole circuit composed of two n-channel MOS devices on a dielectric isolation substrate, a diode isolated in series between an upper arm device and an output terminal is inserted in series. By connecting the diode to the forward direction from the upper arm side device to the output terminal direction, and arranging it in the adjacent region of the upper arm side device,
A displacement current generated when the upper arm device is turned on can be used as a load current via a diode adjacent to the upper arm device. As a result, the load current can be increased without increasing the area occupied by the upper arm device (device region). Furthermore, since the diode can prevent the current flowing out from the load from flowing to the ground via N3, which is an adjacent element that operates in the same phase as the lower arm device, the area occupied by the adjacent element (N3) can be reduced. it can.
[0049]
Further, in a totem pole circuit composed of two n-channel MOS devices on a dielectric isolation substrate, a semiconductor region separated by dielectric is formed between the upper arm side device and the output terminal, and the semiconductor region and the upper arm are formed. By placing the side device formation area adjacent to each other,
When the upper arm side device is turned on, the displacement current flowing through the inter-adjacent capacitance C _ISO formed in the dielectric isolation region is used as a load current, so that the area occupied by the upper arm side device (device region) is reduced. It is possible to increase the load current without increasing it.
[0050]
Thus, by using the displacement current as the load current, it is possible to increase the response speed of a plasma display device in which the load is a capacitor.
[Brief description of the drawings]
FIG. 1 is a block diagram of a main part of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 2 is a diagram showing an example of element arrangement when a high voltage circuit portion is formed on a dielectric isolation substrate in the circuit of FIG. 3 is a cross-sectional view of a main part taken along line AA in FIG. 2. FIG.
FIG. 4 is a diagram showing a result of trial production of a totem pole circuit to which the present invention is applied. FIG. 5 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 7 is a diagram showing an example of element arrangement when a high voltage circuit portion is formed on a dielectric isolation substrate in the circuit of FIG. 6. FIG. 8 is a cross-sectional view of an essential part taken along line BB in FIG. FIG. 9 is a diagram showing the result of trial production using a conventional totem pole circuit.
DESCRIPTION OF SYMBOLS 1 Totem pole circuit 3 Level shift circuit 4 Control circuit 5 High voltage circuit part 6 Terminal 7 Dielectric isolation region 8, 13 Drain electrode 9 14 Source electrode 10, 15 Gate electrode 11 Cathode electrode 12 Anode electrode 100, 300 Semiconductor substrate 123 SOI substrate 200 Oxide film N1, N2, N3 n-channel MOSFET
P1 p-channel MOSFET
ZD constant voltage diode R resistor C _ISO adjacent capacitance D1 diode VH output side power supply terminal Do output terminal VL control circuit side power supply terminal Vin input terminal Vg1 gate signal Vg2 controlling N1 gate signal Vg3 controlling N3 Gate signal Idis Displacement current Vout Output voltage at Do terminal Output current at Iout Do terminal

Claims (4)

In a semiconductor integrated circuit device including a totem pole circuit, in which a lower arm side and an upper arm side are configured by two n-channel MOS devices that are dielectrically separated from each other, as an output circuit,
An n-channel MOS device on the upper arm side and a diode formed through a dielectric isolation region;
The anode of the diode is electrically connected to the low-potential side main electrode of the n-channel MOS device on the upper arm side, and the cathode of the diode and the high-potential side main electrode of the n-channel MOS device on the lower arm side are connected A semiconductor integrated circuit device characterized in that it is electrically connected and a connection point between the drain and the cathode of the diode is an output of the output circuit. In a semiconductor integrated circuit device including a totem pole circuit, in which a lower arm side and an upper arm side are configured by two n-channel MOS devices that are dielectrically separated from each other, as an output circuit,
A semiconductor region formed through an n-channel MOS device on the upper arm side and a dielectric isolation region;
A connection point between the low-potential side main electrode of the n-channel MOS device on the upper arm side and the high-potential side main electrode of the n-channel MOS device on the lower arm side is connected to the semiconductor region, and the connection point is the output A semiconductor integrated circuit device characterized by being an output of a circuit. In a semiconductor integrated circuit device including a totem pole circuit, in which a lower arm side and an upper arm side are configured by two n-channel MOS devices that are dielectrically separated from each other, as an output circuit,
The second semiconductor substrate of a semiconductor substrate having an insulating film interposed between the first semiconductor substrate and the second semiconductor substrate is divided into a plurality of semiconductor regions separated by dielectrics, and the plurality of divided semiconductors Among the regions, an n-channel MOS device on the upper arm side is formed in the first semiconductor region, an n-channel MOS device on the lower arm side is formed in the second semiconductor region, and adjacent to the first semiconductor region. And forming a diode in the third semiconductor region,
The anode of the diode and the low potential main electrode of the n-channel MOS device on the upper arm side are electrically connected, and the cathode of the diode and the high potential main electrode of the n channel MOS device on the lower arm side are electrically connected And a connection point between the drain and the cathode of the diode is used as an output of the output circuit. In a semiconductor integrated circuit device including a totem pole circuit, in which a lower arm side and an upper arm side are configured by two n-channel MOS devices that are dielectrically separated from each other, as an output circuit,
The second semiconductor substrate of a semiconductor substrate having an insulating film interposed between the first semiconductor substrate and the second semiconductor substrate is divided into a plurality of semiconductor regions separated by dielectrics, and the plurality of divided semiconductors Forming an n-channel MOS device on the upper arm side in the first semiconductor region and forming an n-channel MOS device on the lower arm side in the second semiconductor region;
A connection point between the low potential side main electrode of the n-channel MOS device on the upper arm side and the high potential side main electrode of the n channel MOS device on the lower arm side is formed adjacent to the first semiconductor region. A semiconductor integrated circuit device, wherein the connection point is an output of the output circuit.

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