JPH01184860A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To effectively manufacture a semiconductor device of chip multi-stage mounting type, by a method wherein, before ICs are not cut off from a film tape of tape carrier system, a plurality of corresponding lead terminals of ICs are connected with each other, and sealing is performed in this state. CONSTITUTION:The IC chip 1a of an IC memory 12 mounted on a film tape 6b is in the mirror image relation to the IC chip 1 of an IC memory 11 mounted on a tape 6a, with respect to internal circuits and electrodes except a chip selecting electrode. Each lead terminal 5 of the above IC chips is also in a mirror image relation. The film tape 6a mounting the IC memory 11 is turned over, and thereon the film tape 6b mounting the IC memory 12 is so stacked that the mutual lead terminals 5 face and neighbor with each other. In the state where the IC memories 11, 12 are on the film tapes 6a, 6b, respectively, the lead terminals 5 of the IC memories 11, 12 are mutually joined. The sealing is performed in this state.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device.
A method for manufacturing a semiconductor device that assembles semiconductors using the so-called tape carrier method (TAB method) based on a flexible insulating film, and a method for manufacturing a multistage chip mounting type IC that is less likely to cause connection failures and has good production efficiency. Regarding.

[Prior Art] In order to increase the memory capacity of a conventional semiconductor device configured with a semiconductor memory such as ROM1RAM, a plurality of memory chips must be installed. All terminals other than the chip select terminal are commonly connected to their corresponding signal terminals.

Therefore, as the memory capacity increases, the memory IJIC occupancy rate on the board increases, making it difficult to downsize and also making the wiring pattern more complex.

As a result, in order to increase memory capacity in the same occupied area, multi-stage mounting is performed in which memory chips are stacked.

As a method for multi-stage mounting using a TAB type memo UIC, for example, it is carried out through a process as shown in FIG. That is, the tape-carried memory IC is punched and formed in step 100 to cut off the excess chip select terminal (C8 terminal). In parallel with this, in step 101, the tape-carried memory IC is similarly punched and formed to cut off the excess C8 terminal. In this way, multiple memory ICs
Cut out the elements in advance (.

Separately, in step 102, cream solder printing is performed to coat the printed circuit board with cream solder, and then in step 103, the memory IC obtained in step 100 is brought to the board side.
The lead terminals and the board terminals are properly aligned (1)) and mounted on the board in step 104.

In the next step 105, similarly, bring the memo UIC obtained in step 101 to the board side and properly align the lead terminal and the board terminal (2).
) In step 106, two memory ICs are mounted on the board, and in step 107, the lead terminals of these two memory ICs and the board terminals are simultaneously soldered and mounted on the board.

[Issue to be solved] This conventional method has the following drawbacks.

(1) The U-card terminal is not fixed sufficiently, and it is necessary to mount it on the board etc. with the IC chip part exposed, making the handling mechanism complicated and difficult to handle easily. .

(2) After separating the memory IC from the film tape, the board terminals and lead terminals are aligned, but since multiple memory ICs are stacked in multiple stages, it is difficult to align the lead terminals of the upper memory IC. be.

(3) Since the forming shapes of the lead terminals of the ICs arranged above and below are different, the number of types of punching/forming molds corresponding to the number of ICs stacked in multiple stages is required.

(4) When IC is multi-staged due to variations in forming shape, proper forming cannot be performed on all lead terminals, resulting in lead terminals where stress concentration occurs.

It is an object of the present invention to provide a method for manufacturing a chip multi-stage mounting type semiconductor device with high production efficiency by solving various handling problems in the manufacturing process that the conventional semiconductor device manufacturing method has. With the goal.

[Means for Solving the Problems] A semiconductor device of the present invention for achieving the above-mentioned object is a method for manufacturing a semiconductor device in which semiconductor chips mounted using a tape carrier method are vertically mounted in multiple stages. Chip-mounted tapes are arranged one above the other, and the corresponding lead terminals connected to the respective semiconductor chips mounted on the upper and lower tapes are electrically connected to each other via a lead member serving as an outer lead or directly. , for sealing a plurality of semiconductor chips whose corresponding lead terminals are connected to each other.

[Function] In this way, when mounting IC chips mounted using the tape carrier method in multiple stages, the corresponding lead terminals of the multiple IC chips are connected to each other before the IC chips are separated from the film tape, and sealed in this state. Since the IC is then handled in a packaged state,
It becomes very easy to handle.

As a result, when mounted on a board or the like, alignment with the board is easy and lead terminals are less likely to bend. Also, for other uses, semiconductor devices can be cut out from film tape in packaged form.
The subsequent handling process becomes simple, and a chip multi-stage mounting type semiconductor device can be manufactured with high production efficiency.

[Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a flowchart of a semiconductor manufacturing process shown in an embodiment of the manufacturing method according to the present invention, and FIG. 2(a),
(b) is a cross-sectional view of a memory IC that is tape-carried in each manufacturing process and a cross-sectional view of a package cut out from the tape carrier; FIG. 3 is a plan view of the memory IC that is tape-carried; and FIG. FIG.
b) is a sectional view of a cut-out package in each of the other embodiments; In addition, in each figure, equivalent parts are indicated by the same reference numerals.

As shown in FIG. 2(a), a memory ICII consisting of an IC chip 1 and lead terminals 5 is mounted, a film tape 6a is turned over, and a memory IC II consisting of an IC chip 1a and lead terminals 5 is placed on top of it. The film tapes 6b on which the U I C12 are mounted are placed one on top of the other so that the lead terminals 5 face each other and are adjacent to each other, and with the memories ICII and 12 on the respective film tapes 8a and eb,
The lead terminals 5 of the IC memories 11 and 12 are joined together.

Here, the memory I mounted on the film tape 6b
The IC chip la of C12 is connected to the IC chip 1 of the memory tct t mounted on the film tape 6a.
Except for the chip select electrode, its internal circuits and electrodes are in a mirror image relationship, and each lead terminal 5 is also arranged in a mirror image relationship.

Therefore, as shown in FIG. 2(a), by arranging the film tape 6b facing the turned-over film tape 6a without turning it over, each memory IC 11, 1
The two lead terminals 5 correspond to each other.

Except for the fact that the IC chips of the IC memory are mirror images of each other, the film tapes 6a and 6b are
Since they have similar configurations, these will be described as film tapes 6 in accordance with FIG.

The film tape 6 has a memory 1cit or 12 disposed inside an opening 4 provided approximately in the center thereof, and a plurality of lead terminals 5 thereof are disposed on both sides in the front and back direction with respect to the feeding direction of the film tape. It is fixed around the corresponding side of part 4.

Therefore, the memory ICII (12) is bridged by the lead terminals 5 on both sides of the film tape 6.
each lead terminal 5 and its IC chip l.
(or each electrode of the IC chip la) via bumps 3.

A sprocket hole 14 is provided around the front and rear of the film tape 6, and the sprocket hole 14 allows the film tape 6 to be accurately fed through the sprocket with an error within a range of, for example, ±20 μm, so that the two film tapes 6a, 8b can be transported in a vertically arranged state as shown in FIG. 2(a).

Therefore, the memory ICI arranged vertically in this way
The positioning of the respective lead terminals 5 of I and 12 can be performed extremely accurately.

Therefore, through the manufacturing process shown in FIG. 1, the lead terminals 5 are joined together on the film tapes 6a and 3b.
After that, these corresponding lead terminals are joined to each other.
The two memories ICII, 12 are simultaneously sealed and a part of the connected lead terminals 5 or the lead terminals of the lead frame are packaged as outer leads, and the packaged state is cut out from the film tape 8 a e 8 b. 2. A semiconductor device having a package 13 as shown in FIG. 2(b) and two memories ICII and 12 inside the package 13 is manufactured. Note that 7 is an outer lead formed by joining the lead terminals 5 together.

The manufacturing method will be explained below. In step 111 of FIG.
Punch out the extra chip select terminal (C8 terminal) of
Separately, in step 112, similarly punch out the extra C8 terminal of the memory IC 12 on another tape carrier,
The film tape 6.6 on which the two memories ICII, 12 are mounted is arranged and fed close to each other in two stages, upper and lower, as shown in FIG. 2(a).

Then, in step 113, the film tape 6a is removed.

The lead terminals of the two memories ICl1.12 of 6b are aligned and positioned as shown in FIG. 2(a). Note that this uses two reels of film tapes 8a and 8b on which the two memories ICII and 12 that are the targets of this tape carrier are mounted, one on top and one on the bottom so that they are turned over. This is done by setting it to .

Next, in step 114, the film tape 8 a +6
The corresponding lead terminals 5 of the two memories ICII, 12 of b are joined together. In this case, after alignment, the lower lead terminal 5 will be joined.The method for joining is to plate the upper half of the lead terminal 5 with Sn plating and the lower half with Au plating. If these are separated, an Au-3n junction is formed at the time of bonding. Or lower memory I
When a solder layer is formed by printing on the lead terminal 5 of C, a pbSn junction is formed.

Next, in step 115, for the two memories ICl1.12 obtained in the previous step 114, in which the corresponding lead terminals 5 are joined, the parts of the joined lead terminals 5 are exposed to the outside. A package mold frame divided into two horizontally arranged vertically is mounted from above and below to cover these memory ICs. and,
In step 116, epoxy resin or the like is poured into the package mold frame to perform transfer mold resin sealing. Then, when the package 11 is finally cut out, the second
A memory IC package 15 having two built-in memories ICl1 and 12 as shown in Figure (b) is obtained.

This memory IC package 15 becomes a memory IC with approximately the same area and twice the capacity as the conventional one. Therefore, in step 118, this memory IC package 15 can be mounted on a printed circuit board or used as it is by being transferred to other processes. Note that when mounting on a printed circuit board in step 118, the lead terminals of the cut out package may be simply formed and mounted.

By the way, the film tapes 6a and 8b on which the memories ICII or 12 are mounted are formed by forming lead terminals 5 with Cu foil on a flexible film tape such as polyimide, and forming bumps 3 (Au bumps) on the film tapes 6a and 8b. An IC chip 1 and lead terminals 5 are bonded together. Note that, if necessary, the joint portion between the IC chip 1 and the lead terminals 5 may be covered in advance with a sealing resin.

Here, when two memory ICs are stacked, it is necessary to process the chip select terminal. For example, as shown in FIG. 4 and its enlarged view, the tip of the lead terminal 5 is Lead terminals with branches can be used.

That is, 8 is a chip select terminal among the lead terminals 5, and one of the chip select terminals 8 of the upper and lower memory ICs 11 and 12 mounted on the film tapes 6a and 6b has a punched hole 9, and the other one has a punched hole 9. One is to punch at the position of the punched hole 10 (near the base of the lead terminal) and use only one of the chip select terminals 8 in a conductive state.
The other chip select terminals are made non-conductive. In this way, the film tapes 6a and B disposed above and below
The positions of the chip select terminals 8 of the memory ICII, 12 mounted on the memory ICII, b can be made different. Thereafter, as shown in FIG. 2(a), the lead terminals 5 of the upper memory ICII and the lead terminals 5 of the lower memory IC12 may be aligned.

At this time, the chip select terminals 8 are positioned independently and at different positions in each of the memories ICII and 12 by the punching described above.

The parts where the lead terminals 5 are joined are shown in Fig. 2 (
As shown in b), not from the base of the lead terminal 5,
It is located outside the punched holes 9 and 10. Also, memory I
When C is stacked in two or more stages, the chip select terminals 8 need only be branched by the number of stacked IC chips. Furthermore, the above process includes two film tapes 6a,
This can be done continuously while winding these up on the Elb.

Figure i5 (a) shows that a lead frame made of Fe-N1 alloy, Cu alloy, etc. is interposed between the two film tapes 6a and 8b of Figure 2 (a), and each film tape 8
Memory IC11, 12 installed in ae8b
The lead terminals 5 are shortened and these are respectively joined to both sides of the inner lead portion 7b of the lead terminal 7a formed by the lead frame. In this case,
The chip select terminal 8 is selectively connected to the inner lead portion 7b of one of the polished terminals 7a.

In FIG. 5(b), the film tape 6b side is replaced with the film tape 6a, and two film tapes 8a+6a are used.
Both are turned over, and the lead terminals 5 are joined to each other from positions outside the memory ICs 11 and 12. In addition,
In this case, the IC chips are not mirror images.

As described above, in the embodiment, the lead terminals of two memory ICs are placed on a tape and joined at the top and bottom, but more film tapes may be stacked to make the memory IC multilayered.

Connections between lead terminals are made by connecting corresponding lead terminals except for the chip select terminal, but this is
This does not mean all the lead terminals connected to each electrode of the C chip, and if there is a non-corresponding lead terminal, it is sufficient to connect only the corresponding parts except for the lead terminal.

In addition, the method of joining is, for example, by printing cream solder on the lead terminals of the memory IC of the film tape 6 on the lower side, and using low melting point solder etc. as the solder.
Heating may also be done at a temperature lower than the heat resistant temperature of the film tape.

Although the embodiments mainly describe memory ICs, the present invention is not limited to memory ICs, but can be applied to the manufacturing of semiconductor devices in general.

[Effects of the Invention] As can be understood from the above description, in this invention, when IC chips mounted using a tape carrier method are mounted in multiple stages, the corresponding leads of a plurality of IC chips are removed before separating the ICs from the film tape. Since the terminals are connected and sealed in this state, the IC is in a packaged state and becomes very easy to handle.

As a result, when mounted on a board or the like, alignment with the board is easy and lead terminals are less likely to bend. Also, for other uses, semiconductor devices can be cut out from film tape in packaged form.
The subsequent handling process becomes simple, and a chip multi-stage mounting type semiconductor device can be manufactured with high production efficiency.

[Brief explanation of the drawing]

FIG. 1 is a flowchart of a semiconductor manufacturing process shown in an embodiment of the manufacturing method according to the present invention, and FIG. 2(a),
(b) is a cross-sectional view of a memory IC that is tape-carried in each manufacturing process and a cross-sectional view of a package cut out from the tape carrier; FIG. 3 is a plan view of the memory IC that is tape-carried; and FIG. FIG.
b) is a cross-sectional view of the package cut out in each of the other embodiments, and FIG. 6 is a flowchart of the conventional manufacturing method. DESCRIPTION OF SYMBOLS 1... IC chip, 2... Sealing resin, 3... Bump, 4... Outer lead, 5... Lead terminal, 6...
... Polyimide tape, 7... Lead terminal by lead frame, 8... Chip select terminal, 9... Punching hole, 10-... Punching hole, 11.12... Memory IC, 13... Package, 15...Memory IC package. Patent Applicant Hitachi Maxell Co., Ltd. Agent Patent Attorney Kore Kajiyama

Claims (5)

[Claims] (1) In a method for manufacturing a semiconductor device in which semiconductor chips mounted using a tape carrier method are mounted vertically in multiple stages, tapes carrying the semiconductor chips are arranged one above the other, and each of the tapes mounted on the upper and lower tapes is Corresponding lead terminals connected to the semiconductor chips are electrically connected to each other via a lead member serving as an outer lead or directly, and the plurality of semiconductor chips to which the corresponding lead terminals are connected are sealed. A method for manufacturing a semiconductor device, characterized by: (2) A claim characterized in that corresponding lead terminals connected to each of the semiconductor chips mounted on the upper and lower tapes are directly joined to each other, and the ends of the joined lead terminals serve as outer leads. Item 1. A method for manufacturing a semiconductor device according to item 1. (3) The semiconductor chips arranged on the upper side and the semiconductor chips arranged on the lower side have each electrode other than the chip select electrode in a mirror image relationship, and are connected to the respective electrodes of the upper and lower semiconductor chips. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the leads are arranged and bonded so as to face each other. (4) At least one tip of the lead terminal formed on the tape is formed by branching into multiple branches, and different branches among the branched portions of the lead terminal branched on the tape arranged above and below are formed on the tape. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the tape is cut and the corresponding lead terminals are joined together. (5) The method for manufacturing a semiconductor device according to claim 1 selected from claims 1 to 4, wherein the semiconductor chip is a memory element.