JPH01184587A - Two-dimensional median filter - Google Patents

Abstract

PURPOSE:To perform a fast processing with a simple circuit by detecting the maximum value of an image element signal in a processing targeted area, and executing a procedure to replace the value of an image element having the maximum value by the minimum value. CONSTITUTION:A digital image signal stored in an image signal memory 11 is supplied to a maximum value detector 12 in time series. The maximum value detector 12 detects the maximum value in the digital image signal, and also, detects the input order of the value. The input order detected at the maximum value detector 12 is supplied to a selector 13 in an address generation circuit 16. The selector 13 selects the signal of a counter 4 at the time of executing the detection of the maximum value, and the memory address of the maximum value is generated by an adder 15. The minimum value is written on a generated address. By repeating such operation, an image element with a large value can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a two-dimensional median filter for extracting a pixel signal having a central magnitude value from a plurality of pixel signals in digital image processing.

(Prior Art) Conventionally, in order to extract a signal having a median value from a fixed number of pixel signals with different values, these pixel signals are sorted in the order of their values. A sorting circuit is used to determine the order of magnitude of a plurality of signals and extract the pixel signal with the median value. As a sorting circuit for this purpose, there is a method in which sequentially sent data is sorted each time, extracted as one ordered sequence, and then the central value is extracted. This method takes a long processing time and is difficult to apply to real-time video processing, which requires particularly high-speed processing. Therefore, a method has been proposed in which a histogram is created and a two-dimensional median filter is processed in real time. (I Triple E Transactions on Acoustic Speech and
Signal processing (IE' Trans, on
Acoustics, 5peech, and Si
gnal Processing) vol, As5P-
27°No, 1. Feb, 1979. P13~1B>
The two-dimensional median filter is performed by detecting a signal having a thickness at the center from mxn pixel signals. And a screen of xxy pixels (X, Y>m.

n) Shift the processing target area of m×n pixels one pixel at a time like a rask scan, and execute a median filter for the entire screen by detecting the pixel with the center size for each shifted m×n pixel. . Therefore, first, a histogram representing the magnitude of the signal value of m×n pixels to be processed and the number of pixels for each magnitude is created. Here, the 0th order mX where the number of pixels with a value smaller than the median value is set to 1
When the n-pixel processing target area is shifted one pixel to the right, m pixels at the left end are removed from the area, and m pixels are newly added to the right end. As the pixels change due to this shift of the target area, the histogram is changed, and the number of pixels 1 having a value smaller than the previous median value is determined, which is smaller than the median value. Therefore, a value on the histogram that is one value larger than the histogram median value that is one value smaller than the previous median value on the histogram is approximated by a new median value. By repeating this operation, a two-dimensional median filter is executed for the entire screen.

(Problems to be Solved by the Invention) As already mentioned, there is a method for sorting data sequentially sent by a sorting circuit each time and extracting it as one ordered sequence, and then detecting data having a median size. Processing time will be longer. Further, although the method using a histogram can achieve high speed, it requires complicated memory addressing for the operation of creating a histogram and changing it, and has the problem of increasing the circuit scale.

An object of the present invention is to provide a two-dimensional median filter that can be implemented at high speed and with a simple circuit.

(Means for Solving the Problem) According to the first invention of the present application, an image signal memory that stores digital image signals, and a maximum value and its input order are detected from among the time-series outputs of the image signal memory. and an address generation circuit that uses at least the input order of the maximum value outputted by the maximum value detector and an external signal as input signals to generate an address of the image signal memory. A median filter is obtained.

According to a second invention of the present application, an image signal memory that stores a digital image signal, a minimum detector that detects a minimum value and its input order from among the time-series outputs of the image signal memory, and the minimum value detector A median filter is obtained which is characterized in that it is constituted of at least an address generation circuit which uses at least the input order of the minimum value outputted by the device and an external signal as an input signal and generates an address of the image signal memory.

According to the third invention of the present application, there is provided an image signal memory that stores digital image signals, and a first memory that selects one of the time series output of the image signal memory and the time series output of the first-in first-out memory to be described later. a maximum value detector that detects the maximum value and its input order from among the time series outputs of the first selector, and a first-in, first-out memory that stores the maximum value output from the maximum value detector and one time. and an input order of the maximum value output by the maximum value detector, and an address generation circuit that receives at least an external signal as an input signal and generates an address of the image signal memory;
A two-dimensional median filter with the following characteristics is obtained.

According to the fourth invention of the present application, there is provided an image signal memory that stores digital image signals, and a first memory that selects one of the time series output of the image signal memory and the time series output of the first-in first-out memory to be described later. a selector, a minimum value detector that detects the minimum value and its input order from the time-series output of the first selector, and a first-in, first-out memory that stores the minimum value output by the minimum value detector at one time. and an input order of the minimum value output by the minimum value detector, and an address generation circuit that uses at least an external signal as an input signal and generates an address of the image signal memory. A filter is obtained.

According to the fifth invention of the present application, an image signal memory that stores digital image signals, a time series output of the image signal memory, and one of the outputs of a plurality of first-in first-out memories to be described later are selected. a first selector; a maximum value detector that detects a maximum value and its input order from among the time series outputs of the first selection; a control circuit that resets a part of the storage contents of the first-in, first-out memory according to the input order of the maximum value output by the maximum value detector; and an input order of the maximum value output by the maximum value detector;
A two-dimensional median filter is obtained which is characterized in that it is comprised of at least an external signal and an address generation circuit which uses at least an input signal as an input signal and generates an address of the image signal memory.

According to the sixth invention of the present application, an image signal memory for storing digital image signals, and a first selection of selecting one of the time-series output of the image signal memory and the output of a plurality of first-in, first-out memories. a minimum value detector for detecting the minimum value and its input order from among the time-series outputs of the first selector; and a plurality of first-in, first-out memories for storing the minimum values output by the minimum value detector. , a control circuit that resets a part of the storage contents of the first-in-first-out memory according to the input order of the minimum values output by the minimum value detector; and a control circuit that resets the input order of the minimum values output by the minimum value detector, and A two-dimensional median filter is obtained, which includes at least an address generation circuit that generates an address of the image signal memory as an input signal.

According to the seventh invention of the present application, an image signal memory that stores a digital image signal, a selector that selects either a time-series output of the image signal memory or a first-in, first-out memory output described later; a minimum value/maximum value detector for detecting the minimum value or maximum value from the time series output of the device; a first-in, first-out memory for storing the minimum value or maximum value outputted by the minimum value/maximum value detector; A two-dimensional median filter is obtained, which is characterized in that it includes at least an input signal and an address generation circuit that generates an address of the image signal memory.

(Function) The first invention of the present application detects the maximum value of the pixel signal in the processing target area of m×n pixels, replaces the value of the pixel having the maximum value with the smallest value, and resigns the m×n pixel signal. The purpose is to detect the maximum value of .

It becomes a pixel with a value of magnitude.

The second invention of this application detects the minimum value of the pixel signal in the processing target area of m x n pixels, replaces the value of the pixel with the minimum value with the largest value, and then returns the pixel signal of the m x n pixels. This detects the minimum value of the signal.

The pixel has a value of . According to the first and second inventions, a two-dimensional median filter that does not require complicated memory addressing can be realized with a simple circuit configuration.

The third invention of the present application divides a processing target area of m×n pixels into n columns, detects a pixel having the center size of m pixel signals in each column, and The pixel having the center size is further detected from among the pixels having the center size of each column. In order to detect the pixel with the center size in each column, the maximum value of m pixels is replaced with the value of the pixel with the maximum value to the smallest value, and again the maximum value of the signal of m pixels is Detect values. By repeating this procedure m times, it is possible to detect the pixel having the center size within the column. By repeating the procedure of finding the maximum value among the pixels with the median size in each of the n detected columns and replacing it with the smallest value, further calculations are performed from among the n median values. Pixels with a central thickness can be detected.

A fourth invention of the present application is to obtain a minimum value instead of a maximum value in order to detect a pixel having a central size in the third invention.

According to the third and fourth inventions, a two-dimensional median filter can be realized at high speed by detecting a pixel having a central size from among the median values of each column.

The fifth and sixth inventions of the present application provide a two-dimensional Messian filter in which a processing target area of m x n pixels is shifted horizontally or vertically on a frame screen.
This method utilizes the feature of detecting a pixel with a central size among n pixels.

The fifth invention of the present application detects a pixel having a median size among m pixels in each column, and further detects a pixel having a median size among the m pixels in each column, Detect a pixel with a size of . Here, store each detected pixel having a different center size in a register, mX
When the processing target area of n pixels is shifted by one pixel, for example, in the right horizontal direction, the median value corresponding to the leftmost column is deleted, and the pixel with the center size among the m pixels of the rightmost column is detected, This pixel and n-1 already stored in the register
A pixel having a median size is detected among the respective median values. To find the median value, repeat the process of finding the maximum value and replacing it with the minimum value. According to the present invention, since n-1 of the n separate median values have already been found, the median of at most one column is found, and that value is combined with the n-1 values that have already been found. It is only necessary to detect a pixel having a median size from among the median values of , and processing can be performed at high speed.

A sixth invention of the present application is to repeat the procedure of finding the minimum value and replacing it with the largest value in order to detect the median value in the fifth invention, and can perform processing at high speed.

A seventh invention of the present application is that in the fifth invention, the maximum value of each column is determined instead of the median value of each of the n columns, and the minimum value is determined and output from among the n maximum values. Since n-1 of the n median values have already been found, find the maximum value of at most one column and combine that value with the n-1 maximum values that have already been found. It is sufficient to detect the pixel having the minimum value from among the pixels, and the processing can be performed at high speed.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the first invention of the present application. 11 is an image signal memory, 12 is a maximum value detector, 1
3 is a selector, 14 is a counter, 15 is an adder, 16 is an address generation circuit, 17 is a control circuit, -1 is an input signal line of the image signal memory 11, and 1-2 is an output of the image signal memory 11. Signal lines 1-3 are maximum value output signal lines of the maximum value detector 12; 1-4 are maximum value input rank signal lines of the maximum value detector 12; 1. -5 is an output signal line of the counter 14, 1-6 is an output signal line of the adder 15, 1
-7 is an output signal line of the selector 13, and 1-8 is an input signal line of the adder 15. By addressing the signal of the processing target area of mXn pixels stored in the image signal memory 11 through the input signal line 1-1 of the image signal memory 11 with the output signal line 1-6 of the adder 15. The signal is read out and supplied to the maximum value detector 12 through the output signal line 1-2 of the image signal memory 11.

The maximum value detector 12 outputs the maximum value of the time series input signal supplied from the signal line 1-2 through the signal 1-3, and also outputs the input order of the detected maximum value as the input order of the maximum value. It is supplied to the first input of the selector 13 through the signal line 1-4. The counter 14 outputs a signal counted up or down by 1 to the output signal line 1-5.
is a modulo counter that is output through the selector 13 and supplied to the second input of the selector 13. The selector 13 selects one of the signals inputted through the input rank signal line 1-4 of the maximum value and the output signal line 1-5 of the counter, and sends the selected signal to the adder through the output signal line 1-7. 15 first inputs.

The multi-tot part signal is input to the second input of the adder 15 through the input signal line l-8. When detecting a pixel with a median size among mXn pixels, the counter calculates a number from 0 to mxn-1. Moving the processing area and
The 0 selector 13 increases the value of the external signal input through the input signal lines 1-8 of the adder 15. When performing maximum value detection, the 0 selector 13 selects the signal on the output signal lines 1-5 of the counter 14, and When a value is detected, the signal on the input rank signal line 1-4 of the maximum value of the maximum value detector 12 is selected. Then, by adding the value in the input order of the maximum value and the value of the external signal supplied through the input signal line 1-8, a memory address of the detected maximum value is generated,
The pixel having the most central size at that address can be detected.

The second invention can be realized by using the maximum value detector 12 in FIG. 1 as a minimum value detector.

FIG. 2 is a block diagram showing an embodiment of the third invention of the present application. 2) is an image signal memory; 22 is a first selector; 2)
3 is a maximum value detector, 24 is a counter, 25 is an adder, 2
6 is a second selector, 27 is a first-in first-out memory, 28 is a control circuit, 29 is an address generation circuit, 2-1 is an input signal line of the image signal memory 2), and 2-2 is an image signal memory 2)
2-3 is the output signal line of the first selector 22, 2-4 is the maximum value output signal line of the maximum value detector 23, 2-
5 is an output signal line of the first-in first-out memory 27, 2-6 is the maximum value input priority signal line of the maximum value detector 23, 2-8 is an output signal line of the counter 24, and 2-9 is the second selector 26. Output signal line 2-7 is input signal line of adder 25, 2-1
0 is the output signal line of the adder 25 0 image signal memory 2
) is stored in the 0 image signal memory 2) that stores the image signal input through the input signal line 2-1.
From among the signals of the processing target area of X n pixels, the adder 25
The signal at the specified address is read out through the output signal line 2-10 of the image signal memory 2), and the signal is read out through the output signal line 2-10 of the image signal memory 2).
2 as the first input of the first selector 22. A signal on the output signal line 2-5 of the first-in, first-out memory 27 is supplied as a second input to this first selector. The address generation circuit 29 specifies an address in one of the n columns. To this end, the counter acts as a modulo counter from O to m-1, addressing m pixels within each column. The column is designated by an external signal input from the input signal line 2-7 of the adder 25. At this time,
The second selector 26 selects the signal on the output signal line 28 of the counter 24. The first selector 22 also selects the signal on the output signal line 2-2 and supplies it to the maximum value detector 23 through the output signal line 2-3 of the first selector 22.

The maximum value detector 23 detects the maximum value and its input order from among the time series input signals supplied through the output signal line 2-3, and supplies the maximum value to the first-in, first-out memory 27 through the maximum value output signal line 2-4. and memorize it. The input rank of the detected maximum value is sent to the second selector 2 through the input rank signal line 2-6.
Supply to 6.

This input priority signal line indicates the address in the column of the image signal memory 2) where the detected maximum value signal is stored.
When the maximum value in the column is detected, the second selector 26 selects the signal on the signal line 2-6 in the input order and supplies it to the adder 25 through the signal line 2-9. Furthermore, the adder 25
-10 and is supplied as the address of the image signal memory 2).

The signal of this address, that is, the detected maximum value, is replaced with the smallest value, and the median value 1 of each column where the maximum value of m pixels was detected is again stored in the first-in, first-out memory 27 through the signal line 2-4.

Next, the address of one of the n columns is designated by inputting it to the value m adder 25 through the input signal line 2-7. Then, using the same procedure, a value having the size / at the center of this column is detected. This operation is repeated n times to detect all median values of n columns and store them in the first-in, first-out memory 27.

After storing all median values of n columns, the first selector 22 selects the output signal 1! of the first-in-first-out memory 27.
! The maximum value detector 23, which selects signals 2-5, sequentially inputs the contents of the first-in, first-out memory 27 and detects the maximum value therein. The detected maximum value is rewritten to the minimum value. For this purpose, the first-in, first-out memory 27 has a reset function of rewriting the maximum value to the smallest value by the signal on the input priority signal line 2-6 of the maximum value.

The fourth invention can be realized by replacing the maximum value detector 23 in FIG. 2 with a minimum value detector.

FIG. 3 is a block diagram showing an embodiment of the fifth invention of the present application.

31 is an image signal memory, 32 is a first selector, 33 is a maximum value detector, and 34, 36, and 313 are first and second selectors, respectively.
, the third data clear function is first-in first-out memory, 3
14 is a first-in first-out memory control circuit, 38 is a second selector, 39 is a counter, 310 is an adder, 311 is a control circuit, 312 is an address generation circuit, 3-1 is an input signal line of the image signal memory 31, 3- 2 is an output signal line of the image signal memory 31, 3-3 is an output signal line of the first selector 32,
...3-4 is the maximum value output signal line of the maximum value detector 33,
3-11 is the maximum value input ranking signal line of the maximum value detector 33;
3-5.3-9.3-8 are first, second and third first-in first-out memory control signal lines, 3-16.3-1
7. 3-18 are output signal lines of the first, second and third first-in-first-out memories, 3-12 is an output signal line of the counter 39, 3-13 is an output signal line of the second selector 38, 3 -14 is an input signal line of the adder 310, and 3-15 is an output signal line of the adder 310. The 0 image signal memory 31 stores the image signal input through the signal line 3-1.

Adder 310 specifies the address of image signal memory 31 through output signal line 3-15. Every time this address is searched, mX to be processed from the image signal memory 31
The pixel signal from the 0 image signal memory 31 from which the n pixel signal is read is the output signal! 13-2 as the first input of the first selector 32. Address generation circuit 312 specifies an address indicating a specific pixel among mXn pixels. For this purpose, the counter 39 is set from 0 to m-1
It works as a modulo counter that counts up to m pixels in each column.
It is designated by an external signal input from the 10 input signal lines 3-14. At this time, the second selector 38 selects the signal on the output signal line 3-12 of the counter 39. Further, the first selector 32 selects the signal on the output signal line 3-2. Therefore, the image signals sequentially read out from the image signal memory 31, that is, the time-series input signals, are supplied to the maximum value detector 33 via the second selector 32. The maximum value detector 33 detects the maximum value and its input order from among the time-series input signals input through the signal line 3-3.

The input order of the detected maximum value is transmitted to the input order signal line 3-1.
When the maximum value detector 33 detects the maximum value in the 0 column through 1 and fed to the second selector 38, the second selector 38 selects the signal on the signal line 3-11 and selects the signal on the signal line 3-11. The adder 310 is fed through line 3-13. The adder 310 supplies an address to the image signal memory 31 through the signal line 3-15. This address is stored in the image signal memory 3 where the detected maximum value is stored.
The smallest value is written to this address, which indicates the address of 1, and the detected maximum value is replaced with the smallest value.

When this process is performed again for m pixels, the next largest value is found. This procedure is repeated several times, and the maximum value obtained the second time becomes the pixel having the size at the center of this column.

The maximum value of the pixel signal having the size at the center of the detected column is stored in the first, second, and third first-in, first-out memories 34, 36, and 313 through the signal line 3-4. Said first, second and third first-in first-out memories 34.36.3
13 stores the pixel signal having the center value in each of the other n-1 columns that have already been calculated. The first selector 32 selects the signal on the signal line 3-7 and supplies it to the maximum value detector.

At this time, the selected first-in first-out memory is
The first-in first-out memory 34 is assumed to be a first-in first-out memory 34. Among the n output signals of the first-in, first-out memory 34, a pixel signal having a central magnitude is determined by the method of determining the maximum value and removing it as described above. This is the median filter execution result for m×n pixels. When the aforementioned mXn pixel processing area is shifted by one pixel and a median filter is executed on the new area, the median value of the newly added m pixels is calculated and is stored in the three first-in, first-out memories 34. 36.
313, and the median value among the output signals of the second first-in, first-out memory 36 is determined. This is because the signals stored in the first first-in, first-out memory 34 are partially erased when the median filter of the pre-processing screen is executed. Here, the number of first-in, first-out memories is equal to the number of columns n in the processing area, and this embodiment shows the case where n=3.

By replacing the maximum value detector of this embodiment with a minimum value detector, a sixth embodiment of the invention can be obtained.

FIG. 4 is a block diagram showing an embodiment of the seventh invention of the present application. 41 is an image signal memory, 42 is a selector, 43 is a minimum/maximum value detector, 44 is a first-in first-out memory, 48 is a counter, 49 is an adder, 410 is a control circuit, and 4-1 is an input signal of the image memory 41 4-2 is the output signal line of the image signal memory 41, 4-3 is the output signal line of the selector 42, and 4-4 is the minimum value or maximum value output signal line of the minimum value maximum value detector 43. , 4-5 are the output signal lines of the first-in first-out memory 44, and 4-12 are the counters 48.
4-11 is an input signal line of the adder 49, and 4-13 is an output signal line of the adder 49. The image signal memory 41 is input through the signal line 4-1.
Out of the mXn pixel signals to be processed of the image signals stored in the adder 49, the signal at the specified address is read out through the output signal line 4-13 of the adder 49, and the signal at the designated address is read out through the signal line 4-2 to the selector. 42. The selector 42 selects the signal line 4-2 and inputs the signal to the minimum value/maximum value detector 43 through the signal line 4-3. The minimum value/maximum value detector 43 finds the maximum value of n pixels in a column inputted in time series, and stores it in the first-in, first-out memory 44 . The first-in, first-out memory 44 stores the maximum value of the (n-1) column that has already been detected. Here, the selector is the first-in first-out memory 44
The signal on the output signal line 4-5 is selected, and the minimum value among the n maximum values stored therein in the n columns is determined. This is the value to be found. Here, we calculated the maximum value of each column and the minimum value among them, but we calculated the minimum value of each column,
You can also find the maximum value among them.

(Effects of the Invention) According to the first and second inventions of the present application, by using a maximum value detector or a minimum value detector, an image signal memory, and a simple address generation circuit, a complicated address circuit that was previously required can be solved. It is possible to realize a two-dimensional median filter that does not require a sorting circuit or a sorting circuit.

According to the third and fourth inventions of the present application, mX to be treated
By dividing an n pixel signal into n pixel columns, finding the median value for each column, and then finding the median of those n median values, a two-dimensional median filter can be realized at high speed with simple hardware. can.

According to the fifth, sixth, and seventh inventions of the present application, processing of the n-1 column among the n columns is performed by shifting the m×n pixel area on which the median filter processing is performed pixel by pixel. By using what has already been calculated, a two-dimensional median filter can be realized with simple hardware and at extremely high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the first invention, FIG. 2 is a block diagram showing an embodiment of the third invention, and FIG. 3 is a block diagram showing an embodiment of the fifth invention.
FIG. 4 is a block diagram showing an embodiment of the seventh invention. FIG. 4 is a block diagram showing an embodiment of the seventh invention. 11.12, 13.41... Image signal memory 1
2.23,33. ...... Maximum value detector 16
．． 29,312.411...Address generation circuit・27
．． 44・・・・・・・・・・・・・・・First in first out memory 34・−・・・・・・・・・・・・・・・・・・・
First first-in first-out memory 36...
......Second first-in first-out memory 313
・・・・・・・・・・・・・・・・・・Third first-in first-out memory.

Claims (7)

[Claims] (1) An image signal memory that stores digital image signals, a maximum value detector that detects the maximum value and its input order from among the time-series outputs of the image signal memory, and a maximum value that the maximum value detector outputs. 1. A median filter comprising at least an address generation circuit that takes at least an input order of input signals and an external signal as an input signal and generates an address of the image signal memory. (2) an image signal memory that stores a digital image signal; a minimum value detector that detects a minimum value and its input order from among the time-series outputs of the image signal memory; and a minimum value that the minimum value detector outputs; 1. A median filter comprising at least an address generation circuit that takes at least an input order of input signals and an external signal as an input signal and generates an address of the image signal memory. (3) an image signal memory that stores digital image signals; a first selector that selects one of the time-series output of the image signal memory and the time-series output of the first-in, first-out memory to be described later; a maximum value detector that detects the maximum value and its input order from the time series output of the selector No. 1; a first-in, first-out memory that temporarily stores the maximum value output from the maximum value detector; A two-dimensional median filter comprising at least an input order of a maximum value to be output, and an address generation circuit that uses at least an external signal as an input signal and generates an address of the image signal memory. (4) an image signal memory that stores digital image signals; a first selector that selects one of the time-series output of the image signal memory and the time-series output of the first-in, first-out memory to be described later; a minimum value detector for detecting the minimum value and its input order from among the time series outputs of the selector No. 1; a first-in, first-out memory for storing the minimum value output from the minimum value detector; and the minimum value detector; A two-dimensional median filter comprising at least an input order of the minimum value outputted by the filter, and an address generation circuit that uses at least an external signal as an input signal and generates an address of the image signal memory. (5) an image signal memory that stores a digital image signal; a first selector that selects one of the time-series output of the image signal memory and the output of a plurality of first-in, first-out memories to be described later; a maximum value detector that detects the maximum value and its input order from among the time-series outputs of the first selector;
a plurality of first-in, first-out memories that store the maximum values output by the maximum value detector; a control circuit that resets a part of the stored contents of the first-in, first-out memories according to the input order of the maximum values output by the maximum value detector; A two-dimensional median filter comprising at least an input order of a maximum value output by a maximum value detector, an external signal, and an address generation circuit that uses at least an input signal to generate an address of the image signal memory. (6) an image signal memory that stores a digital image signal; a first selector that selects one of the time-series output of the image signal memory and the output of a plurality of first-in, first-out memories; a minimum value detector for detecting the minimum value and its input order from among the time series outputs of the selector; a plurality of first-in, first-out memories for storing the minimum value output by the minimum value detector; and the minimum value detector. A control circuit resets a part of the stored contents of the first-in-first-out memory according to the input order of the minimum value output by the minimum value detector, and the input order of the minimum value output by the minimum value detector is determined by using an external signal as at least the input signal and the image signal. A two-dimensional median filter comprising at least an address generation circuit that generates a memory address. (7) an image signal memory that stores digital image signals, and a selector that selects either a time-series output of the image signal memory or a first-in first-out memory output described later;
a minimum value maximum value detector for detecting the minimum value or maximum value from the time series output of the selector; a first-in first-out memory storing the minimum value or maximum value output by the minimum value maximum value detector; and an external signal. A two-dimensional median filter, characterized in that it is configured of at least an address generation circuit that takes at least an input signal as an input signal and generates an address of the image signal memory.