JPH01179454A - Heterojunction semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To lessen extremely the sheet resistance between an emitter wiring and to realize a high emitter efficiency, a high carrier speed and a high collector breakdown strength by a method wherein the emitter, which needs a buried wiring, is backed by a low-resistance Si layer. CONSTITUTION:A heterojunction semiconductor device is constituted into a structure; wherein a high concentration emitter (GaP epitaxial layer) comes into contact with a high-concentration base layer 10 and moreover, an impurity distribution in the base is decreased steeply from the side of the emitter 2 toward the side of a collector region 5; and a high emitter injection efficiency, a low base resistance, a high-speed carrier traveling and a high collector breakdown strength are satisfied simultaneously. Moreover, as the emitter is also used by backing the high-concentration GaP epitaxial layer 2 by a low-resistance Si layer 13, this contact resistance and the sheet resistance between the emitter and a metallic wiring (third oxide film) 12 are also very small. As the layer 2 is located on a high-resistance Si substrate 1, an emitter capacitance can be also lessened sufficiently, it is effective for the high-speed operation of a device and moreover, the device is low in cost as consisting of Si.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same.

[Conventional technology]

In bipolar transistors capable of high-speed switching operations, a so-called hetero-bipolar transistor has been proposed, which uses a heterojunction with a wider forbidden band width on the emitter side than on the base side for the emitter-base junction in order to improve emitter efficiency. ing. In hetero bipolar transistors, in order to achieve high-speed operation, it is effective to make the minority carriers injected from the emitter travel in the base region in the state of so-called hot carriers, and for this purpose, the emitter-base junction is made an ablative junction. There is a need.

Furthermore, the emitter-base band offset can be used to improve emitter injection efficiency and reduce base resistance at the same time.

[Problem that the invention seeks to solve]

However, in order to obtain the high emitter current necessary for high-speed operation, the impurity concentration of the emitter needs to be as high as that of the base, and the highly doped emitter and the highly doped base form an ablative junction. Therefore, if a high density of interface states exists at the emitter-base boundary, the interband tunnel recombination current through this interface state will increase, and the predicted emitter injection efficiency cannot be achieved. .

In fact, in conventional hetero-bipolar transistors, misfit dislocations occur due to mismatch in lattice constants and differences in thermal expansion coefficients at the hetero interface during heteroepitaxial growth, and these become centers of interband tunnel recombination of carriers. , there was a problem that device characteristics were adversely affected. Also, although it is true that as a single device it has higher performance than a conventional homogeneous bipolar transistor, when a heterogeneous bipolar transistor is applied to an integrated circuit, unless efforts are made to reduce the parasitic element effects similar to homogeneous bipolar transistors, the circuit There was also the problem that no significant improvement could be expected from a delay perspective.

An object of the present invention is to overcome such drawbacks of hetero bipolar transistors, to provide a device structure that is capable of high-speed operation, and can suppress parasitic element effects, and a manufacturing method for realizing a device with such a structure. be.

[Means for solving problems]

a high-concentration region of a conductivity type opposite to that of the substrate formed on a high-resistance semiconductor substrate made of a semiconductor; and a second semiconductor formed on the high-concentration region and having a wider forbidden band width than the first semiconductor. an emitter layer of a high concentration region having the same conductivity type as the high concentration region, and a third semiconductor formed on the emitter layer and having a narrower forbidden band width than the second semiconductor, and having conductivity opposite to that of the emitter layer. a base layer formed of a high concentration region whose concentration decreases sharply in a direction away from the interface with the emitter region; and a base layer opposite to the base layer formed on the base layer and having a constant impurity distribution. The present invention is a heterojunction bipolar transistor characterized by having a collector layer made of a conductive semiconductor, and a collector electrode wiring layer that is in contact with the collector layer through an insulating layer having a window on the collector layer.

Further, in the method for manufacturing a semiconductor device of the present invention, a high concentration region of a conductivity type opposite to that of the substrate is formed on a high resistance semiconductor substrate made of a first semiconductor having a narrow bandgap; a step of heteroepitaxially growing an emitter region made of a second semiconductor having a wider forbidden band width than the semiconductor and having a high concentration impurity of the same conductivity type as the high concentration region;
An element isolation trench groove is formed in a third semiconductor substrate having a narrower forbidden band width than the second semiconductor substrate, the trench is filled halfway down with a first oxide film, and the second semiconductor substrate is formed by high-acceleration ion implantation. The end of the deepest part of the impurity distribution to achieve the same conductivity type as the high concentration epitaxial region of the semiconductor is deeper than the bottom of the oxide film of the element isolation trench, and the end of the shallowest part is of the element isolation layer. The first polysilicon is implanted to be shallower than the bottom, and the first polysilicon is deposited by the CVD method, and the first polysilicon is implanted by ion implantation to realize a conductivity type different from that of the high concentration epitaxial region of the second semiconductor, and the second semiconductor is ion-implanted and heat treated. The polysilicon layer is doped with impurities, a second oxide film is deposited using the CVD method to a thickness such that its top is lower than the top of the trench, the second polysilicon is deposited on the entire surface using the CVD method, and one-selective polishing is performed. a step of completely removing the second polysilicon and flattening the surface, a step of bonding the first semiconductor substrate and the third semiconductor substrate, and a step of removing the third semiconductor substrate by a selective polishing method. A third oxide film is formed by a CVD method, a contact hole is formed by a lithography process, an electrode wiring layer is formed, and a third oxide film is removed by a lithography process. 1. A method for manufacturing a heterojunction bipolar transistor, comprising a step of forming electrode wiring.

[Effect]

Next, the structural principle of the semiconductor device having the structure of the present invention will be explained. The hetero bipolar transistor of the present invention is
As shown in Fig. 3, the high concentration emitter and the high concentration base are in contact with each other, and the impurity distribution in the base decreases sharply from the emitter side to the collector side, resulting in high emitter injection efficiency, low paste resistance, High-speed carrier running and high collector voltage resistance can be satisfied at the same time. The former two are contributed by the high concentration at the emitter end of the base, and the latter two are contributed by the low concentration at the collector end of the base. In addition, the hetero bipolar transistor of the present invention has an emitter on the substrate side and a collector on the surface side, and the upper part of the collector is in direct contact with the electrode wiring layer, so the high speed operation of the emitter top type hetero bipolar transistor is inhibited. In addition, the emitter is in contact with a low resistance layer that has the same conductivity type as the emitter and has a narrow forbidden band width, and beyond that is a high resistance substrate, so the emitter substrate can be removed. Both the capacitance and the embedded wiring layer resistance of the emitter in the substrate are extremely small, and the high speed performance of the hetero bipolar transistor can be fully utilized in an integrated circuit.

Next, the principle of the method for manufacturing a hetero bipolar transistor of the present invention will be explained. When forming a collector top type hetero bipolar transistor based on the conventional hetero epitaxial growth method, it is necessary to grow two layers, a base layer and a collector layer, and the thickness of the hetero growth film is quite thick. This resulted in the impurity type having to be changed twice during the process.

There are difficulties in crystal growth, such as redistribution of impurities and a decrease in crystallinity. The only hetero-growth method that can satisfy such requirements is the MBE method, but this method has problems in terms of throughput and manufacturing cost. In addition, particularly in Si-based hetero bipolar transistors, there is also the problem that it is difficult to realize a good hetero interface because the hetero emitter material with a similar lattice constant is not GaP L/. One of the features of the manufacturing method of the present invention is that a heteroepitaxial growth method is used to form a junction between a low resistance layer and an emitter layer on a high resistance substrate to realize a heterojunction. be. In the heteroepitaxial growth method, by providing a buffer layer made of a strained superlattice at the hetero interface, it is possible to concentrate the hetero mismatch at the interface and instead improve the crystallinity within the upper epitaxial layer. Although this method is used as an effective means, it cannot be used for hetero bipolar transistors where the quality of the hetero interface is sensitively reflected in the device characteristics. Since it is used in a place where there is no need to view it as a problem, the hetero-growth method using the above-mentioned buffer layer formation can be used, and the crystallinity of the emitter surface can be improved. The emitter and the collector/base region are manufactured separately on different types of semiconductor substrates, and after the surfaces of both are planarized, a bonding technique is used. Another feature is
After such bonding, the semiconductor substrate on the collector side, which is originally unnecessary, is removed in order to completely eliminate the collector/substrate capacitance that impedes high-speed operation of the hetero-bipolar transistor integrated circuit.

By such a manufacturing method, a semiconductor device having the structure of the present invention can be reliably realized.

〔Example〕

Hereinafter, a typical embodiment of the structure and manufacturing method of a semiconductor device using the present invention will be explained using a series of process diagrams shown in FIGS. 2(a) to (2) and a structural diagram shown in FIG. do.

Figure 2 (a) shows surface orientation (100) and impurity concentration 5X10.
1', 2500 layers of low resistance layer 13 with phosphorus concentration I x 101020a" were formed, and after lamp annealing, 2000 layers of high concentration n-type GaP epitaxial layer 2 with SL concentration 3 x 10" -1 was formed. be. On the other hand, as shown in Figure 2(b), the plane orientation (IOO) and the impurity concentration are 5X.
A CVD nitride film 3 was deposited on the entire surface of the p-type Si substrate 4 of 1015(7)-3 by 2000 layers, and this was further patterned, and using this as a mask, the substrate 4 was etched by about 1000 layers to form grooves. and further CVD nitriding 11u3
After depositing 500 layers, the CVD nitride film 3 is etched by the RIE method to form a so-called sidewall to obtain the structure shown in FIG. 2(b). Next, using the CVD nitride film 3 as a mask, the trench is further deepened by RIE to form element isolation trenches with a total depth of 3000 as shown in FIG. 2(c). Next, a first oxide film 6 is formed by thermally oxidizing the lower part of the trench sidewall and the trench bottom by approximately 900 people using the LOGO3 oxidation method, and the nitride film 3 is further removed, and the projection range is increased to approximately 3000 by using the high acceleration ion implantation method.
As ions were implanted at a peak concentration of 5 x 10''an-', and the As was activated by lamp annealing.

A collector region 5 is formed to obtain the structure shown in FIG. 2(c).

Next, approximately 900 boron-doped polysilicon layers are deposited by CVD to form a first polysilicon layer 9.
A second oxide film 8 is formed by depositing 900 oxide films by the CVD method, and a second polysilicon layer 7 is formed by the CVD method to obtain the structure shown in FIG. 2(d). get. Next, the second polysilicon layer 7 is polished by a single selective polishing method. Since the selective polishing method is used, the polishing rate becomes extremely slow at the upper end of the field portion of the second oxide film 8, and polishing virtually ends there, so that a flat structure can be obtained with good control. At this time, the second oxide film 8 and the first polysilicon layer 9 on the device are completely scraped off, and they stop in the middle of the Si substrate 4 (Fig. 2(e)).
). Next, the Si surface is oxidized by lamp oxidation for about 400 hours. At this time, since the first polysilicon layer 9 is exposed around the island-shaped silicon region, this portion is also oxidized. Since this portion is highly doped, if the conditions are selected, it is possible to achieve a situation where the oxidation rate is faster than that of the Si substrate 4. Therefore, next, by etching the oxide film using the RIE method, a situation can be realized in which the oxide film is completely removed on the Si substrate 4 and the oxide film remains on the first polysilicon layer 9. . Next, using the oxide film as a mask, the Si substrate 4 is
The impurity concentration I
A base layer 10 made of boron-doped silicon of 10"an-' is formed to backfill the trench. At this time,
Since the first polysilicon layer 9 around the island-shaped silicon region is covered with an oxide film, selective epitaxial silicon does not grow in this portion.

The base layer 10 and the first polysilicon layer 9 are in electrical contact at a portion below the edge of the oxide film. Since selective epitaxial growth is performed with good flatness, the surface of the silicon substrate is almost flat at this time. Next, the Si substrate 4 and the high-resistance SL substrate 1 on which the GaP epitaxial layer 2 is placed are bonded together by thermal bonding while aligning their in-plane axes, as shown in FIG.
Obtain the structure of f). Next, by selective polishing again, Si
Polishing of the substrate 4 from below is stopped by the lower part of the chemical film 6 acting as a stopper (FIG. 2 (2)). Since the peak position of the As concentration in the collector region 5 is aligned in advance with the upper part of the first oxide film 6, the highest concentration portion of the collector region 5 is exposed after polishing. Next, the substrate is turned upside down, the first oxide film 6 and the first polysilicon layer 9 are patterned by a lithography process, and the first polysilicon layer 9 around the device is removed. Next, a trench groove is formed by a lithography process, and emitter isolation is performed. Next, a third oxide film 12 is formed by a CVD method, and a wiring metal layer 11 is formed by a contact hole formation process and a wiring formation process. death,
The final device structure shown in FIG. 1 is obtained. In view of the above steps, in the step of forming the hetero bipolar device section, the mask step is only performed once for the initial pattern formation of the nitride film 3, and the device can be formed completely on a self-line.

Since the temperature of thermal bonding is about 400 to 500℃, GaP
There is little redistribution of impurities in the emitter and in the Si-based collector. Moreover, since SL and GaP have good lattice matching, it is possible to significantly reduce the interface states compared to when using the conventional heteroepitaxial growth method.
Therefore, despite the collector top structure, it is possible to realize an impurity profile in which the concentration is maximum near the interface on the emitter side within the base, and at the same time obtain high emitter efficiency. Furthermore, an electrode can be formed in the collector region 5 at the highest concentration point, which is effective in significantly reducing collector contact resistance. Both the intrinsic base (base layer 10) and the extrinsic base (first polysilicon layer 9) are highly doped, and there is no problem in contacting them. Further, since the emitter is also used by backing the high concentration GaP epitaxial layer 2 with the Si low resistance layer 13, the contact resistance and the sheet resistance up to the metal wiring 12 are also extremely small. Since the GaP epitaxial layer 2 is on the high-resistance SL substrate 1, the emitter capacitance can be made sufficiently small, which is effective for high-speed operation of the device.
Moreover, since the substrate is made of Si, it is inexpensive.

Further, the GaP epitaxial layer only needs to be grown over the entire surface of the substrate, and microfabrication technology is not necessary for the GaP epitaxial layer. Furthermore, since GaP exists only as an intermediate layer after thermal bonding, it can be brought into the SL process again, and there are no problems such as contamination during contact formation or wiring formation. Therefore, the device dimensions are completely determined only by the microfabrication technology in the Si process, which has a great effect on high integration.

〔Effect of the invention〕

As described above, according to the hetero bipolar transistor of the present invention, the impurity distribution in the base is made high in concentration near the interface on the emitter side and sharply decreases toward the collector side, thereby achieving high emitter efficiency. Achieves high carrier speed, high collector pressure resistance, and
Although there is no inter-substrate capacitance at all, an emitter-to-substrate capacitance is added instead, but since the emitter is formed on a high-resistance semiconductor substrate, this is sufficiently small and the emitter-base-collector capacitance is small. Low contact resistance has been achieved for all terminals, and the emitter, which only requires embedded wiring, is lined with a low-resistance silicon layer, so the emitter wiring sheet resistance can be extremely low, allowing ultra-high-speed logic It exhibits outstanding effects in forming integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing an embodiment of the hetero bipolar transistor of the present invention, and FIGS. 2 (a) to (2) are a series of steps showing an embodiment of the method for manufacturing the hetero bipolar transistor of the present invention. 3 are conceptual diagrams showing the principle of a hetero bipolar transistor having the structure of the present invention.

Claims (2)

[Claims] (1) a high-concentration region of a conductivity type opposite to that of the substrate formed on a high-resistance semiconductor substrate made of a first semiconductor with a narrow band gap, and a high-concentration region formed on the high-concentration region and made of a first semiconductor; an emitter layer of a high concentration region made of a second semiconductor having a wider forbidden band width and having the same conductivity type as the high concentration region; and a third emitter layer formed on the emitter layer and having a narrower forbidden band width than the second semiconductor. a base layer consisting of a high concentration region having a conductivity type opposite to that of the emitter layer and whose concentration decreases sharply in a direction away from the interface with the emitter region; a collector layer made of a semiconductor of a conductivity type opposite to that of the base layer, which has an impurity distribution of Heterojunction semiconductor device. (2) A high-concentration region of a conductivity type opposite to that of the substrate is formed on a high-resistance semiconductor substrate made of a first semiconductor with a narrow band gap, and a second semiconductor substrate with a band gap wider than that of the first semiconductor is further formed. a step of heteroepitaxially growing an emitter region made of a semiconductor and having a high concentration impurity of the same conductivity type as the high concentration region; form a groove,
The trench is filled halfway down with the first oxide film, and by high-acceleration ion implantation, an impurity that achieves the same conductivity type as the highly doped epitaxial region of the second semiconductor is implanted so that the deepest end of the distribution is between the elements. depositing first polysilicon by a CVD method by implanting the first polysilicon to be deeper than the bottom of the oxide film of the isolation trench and so that the end of the shallowest part is shallower than the bottom of the inter-element isolation layer;
The polysilicon layer is doped with an impurity by ion implantation and heat treatment to achieve a conductivity type different from that of the high-concentration epitaxial region of the second semiconductor by ion implantation, and a second oxide film is formed on the top by CVD. depositing the second polysilicon to a thickness lower than the top of the groove, depositing second polysilicon on the entire surface by CVD, removing the second polysilicon from the entire surface and flattening the surface by selective polishing; a step of bonding the first semiconductor substrate and the third semiconductor substrate, and removing the third semiconductor substrate by selectively polishing it to the interface with the first oxide film by a selective polishing method, and removing the third semiconductor substrate by a CVD method. A method for manufacturing a heterojunction semiconductor device, comprising the steps of: forming a third oxide film by a lithography process, forming a contact hole by a lithography process, forming an electrode wiring layer, and forming an electrode wiring by a lithography process. .