JPH01179452A - Heterojunction semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize a high emitter efficiency, a high carrier speed and a high collector breakdown strength by a method wherein the title device is constituted into a structure, wherein an impurity distribution in a base is set into a high concentration in the vicinity of an interface on the side of an emitter and is decreased steeply toward the side of a collector. CONSTITUTION:A heterojunction semiconductor device is constituted into a structure, wherein an impurity distribution in a base 10 is reduced steeply from the side of a high concentration emitter (GaP epitaxial layer) 2 toward the side of a collector region 5, and a high emitter injection efficiency, a low base resistance, a high-speed carrier traveling and a high collector breakdown strength are satisfied simultaneously. The former both are contributed by a fact that the concentration of the base 10 is high at the ends of the emitter and the latter both are contributed by a fact that the concentration of the base is low at the ends of the collector. Moreover, as the side of a sapphire substrate 1, which is an insulator, is the emitter, an emitter-substrate capacity is sufficiently small and the surface side is the collector and comes into contact directly with an electrode wiring layer at the upper part of the collector, a collector-substrate capacity can be removed. Moreover, as the emitter is an epitaxial layer on the insulator substrate, carriers are completely depleted in the substrate, an emitter- substrate capacity is very small and the high-speed efficiency of a heterobipolar transistor can be fulfilled sufficiently in an integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same.

[Conventional technology]

In bipolar transistors capable of high-speed switching operations, a so-called hetero-bipolar transistor has been proposed, which uses a heterojunction between the emitter and base, where the forbidden band width is larger on the emitter side than on the base side, in order to improve emitter efficiency. There is. In order to achieve high-speed operation in a hetero bipolar transistor, it is effective to make the minority carriers injected from the emitter travel in the base region in the state of so-called hot carriers, and for this purpose, the emitter-base junction needs to be an ablative junction. There is. Furthermore, the emitter-base band offset can be used to improve emitter injection efficiency and reduce base resistance at the same time.

[Problem that the invention seeks to solve]

However, in order to obtain the high emitter current necessary for high-speed operation, the impurity concentration of the emitter needs to be as high as that of the base, and the highly doped emitter and the highly doped base form an ablative junction.

Therefore, if a high density of interface states exists at the emitter-base boundary, the interband tunnel recombination current through this interface state will increase, and the predicted emitter injection efficiency cannot be achieved. . In fact, in conventional hetero-bipolar transistors, misfit dislocations occur due to mismatch in lattice constants and differences in thermal expansion coefficients at the hetero interface during heteroepitaxial growth, and these become centers of interband tunnel recombination of carriers. , there was a problem that device characteristics were adversely affected. Also, although it is true that as a single device it has higher performance than a conventional homogeneous bipolar transistor, when a heterogeneous bipolar transistor is applied to an integrated circuit, unless efforts are made to reduce the parasitic element effects similar to homogeneous bipolar transistors, the circuit There was also the problem that no significant improvement could be expected from a delay perspective.

An object of the present invention is to overcome such drawbacks of hetero bipolar transistors, to provide a device structure that is capable of high-speed operation, and can suppress parasitic element effects, and a manufacturing method for realizing a device with such a structure. .

[Means for solving problems]

The semiconductor device of the present invention includes an emitter layer made of a first semiconductor with a high impurity concentration formed on an insulating substrate, and a second emitter layer formed on the emitter and having a narrower bandgap than the first semiconductor. a base layer made of a semiconductor and having a conductivity type opposite to that of the high concentration region and whose concentration decreases steeply in a direction away from the interface with the high concentration region; and a base layer formed on the base layer. , a collector layer made of a semiconductor of a conductivity type opposite to that of the base layer and having a certain impurity distribution, and a collector electrode wiring layer formed on the collector layer in contact with the collector layer via an insulating layer with a window. A heterojunction bipolar transistor characterized by having the following features.

Further, the method for manufacturing a semiconductor device of the present invention includes a step of epitaxially growing a high impurity concentration region made of a first semiconductor on an insulating substrate; An element isolation trench groove is formed in a substrate made of a semiconductor of An impurity to achieve this is implanted so that the end of the deepest part of the distribution is deeper than the bottom of the oxide film of the isolation trench, and the end of the shallowest part is shallower than the bottom of the isolation layer. depositing a first polysilicon layer by ion implantation method and doping an impurity into the polysilicon layer by heat treatment to achieve a conductivity type different from that of the high concentration epitaxial region of the first semiconductor by ion implantation method; A second oxide film is deposited to a thickness such that its top is lower than the top of the trench, a second polysilicon is deposited on the entire surface using a CVD method, and the second polysilicon is completely removed using a selective polishing method. a step of planarizing the surface, a step of bonding the insulating substrate and the semiconductor substrate, and selectively polishing the semiconductor substrate to the interface with the first oxide film using a one-selective polishing method; A heterojunction bipolar transistor comprising the steps of forming a third oxide film by a CVD method, forming a contact hole by a lithography process, forming an electrode wiring layer, and forming an electrode wiring by a lithography process. This is the manufacturing method.

[Effect]

Next, the structural principle of the semiconductor device having the structure of the present invention will be explained. The hetero bipolar transistor of the present invention is
As shown in Figure 3, the highly concentrated emitter and highly concentrated base are in contact with each other, and the impurity distribution in the base decreases sharply from the emitter side to the collector side, resulting in high emitter injection efficiency, low base resistance, and high speed. Carrier running and high collector voltage resistance can be satisfied at the same time. The former two are contributed by the high concentration at the emitter end of the base, and the latter two are contributed by the low concentration at the collector end of the base.

In addition, the hetero bipolar transistor of the present invention has an emitter on the substrate side and a collector on the front side, and the upper part of the collector is in direct contact with the electrode wiring layer, so the hetero bipolar transistor of the emitter top type does not inhibit high-speed operation. The capacitance between the collector and substrate can be removed, and since the emitter is an epitaxial layer on an insulating substrate, the substrate is completely depleted of carriers, and the emitter-substrate capacitance is extremely small, making it possible to realize high-speed hetero bipolar transistors. The characteristics can be fully demonstrated in integrated circuits.

Next, the principle of the method for manufacturing a hetero bipolar transistor of the present invention will be explained. When forming a collector-top type hetero bipolar transistor based on the conventional heteroepitaxial long-forming method, two layers, a base layer and a collector layer, must be grown, and the thickness of the hetero-grown film is quite large. This resulted in a thick product, and the impurity mold had to be changed twice during the process.
There are difficulties in crystal growth, such as redistribution of impurities and a decrease in crystallinity. The MBE method is the only hetero-growth method that can satisfy such requirements.

This poses problems in terms of throughput and manufacturing costs. In addition, particularly in Si-based hetero bipolar transistors, GaP is the only hetero emitter material with a similar lattice constant, and there is also the problem that it is difficult to realize a good hetero interface. One of the features of the manufacturing method of the present invention is that
In order to realize a heterojunction, we do not use the heteroepitaxial growth method, but instead manufacture the emitter and collector/base regions separately on different types of semiconductor substrates, and then use bonding technology after flattening the surfaces of both. be. Another feature is that after such bonding, the semiconductor substrate on the collector side, which is originally unnecessary, is removed in order to completely eliminate the collector/substrate capacitance that impedes the high-speed operation of the hetero bipolar transistor integrated circuit. It is a point. By such a manufacturing method, a semiconductor device having the structure of the present invention can be reliably realized.

〔Example〕

Hereinafter, a typical embodiment of the structure and manufacturing method of a semiconductor device using the present invention will be described using a series of process diagrams in FIGS. .

FIG. 2(a) shows a state in which a high concentration n-type GaP epitaxial layer 2 with a SL concentration of 3×10 19 cm −3 and a thickness of 2000 layers is formed on a sapphire substrate 1 with a plane orientation of (100).

On the other hand, as shown in FIG. 2(b), 2000 layers of cvo nitrogen (143) were deposited on the entire surface of the p-type Si substrate 4 with the plane orientation (100) and the impurity concentration 5 x 101san-' (7).
This was further patterned, and the substrate was etched by about 1000 people using this as a mask to form grooves.
After 500 deposits of the VD nitride film 3, the CVD nitride film 3 is directly etched by the RIB method to form a so-called side wall to obtain the structure shown in FIG. 2(b). In FIG. 2(c), RIE is performed using the CvD nitride film 3 as a mask.
The grooves are further deepened by the method to form inter-element isolation grooves with a total depth of 3000 people. Next, the lower part of the groove side wall and the groove bottom were thermally oxidized by about 900 people using the LOGO3 oxidation method.
After forming the oxide film 6 and removing the nitride film 3, the projection range is approximately 300 mm by high-acceleration ion implantation.
As ions are implanted at a peak concentration of 5.times.10.sup.19 an-', and the As is activated by lamp annealing to form the collector region 5 to obtain the structure shown in FIG. 2(c).

In FIG. 2(d), a first polysilicon layer 9 is formed by depositing boron-doped polysilicon by approximately 900 layers using the CVD method, and a second oxide film is further deposited by 900 layers using the CVD method. A film 8 is formed, and C
A second polysilicon layer 7 is formed by the VD method to obtain the structure shown in FIG. 2(d). In FIG. 2(e), the second polysilicon layer 7 is polished by a selective polishing method. Since the selective polishing method is used, the polishing rate is controlled at the upper end of the field portion of the second oxide film 8, so that a flat structure can be obtained with good control. At this time, the second oxide film 8.
The first polysilicon layer 9 is completely scraped off, and the Si substrate 4
It has stopped in the middle. Next, the Si surface is oxidized by lamp oxidation for about 400 minutes. At this time, since the first polysilicon layer 9 is exposed around the island-shaped silicon region, this portion is also oxidized. Since this portion is highly doped, if the conditions are selected, it is possible to achieve a situation where the oxidation rate is faster than that of the Si substrate 4. Therefore, next, the oxide film is etched by RIE method.

A situation can be realized in which the oxide film is completely removed on the 81 substrate 4 and the oxide film remains on the first polysilicon layer 9. Next, using the oxide film as a mask, the Si substrate 4 is
00 etching to create a groove, then selective epitaxial growth to an impurity concentration of about 200 I x 102
A base layer 10 made of silicon doped with 0an-3 boron is formed to backfill the trench.

At this time, since the first polysilicon layer 9 around the island-shaped silicon region is covered with an oxide film, selective epitaxial silicon does not grow in this portion. base layer 10
and first polysilicon layer 9 are in electrical contact with each other at a portion below the edge of the oxide film. Since selective epitaxial growth is performed with good flatness, the surface of the silicon substrate is almost flat at this time.

Next, the Si substrate 4 and the sapphire substrate 1 are bonded together by thermal bonding while aligning their in-plane axes to obtain the structure shown in FIG. Next, the Si substrate 4 is polished from below again by the selective polishing method. In this step, the first
The lower part of the oxide film 6 acts as a stopper to stop polishing (the second
Figure (b)). Since the peak position of the As concentration in the collector region 5 is aligned in advance with the upper part of the first oxide film 6, the highest concentration portion of the collector region 5 is exposed after polishing. next,
The substrate is turned upside down, the first oxide film 6 and the first polysilicon layer 9 are patterned by a lithography process, and the first polysilicon layer 9 around the device is removed.

Next, a trench groove is formed using a lithography process to perform emitter isolation, and then a third oxide film 1 is formed using a CVD method.
2, and a wiring metal layer 11 is formed by a contact hole forming process and a wiring forming process to obtain the final device structure shown in FIG.

In view of the above steps, in the step of forming the hetero bipolar device section, the mask step is only performed once for the initial pattern formation of the nitride film 3, and the device can be formed completely on a self-line. Since the thermal bonding temperature is about 400 to 500° C., impurities in the GaP emitter and Si-based collector are hardly redistributed. In addition, since Si and GaP have good lattice matching, the interface states can be significantly reduced compared to when using the conventional heteroepitaxial growth method, and therefore,
Despite the collector-top structure, it is possible to achieve an impurity profile in the base where the concentration is maximum near the interface on the emitter side, and at the same time achieve high emitter efficiency. Furthermore, an electrode can be formed in the collector region 5 at the highest concentration point, which is effective in significantly reducing collector contact resistance. Both the intrinsic base (base layer 10) and the extrinsic base (first polysilicon layer 9) are highly doped, so there is no problem in contacting them. Furthermore, since the emitter also uses the highly doped GaP epitaxial layer 2, its contact resistance is so small as to pose no problem.

GaP epitaxial layer 2 is an insulator sapphire substrate 1
Because it is on the top, the emitter capacitance can also be made very small, which is effective for high-speed operation of the device.

Further, as long as the GaP epitaxial layer can be grown over the entire surface of the substrate, microfabrication technology is not necessary for the GaP epitaxial layer. Therefore, device dimensions are determined only by the microfabrication technology used in the Si process.

It has a tremendous effect on high integration.

〔Effect of the invention〕

As described above, according to the hetero bipolar transistor of the present invention, the impurity distribution in the base is made high near the interface on the emitter side and sharply decreases toward the collector side, thereby achieving high emitter efficiency. , high carrier speed, high collector pressure resistance, and collector
Although the capacitance between the substrates has been completely eliminated and the capacitance between the emitter and the substrate has been newly added in its place, this is sufficiently small because the emitter is formed on the insulating substrate, and is similar to that when using a semi-insulating substrate. There is no abnormal interference between devices. In addition, low contact resistance has been achieved at all emitter, base, and collector terminals, making it extremely effective in forming ultra-high-speed logic integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing an embodiment of the hetero bipolar transistor of the present invention, and FIGS. 2 (a) to (g) are a series of steps showing an embodiment of the method for manufacturing the hetero bipolar transistor of the present invention. 3 are conceptual diagrams showing the principle of a hetero bipolar transistor having the structure of the present invention.

Claims (2)

[Claims] (1) An emitter layer made of a first semiconductor with a high impurity concentration formed on an insulating substrate, and an emitter layer made of a second semiconductor formed on the emitter and having a narrower forbidden band width than the first semiconductor. a base layer consisting of a high concentration region that has a conductivity type opposite to that of the high concentration region and whose concentration decreases sharply in a direction away from the interface with the high concentration region; and a base layer formed on the base layer and containing a certain amount of impurity. a collector layer made of a semiconductor having a conductivity type opposite to that of the base layer; and a collector electrode wiring layer formed on the collector layer in contact with the collector layer via an insulating layer with a window. Characteristic heterojunction semiconductor device. (2) A step of epitaxially growing a high impurity concentration region made of a first semiconductor on an insulating substrate; A trench is formed, the trench is filled halfway down with a first oxide film, and an impurity that achieves the same conductivity type as the high-concentration epitaxial region of the first semiconductor is implanted into the deepest part of the distribution by high-acceleration ion implantation. The implantation is performed so that the end of the part is deeper than the bottom of the oxide film of the element isolation trench, and the end of the shallowest part is shallower than the bottom of the element isolation layer.
A first polysilicon layer is deposited by a CVD method, and an impurity is doped into the polysilicon layer by an ion implantation method and a heat treatment to achieve a conductivity type different from that of the high concentration epitaxial region of the first semiconductor. A second oxide film is deposited to a thickness such that its top is lower than the top of the trench by a CVD method, a second polysilicon is deposited on the entire surface by a CVD method, and the second polysilicon is completely removed by a selective polishing method. At the same time, the semiconductor substrate is removed by flattening the surface, bonding the insulating substrate and the semiconductor substrate, and selectively polishing the semiconductor substrate to the interface with the first oxide film using a selective polishing method. ,
A heterojunction semiconductor device comprising the steps of forming a third oxide film by a CVD method, forming a contact hole by a lithography process, forming an electrode wiring layer, and forming an electrode wiring by a lithography process. Production method.