JPH01179367A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPH01179367A JPH01179367A JP33234587A JP33234587A JPH01179367A JP H01179367 A JPH01179367 A JP H01179367A JP 33234587 A JP33234587 A JP 33234587A JP 33234587 A JP33234587 A JP 33234587A JP H01179367 A JPH01179367 A JP H01179367A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- conductive thin
- gate electrode
- insulating film
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000010408 film Substances 0.000 claims abstract description 40
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 4
- 150000003377 silicon compounds Chemical class 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 7
- 229910021332 silicide Inorganic materials 0.000 abstract 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- IJKVHSBPTUYDLN-UHFFFAOYSA-N dihydroxy(oxo)silane Chemical compound O[Si](O)=O IJKVHSBPTUYDLN-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は薄膜トランジスタの製造方法に関し、特にゲー
ト電極がチャネル領域を形成する導電性薄膜の下部に位
置する構造で、しかもソース、ドレインの両方又はドレ
インのみをオフセットさせた薄膜トランジスタの製造方
法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a thin film transistor, and particularly relates to a method for manufacturing a thin film transistor, in particular a structure in which a gate electrode is located below a conductive thin film forming a channel region, and in which both a source, a drain, or The present invention relates to a method of manufacturing a thin film transistor in which only the drain is offset.
従来、この種のＭＯ３型薄膜トランジスタにおいては、
ドレイン耐圧の向上或いは他の電気特性の改善等を目的
として、ソース、ドレインの両方又はドレインのみをオ
フセットさせた構造が提案されている。このオフセット
構造の薄膜トランジスタの製造方法としては、例えば第
３図（ａ）乃至（ｃ）の工程が採用されている。Conventionally, in this type of MO3 type thin film transistor,
For the purpose of improving drain breakdown voltage or other electrical characteristics, structures in which both the source and drain or only the drain are offset have been proposed. As a method for manufacturing a thin film transistor having this offset structure, the steps shown in FIGS. 3(a) to 3(c), for example, are employed.
先ず、第３図（ａ）のように、絶縁性基板１上に所要パ
ターンのゲート電極２を形成し、この表面をゲート絶縁
膜３で覆う。更に、このゲート電極２の上及び絶縁性基
板１上にチャネル領域を形成する導電性薄膜４を形成す
る。First, as shown in FIG. 3(a), a gate electrode 2 of a desired pattern is formed on an insulating substrate 1, and its surface is covered with a gate insulating film 3. Further, a conductive thin film 4 is formed on the gate electrode 2 and on the insulating substrate 1 to form a channel region.
次いで、第３図（ｂ）のように、導電性薄膜４上に、ゲ
ート電極２を跨ぎかつ両側にオフセット長だけ伸ばして
イオン注入マスク材１１を形成し、これをマスクとして
前記導電性薄膜４に不純物イオンを注入する。Next, as shown in FIG. 3(b), an ion implantation mask material 11 is formed on the conductive thin film 4, spanning the gate electrode 2 and extending by an offset length on both sides, and using this as a mask, the conductive thin film 4 is Inject impurity ions into.
しかる上で、所要の熱処理を施し、かつマスク材１１を
除去することにより、第３図（Ｃ）のように、夫々オフ
セットされたソース８．ドレイン９が導電性薄膜４に形
成される。Then, by performing the necessary heat treatment and removing the mask material 11, the sources 8. and 8. are offset, respectively, as shown in FIG. A drain 9 is formed in the conductive thin film 4.
なお、ドレインのみをオフセットさせる構造の製造方法
は、第３図（ｂ）におけるイオン注入マスク材１１を、
ソース側でゲート電極２の端部に一致させ、ドレイン側
をオフセット長だけゲート電極２より外側に伸ばした上
でイオン注入を行えばよい。In addition, the manufacturing method of the structure in which only the drain is offset is as follows:
Ion implantation may be performed after aligning the source side with the end of the gate electrode 2 and extending the drain side outward from the gate electrode 2 by an offset length.
上述した従来の薄膜トランジスタの製造方法では、ソー
ス、ドレイン等をオフセットさせるためにゲート電極２
を覆うマスク材１１を形成し、このマスク材１１を用い
てイオン注入を行っているため、ゲート電極２に対する
マスク材１１の位置合わせずれが生じると、これがその
ままオフセット長の変動になる。このため、オフセット
長の再現性が低下され、高精度のオフセットｉｔを得る
ことが困難であり、オフセット長の変動により、ドレイ
ン耐圧の変動やドレイン電流、リーク電流の変動を招き
、所要の電気特性の薄膜トランジスタを得ることができ
ないという問題がある。In the conventional thin film transistor manufacturing method described above, the gate electrode 2 is used to offset the source, drain, etc.
Since a mask material 11 covering the gate electrode 2 is formed and ion implantation is performed using this mask material 11, if a misalignment of the mask material 11 with respect to the gate electrode 2 occurs, this will directly result in a variation in the offset length. For this reason, the reproducibility of the offset length is reduced, making it difficult to obtain a highly accurate offset it, and fluctuations in the offset length lead to fluctuations in drain withstand voltage, drain current, and leakage current, and the required electrical characteristics. There is a problem in that it is not possible to obtain a thin film transistor of
本発明は、オフセット長を高精度に管理した薄膜トラン
ジスタの製造方法を提供することを目的としている。An object of the present invention is to provide a method of manufacturing a thin film transistor in which offset length is managed with high precision.
本発明の薄膜トランジスタの製造方法は、絶縁膜上にゲ
ート電極及びゲート絶縁膜を形成した上で導電性薄膜を
形成し、かつゲート電極の側面位置にのみ側壁絶縁膜を
形成した上で、不純物を含む材料を選択的に形成し、か
つこの不純物を含む材料から導電性薄膜に不純物を拡散
させてソース。In the method for manufacturing a thin film transistor of the present invention, a conductive thin film is formed after forming a gate electrode and a gate insulating film on an insulating film, a sidewall insulating film is formed only on the sides of the gate electrode, and then impurities are removed. source by selectively forming a material containing impurities and diffusing impurities from this impurity-containing material into a conductive thin film.
ドレインを形成する工程を含んでいるので、側壁絶縁膜
によってソース、ドレインのオフセット長を設定でき、
再現性の良いオフセット構造を製造可能としている。Since it includes the step of forming the drain, the offset length of the source and drain can be set using the sidewall insulating film.
It is possible to manufacture offset structures with good reproducibility.
〔実施例］ 次に、本発明を図面を参照して説明する。〔Example] Next, the present invention will be explained with reference to the drawings.
（第１実施例）
第１図（ａ）乃至（ｅ）は本発明の第１の実施例を製造
工程順に示す断面図であり、ソース側及びドレイン側に
オフセットを有する下部ゲート型ＭＯ３ＴＦＴの製造方
法を示している。(First Embodiment) FIGS. 1(a) to 1(e) are cross-sectional views showing the first embodiment of the present invention in the order of manufacturing steps, in which a lower gate type MO3TFT having an offset on the source side and the drain side is manufactured. Shows how.
先ず、第１図（ａ）のように、絶縁性基板１上にゲート
電極２を選択的に形成し、このゲート電極２の表面にゲ
ート絶縁膜３を形成している。更に、この上にゲート絶
縁膜３を覆うように導電性薄膜４を形成している。First, as shown in FIG. 1(a), a gate electrode 2 is selectively formed on an insulating substrate 1, and a gate insulating film 3 is formed on the surface of this gate electrode 2. Further, a conductive thin film 4 is formed thereon so as to cover the gate insulating film 3.
次いで、第１図（ｂ）のように、前記導電性薄膜４上に
絶縁膜５を形成する。そして、この絶縁膜５を異方性エ
ツチング法でエツチングすることにより、第１図（Ｃ）
のように１、ゲート電極２の側面位置にのみ側壁絶縁膜
６を形成する。Next, as shown in FIG. 1(b), an insulating film 5 is formed on the conductive thin film 4. Then, by etching this insulating film 5 using an anisotropic etching method, as shown in FIG.
1, the sidewall insulating film 6 is formed only on the side surfaces of the gate electrode 2.
しかる後、第１図（ｄ）のように、前記導電性薄膜４及
び側壁絶縁膜６上に、導電型不純物を含有するシリコン
化合物を主成分とする溶液を回転塗布法で塗布し、約４
００°Ｃ前後の低温熱処理を行い酸化硅化物７を形成す
る。そして、この酸化硅化物７をエツチングバックし、
ゲート電極２上の導電性薄膜４の表面を露出させる。Thereafter, as shown in FIG. 1(d), a solution mainly composed of a silicon compound containing conductive impurities is applied onto the conductive thin film 4 and the sidewall insulating film 6 by a spin coating method.
A low temperature heat treatment at around 00°C is performed to form a silicon oxide 7. Then, this silicon oxide 7 is etched back,
The surface of the conductive thin film 4 on the gate electrode 2 is exposed.
更に、第１図（ｅ）のように、高温の熱処理を行って酸
化硅化物７に含有されている導電型不純物を導電性薄膜
４に拡散させ、このとき側壁絶縁膜６によってゲート電
極２の両側にオフセント領域を有したソース８．ドレイ
ン９を形成する。Furthermore, as shown in FIG. 1(e), a high-temperature heat treatment is performed to diffuse conductive impurities contained in the silicon oxide 7 into the conductive thin film 4. Source with offset regions on both sides 8. A drain 9 is formed.
したがって、この製造方法では、ソース、ドレインのオ
フセット長は側壁絶縁膜６の厚さにより管理でき、この
側壁絶縁膜６の厚さは即ち絶縁膜５の厚さであるので、
自己整合的に極めて高い精度でオフセット長を設定する
ことが可能となる。Therefore, in this manufacturing method, the offset length of the source and drain can be controlled by the thickness of the sidewall insulating film 6, and since the thickness of the sidewall insulating film 6 is the thickness of the insulating film 5,
It becomes possible to set the offset length with extremely high accuracy in a self-aligning manner.
これにより、再現性のよいオフセット構造の薄膜トラン
ジスタを得ることが可能となる。This makes it possible to obtain a thin film transistor with an offset structure with good reproducibility.
（第２実施例）
第２図（ａ）乃至（ｄ）は本発明の第２の実施例を製造
工程順に示す断面図であり、ここではドレイン側のみに
オフセットを有する下部ゲート型ＭＯ３ＴＦＴの製造方
法を示している。なお、第１図と同一部分には同一符号
を付しである。(Second Embodiment) FIGS. 2(a) to 2(d) are cross-sectional views showing the second embodiment of the present invention in the order of manufacturing steps. Shows how. Note that the same parts as in FIG. 1 are given the same reference numerals.
先ず、第２図（ａ）に示すように、第１実施例の第１図
（ａ）乃至（ｃ）と同一の工程により、絶縁性基板１上
にゲート電極２．ゲート絶縁膜３゜導電性薄膜４及び側
壁絶縁膜６を形成する。First, as shown in FIG. 2(a), a gate electrode 2. A gate insulating film 3. A conductive thin film 4 and a sidewall insulating film 6 are formed.
この後、第２図（ｂ）のように、ドレイン側のみをフォ
トレジスト１０でマスクした上で、ソース側の側壁絶縁
膜６をのみエツチング除去する。Thereafter, as shown in FIG. 2(b), only the drain side is masked with a photoresist 10, and only the sidewall insulating film 6 on the source side is removed by etching.
しかる上で、第２図（ｃ）のように、導電型不純物を含
有するシリコン化合物を主成分とする溶液を回転塗布法
で塗布し、約４００°Ｃ前後の低温熱処理を行い酸化硅
化物７を形成する。そして、この酸化硅化物７をエツチ
ングバックし、ゲート電極２上の導電性薄膜４の表面を
露出させる。Then, as shown in FIG. 2(c), a solution mainly composed of a silicon compound containing conductive impurities is applied by a spin coating method, and a low-temperature heat treatment is performed at about 400°C to form a silicon oxide 7. form. Then, the silicon oxide 7 is etched back to expose the surface of the conductive thin film 4 on the gate electrode 2.
更に、第２図（ｄ）のように、高温の熱処理を行って酸
化硅化物７に含有されている導電型不純物を導電性薄膜
４に拡散させ、ゲート電極２の両側にソース８．ドレイ
ン９を形成する。Furthermore, as shown in FIG. 2(d), high-temperature heat treatment is performed to diffuse conductive impurities contained in the silicon oxide 7 into the conductive thin film 4, and sources 8. are formed on both sides of the gate electrode 2. A drain 9 is formed.
このとき、ドレイン側では側壁絶縁膜６によりオフセッ
トされたドレイン９が形成され、ソース側では側壁絶縁
膜が存在しないため、ゲート電極２に沿ってソース８が
形成されることになる。At this time, a drain 9 offset by the sidewall insulating film 6 is formed on the drain side, and a source 8 is formed along the gate electrode 2 since there is no sidewall insulating film on the source side.
なお、前記各実施例では、ゲート電極２を絶縁性基Ｆｉ
ｌ上に形成しているが、−導電型の半導体基板上に形成
した絶縁膜上にゲート電極を形成する場合でも本発明を
適用できることは言うまでもない。In each of the above embodiments, the gate electrode 2 is formed using an insulating group Fi.
However, it goes without saying that the present invention can also be applied to the case where the gate electrode is formed on an insulating film formed on a -conductivity type semiconductor substrate.
（発明の効果〕
以上説明したように本発明は、ゲート電極の側面位置に
のみ側壁絶縁膜を形成した上で、不純物を含む材料を選
択的に形成し、かつこの不純物を含む材料から導電性薄
膜に不純物を拡散させてソース、ドレインを形成する工
程を含んでいるので、側壁絶縁膜によって自己整合的に
ソース、ドレインのオフセット長を設定でき、再現性の
良いオフセント構造の薄膜トランジスタを製造できる効
果がある。(Effects of the Invention) As explained above, the present invention forms a sidewall insulating film only on the side surfaces of a gate electrode, selectively forms a material containing impurities, and conducts the material from the material containing impurities. Since it includes the process of forming the source and drain by diffusing impurities into the thin film, the offset length of the source and drain can be set in a self-aligned manner using the sidewall insulating film, making it possible to manufacture thin film transistors with an offset structure with good reproducibility. There is.
第１図（ａ）乃至（ｅ）は本発明の第１実施例を製造工
程順に示す縦断面図、第２図（ａ ）乃至（ｄ）は本発
明の第２実施例を製造工程順に示す縦断面図、第３図（
ａ）乃至（Ｃ）は従来の製造方法を工程順に示す縦断面
図である。
１・・・絶縁性基板、２・・・ゲート電極、３・・・ゲ
ート絶縁膜、４・・・導電性薄膜、５・・・絶縁膜、６
・・・側壁絶縁膜、７・・・酸化硅化物、８・・・ソー
ス、９・・・ドレイン、１０・・・フォトレジスト、１
１・・・マスク材。
第３図
１ＪＩＩｌｌｊFIGS. 1(a) to (e) are longitudinal sectional views showing a first embodiment of the present invention in the order of manufacturing steps, and FIGS. 2(a) to (d) show a second embodiment of the present invention in the order of manufacturing steps. Longitudinal sectional view, Figure 3 (
a) to (C) are vertical cross-sectional views showing a conventional manufacturing method in the order of steps. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Gate electrode, 3... Gate insulating film, 4... Conductive thin film, 5... Insulating film, 6
...Side wall insulating film, 7...Silicate oxide, 8...Source, 9...Drain, 10...Photoresist, 1
1...Mask material. Figure 3 1JIIllj
Claims (1)
ゲート絶縁膜で覆う工程と、このゲート絶縁膜を含む前
記絶縁膜の上に導電性薄膜を形成する工程と、全面に絶
縁膜を形成した上でこれを異方性エッチングして前記ゲ
ート電極の側面位置にのみ絶縁膜を側壁絶縁膜として残
す工程と、全面に不純物を含む材料を塗布しかつこれを
エッチングバックして前記ゲート電極上の導電性薄膜を
露呈させる工程と、熱処理を施して前記不純物を含む材
料から導電性薄膜に不純物を拡散させてソース、ドレイ
ンを形成する工程を含むことを特徴とする薄膜トランジ
スタの製造方法。(1) A step of forming a gate electrode on an insulating film and covering the surface with a gate insulating film, a step of forming a conductive thin film on the insulating film including the gate insulating film, and a step of forming an insulating film on the entire surface. is formed and anisotropically etched to leave an insulating film as a sidewall insulating film only at the side positions of the gate electrode, and a material containing impurities is applied to the entire surface and etched back to form the gate electrode. A method for manufacturing a thin film transistor, comprising the steps of: exposing a conductive thin film on an electrode; and performing heat treatment to diffuse impurities from the impurity-containing material into the conductive thin film to form a source and a drain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33234587A JP2541259B2 (en) | 1987-12-30 | 1987-12-30 | Method for manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33234587A JP2541259B2 (en) | 1987-12-30 | 1987-12-30 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01179367A true JPH01179367A (en) | 1989-07-17 |
| JP2541259B2 JP2541259B2 (en) | 1996-10-09 |
Family
ID=18253923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33234587A Expired - Lifetime JP2541259B2 (en) | 1987-12-30 | 1987-12-30 | Method for manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2541259B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04338650A (en) * | 1991-05-15 | 1992-11-25 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH05152571A (en) * | 1991-11-27 | 1993-06-18 | Sharp Corp | Resistor |
| EP0565231A2 (en) * | 1992-03-31 | 1993-10-13 | STMicroelectronics, Inc. | Method of fabricating a polysilicon thin film transistor |
| JPH07142734A (en) * | 1993-05-20 | 1995-06-02 | Gold Star Electron Co Ltd | Thin film transistor and manufacture thereof |
| JPH07147415A (en) * | 1993-06-21 | 1995-06-06 | Gold Star Electron Co Ltd | Thin film transistor and manufacture thereof |
-
1987
- 1987-12-30 JP JP33234587A patent/JP2541259B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04338650A (en) * | 1991-05-15 | 1992-11-25 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH05152571A (en) * | 1991-11-27 | 1993-06-18 | Sharp Corp | Resistor |
| EP0565231A2 (en) * | 1992-03-31 | 1993-10-13 | STMicroelectronics, Inc. | Method of fabricating a polysilicon thin film transistor |
| EP0565231A3 (en) * | 1992-03-31 | 1996-11-20 | Sgs Thomson Microelectronics | Method of fabricating a polysilicon thin film transistor |
| JPH07142734A (en) * | 1993-05-20 | 1995-06-02 | Gold Star Electron Co Ltd | Thin film transistor and manufacture thereof |
| JPH07147415A (en) * | 1993-06-21 | 1995-06-06 | Gold Star Electron Co Ltd | Thin film transistor and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2541259B2 (en) | 1996-10-09 |
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